1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/syscore_ops.h> 60 61 #include <asm/acpi.h> 62 #include <asm/desc.h> 63 #include <asm/nmi.h> 64 #include <asm/irq.h> 65 #include <asm/realmode.h> 66 #include <asm/cpu.h> 67 #include <asm/numa.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/misc.h> 79 #include <asm/qspinlock.h> 80 #include <asm/intel-family.h> 81 #include <asm/cpu_device_id.h> 82 #include <asm/spec-ctrl.h> 83 #include <asm/hw_irq.h> 84 #include <asm/stackprotector.h> 85 86 #ifdef CONFIG_ACPI_CPPC_LIB 87 #include <acpi/cppc_acpi.h> 88 #endif 89 90 /* representing HT siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 93 94 /* representing HT and core siblings of each logical CPU */ 95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 96 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 97 98 /* representing HT, core, and die siblings of each logical CPU */ 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 100 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 101 102 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 103 104 /* Per CPU bogomips and other parameters */ 105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 106 EXPORT_PER_CPU_SYMBOL(cpu_info); 107 108 /* Logical package management. We might want to allocate that dynamically */ 109 unsigned int __max_logical_packages __read_mostly; 110 EXPORT_SYMBOL(__max_logical_packages); 111 static unsigned int logical_packages __read_mostly; 112 static unsigned int logical_die __read_mostly; 113 114 /* Maximum number of SMT threads on any online core */ 115 int __read_mostly __max_smt_threads = 1; 116 117 /* Flag to indicate if a complete sched domain rebuild is required */ 118 bool x86_topology_update; 119 120 int arch_update_cpu_topology(void) 121 { 122 int retval = x86_topology_update; 123 124 x86_topology_update = false; 125 return retval; 126 } 127 128 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 129 { 130 unsigned long flags; 131 132 spin_lock_irqsave(&rtc_lock, flags); 133 CMOS_WRITE(0xa, 0xf); 134 spin_unlock_irqrestore(&rtc_lock, flags); 135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 136 start_eip >> 4; 137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 138 start_eip & 0xf; 139 } 140 141 static inline void smpboot_restore_warm_reset_vector(void) 142 { 143 unsigned long flags; 144 145 /* 146 * Paranoid: Set warm reset code and vector here back 147 * to default values. 148 */ 149 spin_lock_irqsave(&rtc_lock, flags); 150 CMOS_WRITE(0, 0xf); 151 spin_unlock_irqrestore(&rtc_lock, flags); 152 153 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 154 } 155 156 static void init_freq_invariance(bool secondary, bool cppc_ready); 157 158 /* 159 * Report back to the Boot Processor during boot time or to the caller processor 160 * during CPU online. 161 */ 162 static void smp_callin(void) 163 { 164 int cpuid; 165 166 /* 167 * If waken up by an INIT in an 82489DX configuration 168 * cpu_callout_mask guarantees we don't get here before 169 * an INIT_deassert IPI reaches our local APIC, so it is 170 * now safe to touch our local APIC. 171 */ 172 cpuid = smp_processor_id(); 173 174 /* 175 * the boot CPU has finished the init stage and is spinning 176 * on callin_map until we finish. We are free to set up this 177 * CPU, first the APIC. (this is probably redundant on most 178 * boards) 179 */ 180 apic_ap_setup(); 181 182 /* 183 * Save our processor parameters. Note: this information 184 * is needed for clock calibration. 185 */ 186 smp_store_cpu_info(cpuid); 187 188 /* 189 * The topology information must be up to date before 190 * calibrate_delay() and notify_cpu_starting(). 191 */ 192 set_cpu_sibling_map(raw_smp_processor_id()); 193 194 init_freq_invariance(true, false); 195 196 /* 197 * Get our bogomips. 198 * Update loops_per_jiffy in cpu_data. Previous call to 199 * smp_store_cpu_info() stored a value that is close but not as 200 * accurate as the value just calculated. 201 */ 202 calibrate_delay(); 203 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 204 pr_debug("Stack at about %p\n", &cpuid); 205 206 wmb(); 207 208 notify_cpu_starting(cpuid); 209 210 /* 211 * Allow the master to continue. 212 */ 213 cpumask_set_cpu(cpuid, cpu_callin_mask); 214 } 215 216 static int cpu0_logical_apicid; 217 static int enable_start_cpu0; 218 /* 219 * Activate a secondary processor. 220 */ 221 static void notrace start_secondary(void *unused) 222 { 223 /* 224 * Don't put *anything* except direct CPU state initialization 225 * before cpu_init(), SMP booting is too fragile that we want to 226 * limit the things done here to the most necessary things. 227 */ 228 cr4_init(); 229 230 #ifdef CONFIG_X86_32 231 /* switch away from the initial page table */ 232 load_cr3(swapper_pg_dir); 233 __flush_tlb_all(); 234 #endif 235 cpu_init_exception_handling(); 236 cpu_init(); 237 rcu_cpu_starting(raw_smp_processor_id()); 238 x86_cpuinit.early_percpu_clock_init(); 239 preempt_disable(); 240 smp_callin(); 241 242 enable_start_cpu0 = 0; 243 244 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 245 barrier(); 246 /* 247 * Check TSC synchronization with the boot CPU: 248 */ 249 check_tsc_sync_target(); 250 251 speculative_store_bypass_ht_init(); 252 253 /* 254 * Lock vector_lock, set CPU online and bring the vector 255 * allocator online. Online must be set with vector_lock held 256 * to prevent a concurrent irq setup/teardown from seeing a 257 * half valid vector space. 258 */ 259 lock_vector_lock(); 260 set_cpu_online(smp_processor_id(), true); 261 lapic_online(); 262 unlock_vector_lock(); 263 cpu_set_state_online(smp_processor_id()); 264 x86_platform.nmi_init(); 265 266 /* enable local interrupts */ 267 local_irq_enable(); 268 269 x86_cpuinit.setup_percpu_clockev(); 270 271 wmb(); 272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 273 } 274 275 /** 276 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 277 * @cpu: CPU to check 278 */ 279 bool topology_is_primary_thread(unsigned int cpu) 280 { 281 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 282 } 283 284 /** 285 * topology_smt_supported - Check whether SMT is supported by the CPUs 286 */ 287 bool topology_smt_supported(void) 288 { 289 return smp_num_siblings > 1; 290 } 291 292 /** 293 * topology_phys_to_logical_pkg - Map a physical package id to a logical 294 * 295 * Returns logical package id or -1 if not found 296 */ 297 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 298 { 299 int cpu; 300 301 for_each_possible_cpu(cpu) { 302 struct cpuinfo_x86 *c = &cpu_data(cpu); 303 304 if (c->initialized && c->phys_proc_id == phys_pkg) 305 return c->logical_proc_id; 306 } 307 return -1; 308 } 309 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 310 /** 311 * topology_phys_to_logical_die - Map a physical die id to logical 312 * 313 * Returns logical die id or -1 if not found 314 */ 315 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 316 { 317 int cpu; 318 int proc_id = cpu_data(cur_cpu).phys_proc_id; 319 320 for_each_possible_cpu(cpu) { 321 struct cpuinfo_x86 *c = &cpu_data(cpu); 322 323 if (c->initialized && c->cpu_die_id == die_id && 324 c->phys_proc_id == proc_id) 325 return c->logical_die_id; 326 } 327 return -1; 328 } 329 EXPORT_SYMBOL(topology_phys_to_logical_die); 330 331 /** 332 * topology_update_package_map - Update the physical to logical package map 333 * @pkg: The physical package id as retrieved via CPUID 334 * @cpu: The cpu for which this is updated 335 */ 336 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 337 { 338 int new; 339 340 /* Already available somewhere? */ 341 new = topology_phys_to_logical_pkg(pkg); 342 if (new >= 0) 343 goto found; 344 345 new = logical_packages++; 346 if (new != pkg) { 347 pr_info("CPU %u Converting physical %u to logical package %u\n", 348 cpu, pkg, new); 349 } 350 found: 351 cpu_data(cpu).logical_proc_id = new; 352 return 0; 353 } 354 /** 355 * topology_update_die_map - Update the physical to logical die map 356 * @die: The die id as retrieved via CPUID 357 * @cpu: The cpu for which this is updated 358 */ 359 int topology_update_die_map(unsigned int die, unsigned int cpu) 360 { 361 int new; 362 363 /* Already available somewhere? */ 364 new = topology_phys_to_logical_die(die, cpu); 365 if (new >= 0) 366 goto found; 367 368 new = logical_die++; 369 if (new != die) { 370 pr_info("CPU %u Converting physical %u to logical die %u\n", 371 cpu, die, new); 372 } 373 found: 374 cpu_data(cpu).logical_die_id = new; 375 return 0; 376 } 377 378 void __init smp_store_boot_cpu_info(void) 379 { 380 int id = 0; /* CPU 0 */ 381 struct cpuinfo_x86 *c = &cpu_data(id); 382 383 *c = boot_cpu_data; 384 c->cpu_index = id; 385 topology_update_package_map(c->phys_proc_id, id); 386 topology_update_die_map(c->cpu_die_id, id); 387 c->initialized = true; 388 } 389 390 /* 391 * The bootstrap kernel entry code has set these up. Save them for 392 * a given CPU 393 */ 394 void smp_store_cpu_info(int id) 395 { 396 struct cpuinfo_x86 *c = &cpu_data(id); 397 398 /* Copy boot_cpu_data only on the first bringup */ 399 if (!c->initialized) 400 *c = boot_cpu_data; 401 c->cpu_index = id; 402 /* 403 * During boot time, CPU0 has this setup already. Save the info when 404 * bringing up AP or offlined CPU0. 405 */ 406 identify_secondary_cpu(c); 407 c->initialized = true; 408 } 409 410 static bool 411 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 412 { 413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 414 415 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 416 } 417 418 static bool 419 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 420 { 421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 422 423 return !WARN_ONCE(!topology_same_node(c, o), 424 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 425 "[node: %d != %d]. Ignoring dependency.\n", 426 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 427 } 428 429 #define link_mask(mfunc, c1, c2) \ 430 do { \ 431 cpumask_set_cpu((c1), mfunc(c2)); \ 432 cpumask_set_cpu((c2), mfunc(c1)); \ 433 } while (0) 434 435 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 436 { 437 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 438 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 439 440 if (c->phys_proc_id == o->phys_proc_id && 441 c->cpu_die_id == o->cpu_die_id && 442 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 443 if (c->cpu_core_id == o->cpu_core_id) 444 return topology_sane(c, o, "smt"); 445 446 if ((c->cu_id != 0xff) && 447 (o->cu_id != 0xff) && 448 (c->cu_id == o->cu_id)) 449 return topology_sane(c, o, "smt"); 450 } 451 452 } else if (c->phys_proc_id == o->phys_proc_id && 453 c->cpu_die_id == o->cpu_die_id && 454 c->cpu_core_id == o->cpu_core_id) { 455 return topology_sane(c, o, "smt"); 456 } 457 458 return false; 459 } 460 461 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 462 { 463 if (c->phys_proc_id == o->phys_proc_id && 464 c->cpu_die_id == o->cpu_die_id) 465 return true; 466 return false; 467 } 468 469 /* 470 * Unlike the other levels, we do not enforce keeping a 471 * multicore group inside a NUMA node. If this happens, we will 472 * discard the MC level of the topology later. 473 */ 474 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 475 { 476 if (c->phys_proc_id == o->phys_proc_id) 477 return true; 478 return false; 479 } 480 481 /* 482 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 483 * 484 * Any Intel CPU that has multiple nodes per package and does not 485 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 486 * 487 * When in SNC mode, these CPUs enumerate an LLC that is shared 488 * by multiple NUMA nodes. The LLC is shared for off-package data 489 * access but private to the NUMA node (half of the package) for 490 * on-package access. CPUID (the source of the information about 491 * the LLC) can only enumerate the cache as shared or unshared, 492 * but not this particular configuration. 493 */ 494 495 static const struct x86_cpu_id intel_cod_cpu[] = { 496 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 497 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 498 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 499 {} 500 }; 501 502 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 503 { 504 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 505 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 506 bool intel_snc = id && id->driver_data; 507 508 /* Do not match if we do not have a valid APICID for cpu: */ 509 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 510 return false; 511 512 /* Do not match if LLC id does not match: */ 513 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 514 return false; 515 516 /* 517 * Allow the SNC topology without warning. Return of false 518 * means 'c' does not share the LLC of 'o'. This will be 519 * reflected to userspace. 520 */ 521 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 522 return false; 523 524 return topology_sane(c, o, "llc"); 525 } 526 527 528 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 529 static inline int x86_sched_itmt_flags(void) 530 { 531 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 532 } 533 534 #ifdef CONFIG_SCHED_MC 535 static int x86_core_flags(void) 536 { 537 return cpu_core_flags() | x86_sched_itmt_flags(); 538 } 539 #endif 540 #ifdef CONFIG_SCHED_SMT 541 static int x86_smt_flags(void) 542 { 543 return cpu_smt_flags() | x86_sched_itmt_flags(); 544 } 545 #endif 546 #endif 547 548 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 549 #ifdef CONFIG_SCHED_SMT 550 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 551 #endif 552 #ifdef CONFIG_SCHED_MC 553 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 554 #endif 555 { NULL, }, 556 }; 557 558 static struct sched_domain_topology_level x86_topology[] = { 559 #ifdef CONFIG_SCHED_SMT 560 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 561 #endif 562 #ifdef CONFIG_SCHED_MC 563 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 564 #endif 565 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 566 { NULL, }, 567 }; 568 569 /* 570 * Set if a package/die has multiple NUMA nodes inside. 571 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 572 * Sub-NUMA Clustering have this. 573 */ 574 static bool x86_has_numa_in_package; 575 576 void set_cpu_sibling_map(int cpu) 577 { 578 bool has_smt = smp_num_siblings > 1; 579 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 580 struct cpuinfo_x86 *c = &cpu_data(cpu); 581 struct cpuinfo_x86 *o; 582 int i, threads; 583 584 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 585 586 if (!has_mp) { 587 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 588 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 589 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 590 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 591 c->booted_cores = 1; 592 return; 593 } 594 595 for_each_cpu(i, cpu_sibling_setup_mask) { 596 o = &cpu_data(i); 597 598 if (match_pkg(c, o) && !topology_same_node(c, o)) 599 x86_has_numa_in_package = true; 600 601 if ((i == cpu) || (has_smt && match_smt(c, o))) 602 link_mask(topology_sibling_cpumask, cpu, i); 603 604 if ((i == cpu) || (has_mp && match_llc(c, o))) 605 link_mask(cpu_llc_shared_mask, cpu, i); 606 607 if ((i == cpu) || (has_mp && match_die(c, o))) 608 link_mask(topology_die_cpumask, cpu, i); 609 } 610 611 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 612 if (threads > __max_smt_threads) 613 __max_smt_threads = threads; 614 615 /* 616 * This needs a separate iteration over the cpus because we rely on all 617 * topology_sibling_cpumask links to be set-up. 618 */ 619 for_each_cpu(i, cpu_sibling_setup_mask) { 620 o = &cpu_data(i); 621 622 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 623 link_mask(topology_core_cpumask, cpu, i); 624 625 /* 626 * Does this new cpu bringup a new core? 627 */ 628 if (threads == 1) { 629 /* 630 * for each core in package, increment 631 * the booted_cores for this new cpu 632 */ 633 if (cpumask_first( 634 topology_sibling_cpumask(i)) == i) 635 c->booted_cores++; 636 /* 637 * increment the core count for all 638 * the other cpus in this package 639 */ 640 if (i != cpu) 641 cpu_data(i).booted_cores++; 642 } else if (i != cpu && !c->booted_cores) 643 c->booted_cores = cpu_data(i).booted_cores; 644 } 645 } 646 } 647 648 /* maps the cpu to the sched domain representing multi-core */ 649 const struct cpumask *cpu_coregroup_mask(int cpu) 650 { 651 return cpu_llc_shared_mask(cpu); 652 } 653 654 static void impress_friends(void) 655 { 656 int cpu; 657 unsigned long bogosum = 0; 658 /* 659 * Allow the user to impress friends. 660 */ 661 pr_debug("Before bogomips\n"); 662 for_each_possible_cpu(cpu) 663 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 664 bogosum += cpu_data(cpu).loops_per_jiffy; 665 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 666 num_online_cpus(), 667 bogosum/(500000/HZ), 668 (bogosum/(5000/HZ))%100); 669 670 pr_debug("Before bogocount - setting activated=1\n"); 671 } 672 673 void __inquire_remote_apic(int apicid) 674 { 675 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 676 const char * const names[] = { "ID", "VERSION", "SPIV" }; 677 int timeout; 678 u32 status; 679 680 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 681 682 for (i = 0; i < ARRAY_SIZE(regs); i++) { 683 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 684 685 /* 686 * Wait for idle. 687 */ 688 status = safe_apic_wait_icr_idle(); 689 if (status) 690 pr_cont("a previous APIC delivery may have failed\n"); 691 692 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 693 694 timeout = 0; 695 do { 696 udelay(100); 697 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 698 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 699 700 switch (status) { 701 case APIC_ICR_RR_VALID: 702 status = apic_read(APIC_RRR); 703 pr_cont("%08x\n", status); 704 break; 705 default: 706 pr_cont("failed\n"); 707 } 708 } 709 } 710 711 /* 712 * The Multiprocessor Specification 1.4 (1997) example code suggests 713 * that there should be a 10ms delay between the BSP asserting INIT 714 * and de-asserting INIT, when starting a remote processor. 715 * But that slows boot and resume on modern processors, which include 716 * many cores and don't require that delay. 717 * 718 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 719 * Modern processor families are quirked to remove the delay entirely. 720 */ 721 #define UDELAY_10MS_DEFAULT 10000 722 723 static unsigned int init_udelay = UINT_MAX; 724 725 static int __init cpu_init_udelay(char *str) 726 { 727 get_option(&str, &init_udelay); 728 729 return 0; 730 } 731 early_param("cpu_init_udelay", cpu_init_udelay); 732 733 static void __init smp_quirk_init_udelay(void) 734 { 735 /* if cmdline changed it from default, leave it alone */ 736 if (init_udelay != UINT_MAX) 737 return; 738 739 /* if modern processor, use no delay */ 740 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 741 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 742 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 743 init_udelay = 0; 744 return; 745 } 746 /* else, use legacy delay */ 747 init_udelay = UDELAY_10MS_DEFAULT; 748 } 749 750 /* 751 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 752 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 753 * won't ... remember to clear down the APIC, etc later. 754 */ 755 int 756 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 757 { 758 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 759 unsigned long send_status, accept_status = 0; 760 int maxlvt; 761 762 /* Target chip */ 763 /* Boot on the stack */ 764 /* Kick the second */ 765 apic_icr_write(APIC_DM_NMI | dm, apicid); 766 767 pr_debug("Waiting for send to finish...\n"); 768 send_status = safe_apic_wait_icr_idle(); 769 770 /* 771 * Give the other CPU some time to accept the IPI. 772 */ 773 udelay(200); 774 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 775 maxlvt = lapic_get_maxlvt(); 776 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 777 apic_write(APIC_ESR, 0); 778 accept_status = (apic_read(APIC_ESR) & 0xEF); 779 } 780 pr_debug("NMI sent\n"); 781 782 if (send_status) 783 pr_err("APIC never delivered???\n"); 784 if (accept_status) 785 pr_err("APIC delivery error (%lx)\n", accept_status); 786 787 return (send_status | accept_status); 788 } 789 790 static int 791 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 792 { 793 unsigned long send_status = 0, accept_status = 0; 794 int maxlvt, num_starts, j; 795 796 maxlvt = lapic_get_maxlvt(); 797 798 /* 799 * Be paranoid about clearing APIC errors. 800 */ 801 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 802 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 803 apic_write(APIC_ESR, 0); 804 apic_read(APIC_ESR); 805 } 806 807 pr_debug("Asserting INIT\n"); 808 809 /* 810 * Turn INIT on target chip 811 */ 812 /* 813 * Send IPI 814 */ 815 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 816 phys_apicid); 817 818 pr_debug("Waiting for send to finish...\n"); 819 send_status = safe_apic_wait_icr_idle(); 820 821 udelay(init_udelay); 822 823 pr_debug("Deasserting INIT\n"); 824 825 /* Target chip */ 826 /* Send IPI */ 827 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 828 829 pr_debug("Waiting for send to finish...\n"); 830 send_status = safe_apic_wait_icr_idle(); 831 832 mb(); 833 834 /* 835 * Should we send STARTUP IPIs ? 836 * 837 * Determine this based on the APIC version. 838 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 839 */ 840 if (APIC_INTEGRATED(boot_cpu_apic_version)) 841 num_starts = 2; 842 else 843 num_starts = 0; 844 845 /* 846 * Run STARTUP IPI loop. 847 */ 848 pr_debug("#startup loops: %d\n", num_starts); 849 850 for (j = 1; j <= num_starts; j++) { 851 pr_debug("Sending STARTUP #%d\n", j); 852 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 853 apic_write(APIC_ESR, 0); 854 apic_read(APIC_ESR); 855 pr_debug("After apic_write\n"); 856 857 /* 858 * STARTUP IPI 859 */ 860 861 /* Target chip */ 862 /* Boot on the stack */ 863 /* Kick the second */ 864 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 865 phys_apicid); 866 867 /* 868 * Give the other CPU some time to accept the IPI. 869 */ 870 if (init_udelay == 0) 871 udelay(10); 872 else 873 udelay(300); 874 875 pr_debug("Startup point 1\n"); 876 877 pr_debug("Waiting for send to finish...\n"); 878 send_status = safe_apic_wait_icr_idle(); 879 880 /* 881 * Give the other CPU some time to accept the IPI. 882 */ 883 if (init_udelay == 0) 884 udelay(10); 885 else 886 udelay(200); 887 888 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 889 apic_write(APIC_ESR, 0); 890 accept_status = (apic_read(APIC_ESR) & 0xEF); 891 if (send_status || accept_status) 892 break; 893 } 894 pr_debug("After Startup\n"); 895 896 if (send_status) 897 pr_err("APIC never delivered???\n"); 898 if (accept_status) 899 pr_err("APIC delivery error (%lx)\n", accept_status); 900 901 return (send_status | accept_status); 902 } 903 904 /* reduce the number of lines printed when booting a large cpu count system */ 905 static void announce_cpu(int cpu, int apicid) 906 { 907 static int current_node = NUMA_NO_NODE; 908 int node = early_cpu_to_node(cpu); 909 static int width, node_width; 910 911 if (!width) 912 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 913 914 if (!node_width) 915 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 916 917 if (cpu == 1) 918 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 919 920 if (system_state < SYSTEM_RUNNING) { 921 if (node != current_node) { 922 if (current_node > (-1)) 923 pr_cont("\n"); 924 current_node = node; 925 926 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 927 node_width - num_digits(node), " ", node); 928 } 929 930 /* Add padding for the BSP */ 931 if (cpu == 1) 932 pr_cont("%*s", width + 1, " "); 933 934 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 935 936 } else 937 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 938 node, cpu, apicid); 939 } 940 941 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 942 { 943 int cpu; 944 945 cpu = smp_processor_id(); 946 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 947 return NMI_HANDLED; 948 949 return NMI_DONE; 950 } 951 952 /* 953 * Wake up AP by INIT, INIT, STARTUP sequence. 954 * 955 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 956 * boot-strap code which is not a desired behavior for waking up BSP. To 957 * void the boot-strap code, wake up CPU0 by NMI instead. 958 * 959 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 960 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 961 * We'll change this code in the future to wake up hard offlined CPU0 if 962 * real platform and request are available. 963 */ 964 static int 965 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 966 int *cpu0_nmi_registered) 967 { 968 int id; 969 int boot_error; 970 971 preempt_disable(); 972 973 /* 974 * Wake up AP by INIT, INIT, STARTUP sequence. 975 */ 976 if (cpu) { 977 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 978 goto out; 979 } 980 981 /* 982 * Wake up BSP by nmi. 983 * 984 * Register a NMI handler to help wake up CPU0. 985 */ 986 boot_error = register_nmi_handler(NMI_LOCAL, 987 wakeup_cpu0_nmi, 0, "wake_cpu0"); 988 989 if (!boot_error) { 990 enable_start_cpu0 = 1; 991 *cpu0_nmi_registered = 1; 992 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; 993 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 994 } 995 996 out: 997 preempt_enable(); 998 999 return boot_error; 1000 } 1001 1002 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1003 { 1004 int ret; 1005 1006 /* Just in case we booted with a single CPU. */ 1007 alternatives_enable_smp(); 1008 1009 per_cpu(current_task, cpu) = idle; 1010 cpu_init_stack_canary(cpu, idle); 1011 1012 /* Initialize the interrupt stack(s) */ 1013 ret = irq_init_percpu_irqstack(cpu); 1014 if (ret) 1015 return ret; 1016 1017 #ifdef CONFIG_X86_32 1018 /* Stack for startup_32 can be just as for start_secondary onwards */ 1019 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 1020 #else 1021 initial_gs = per_cpu_offset(cpu); 1022 #endif 1023 return 0; 1024 } 1025 1026 /* 1027 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1028 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1029 * Returns zero if CPU booted OK, else error code from 1030 * ->wakeup_secondary_cpu. 1031 */ 1032 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1033 int *cpu0_nmi_registered) 1034 { 1035 /* start_ip had better be page-aligned! */ 1036 unsigned long start_ip = real_mode_header->trampoline_start; 1037 1038 unsigned long boot_error = 0; 1039 unsigned long timeout; 1040 1041 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1042 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1043 initial_code = (unsigned long)start_secondary; 1044 initial_stack = idle->thread.sp; 1045 1046 /* Enable the espfix hack for this CPU */ 1047 init_espfix_ap(cpu); 1048 1049 /* So we see what's up */ 1050 announce_cpu(cpu, apicid); 1051 1052 /* 1053 * This grunge runs the startup process for 1054 * the targeted processor. 1055 */ 1056 1057 if (x86_platform.legacy.warm_reset) { 1058 1059 pr_debug("Setting warm reset code and vector.\n"); 1060 1061 smpboot_setup_warm_reset_vector(start_ip); 1062 /* 1063 * Be paranoid about clearing APIC errors. 1064 */ 1065 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1066 apic_write(APIC_ESR, 0); 1067 apic_read(APIC_ESR); 1068 } 1069 } 1070 1071 /* 1072 * AP might wait on cpu_callout_mask in cpu_init() with 1073 * cpu_initialized_mask set if previous attempt to online 1074 * it timed-out. Clear cpu_initialized_mask so that after 1075 * INIT/SIPI it could start with a clean state. 1076 */ 1077 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1078 smp_mb(); 1079 1080 /* 1081 * Wake up a CPU in difference cases: 1082 * - Use the method in the APIC driver if it's defined 1083 * Otherwise, 1084 * - Use an INIT boot APIC message for APs or NMI for BSP. 1085 */ 1086 if (apic->wakeup_secondary_cpu) 1087 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1088 else 1089 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1090 cpu0_nmi_registered); 1091 1092 if (!boot_error) { 1093 /* 1094 * Wait 10s total for first sign of life from AP 1095 */ 1096 boot_error = -1; 1097 timeout = jiffies + 10*HZ; 1098 while (time_before(jiffies, timeout)) { 1099 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1100 /* 1101 * Tell AP to proceed with initialization 1102 */ 1103 cpumask_set_cpu(cpu, cpu_callout_mask); 1104 boot_error = 0; 1105 break; 1106 } 1107 schedule(); 1108 } 1109 } 1110 1111 if (!boot_error) { 1112 /* 1113 * Wait till AP completes initial initialization 1114 */ 1115 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1116 /* 1117 * Allow other tasks to run while we wait for the 1118 * AP to come online. This also gives a chance 1119 * for the MTRR work(triggered by the AP coming online) 1120 * to be completed in the stop machine context. 1121 */ 1122 schedule(); 1123 } 1124 } 1125 1126 if (x86_platform.legacy.warm_reset) { 1127 /* 1128 * Cleanup possible dangling ends... 1129 */ 1130 smpboot_restore_warm_reset_vector(); 1131 } 1132 1133 return boot_error; 1134 } 1135 1136 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1137 { 1138 int apicid = apic->cpu_present_to_apicid(cpu); 1139 int cpu0_nmi_registered = 0; 1140 unsigned long flags; 1141 int err, ret = 0; 1142 1143 lockdep_assert_irqs_enabled(); 1144 1145 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1146 1147 if (apicid == BAD_APICID || 1148 !physid_isset(apicid, phys_cpu_present_map) || 1149 !apic->apic_id_valid(apicid)) { 1150 pr_err("%s: bad cpu %d\n", __func__, cpu); 1151 return -EINVAL; 1152 } 1153 1154 /* 1155 * Already booted CPU? 1156 */ 1157 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1158 pr_debug("do_boot_cpu %d Already started\n", cpu); 1159 return -ENOSYS; 1160 } 1161 1162 /* 1163 * Save current MTRR state in case it was changed since early boot 1164 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1165 */ 1166 mtrr_save_state(); 1167 1168 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1169 err = cpu_check_up_prepare(cpu); 1170 if (err && err != -EBUSY) 1171 return err; 1172 1173 /* the FPU context is blank, nobody can own it */ 1174 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1175 1176 err = common_cpu_up(cpu, tidle); 1177 if (err) 1178 return err; 1179 1180 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1181 if (err) { 1182 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1183 ret = -EIO; 1184 goto unreg_nmi; 1185 } 1186 1187 /* 1188 * Check TSC synchronization with the AP (keep irqs disabled 1189 * while doing so): 1190 */ 1191 local_irq_save(flags); 1192 check_tsc_sync_source(cpu); 1193 local_irq_restore(flags); 1194 1195 while (!cpu_online(cpu)) { 1196 cpu_relax(); 1197 touch_nmi_watchdog(); 1198 } 1199 1200 unreg_nmi: 1201 /* 1202 * Clean up the nmi handler. Do this after the callin and callout sync 1203 * to avoid impact of possible long unregister time. 1204 */ 1205 if (cpu0_nmi_registered) 1206 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1207 1208 return ret; 1209 } 1210 1211 /** 1212 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1213 */ 1214 void arch_disable_smp_support(void) 1215 { 1216 disable_ioapic_support(); 1217 } 1218 1219 /* 1220 * Fall back to non SMP mode after errors. 1221 * 1222 * RED-PEN audit/test this more. I bet there is more state messed up here. 1223 */ 1224 static __init void disable_smp(void) 1225 { 1226 pr_info("SMP disabled\n"); 1227 1228 disable_ioapic_support(); 1229 1230 init_cpu_present(cpumask_of(0)); 1231 init_cpu_possible(cpumask_of(0)); 1232 1233 if (smp_found_config) 1234 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1235 else 1236 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1237 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1238 cpumask_set_cpu(0, topology_core_cpumask(0)); 1239 cpumask_set_cpu(0, topology_die_cpumask(0)); 1240 } 1241 1242 /* 1243 * Various sanity checks. 1244 */ 1245 static void __init smp_sanity_check(void) 1246 { 1247 preempt_disable(); 1248 1249 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1250 if (def_to_bigsmp && nr_cpu_ids > 8) { 1251 unsigned int cpu; 1252 unsigned nr; 1253 1254 pr_warn("More than 8 CPUs detected - skipping them\n" 1255 "Use CONFIG_X86_BIGSMP\n"); 1256 1257 nr = 0; 1258 for_each_present_cpu(cpu) { 1259 if (nr >= 8) 1260 set_cpu_present(cpu, false); 1261 nr++; 1262 } 1263 1264 nr = 0; 1265 for_each_possible_cpu(cpu) { 1266 if (nr >= 8) 1267 set_cpu_possible(cpu, false); 1268 nr++; 1269 } 1270 1271 nr_cpu_ids = 8; 1272 } 1273 #endif 1274 1275 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1276 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1277 hard_smp_processor_id()); 1278 1279 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1280 } 1281 1282 /* 1283 * Should not be necessary because the MP table should list the boot 1284 * CPU too, but we do it for the sake of robustness anyway. 1285 */ 1286 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1287 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1288 boot_cpu_physical_apicid); 1289 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1290 } 1291 preempt_enable(); 1292 } 1293 1294 static void __init smp_cpu_index_default(void) 1295 { 1296 int i; 1297 struct cpuinfo_x86 *c; 1298 1299 for_each_possible_cpu(i) { 1300 c = &cpu_data(i); 1301 /* mark all to hotplug */ 1302 c->cpu_index = nr_cpu_ids; 1303 } 1304 } 1305 1306 static void __init smp_get_logical_apicid(void) 1307 { 1308 if (x2apic_mode) 1309 cpu0_logical_apicid = apic_read(APIC_LDR); 1310 else 1311 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1312 } 1313 1314 /* 1315 * Prepare for SMP bootup. 1316 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1317 * for common interface support. 1318 */ 1319 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1320 { 1321 unsigned int i; 1322 1323 smp_cpu_index_default(); 1324 1325 /* 1326 * Setup boot CPU information 1327 */ 1328 smp_store_boot_cpu_info(); /* Final full version of the data */ 1329 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1330 mb(); 1331 1332 for_each_possible_cpu(i) { 1333 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1334 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1335 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1336 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1337 } 1338 1339 /* 1340 * Set 'default' x86 topology, this matches default_topology() in that 1341 * it has NUMA nodes as a topology level. See also 1342 * native_smp_cpus_done(). 1343 * 1344 * Must be done before set_cpus_sibling_map() is ran. 1345 */ 1346 set_sched_topology(x86_topology); 1347 1348 set_cpu_sibling_map(0); 1349 init_freq_invariance(false, false); 1350 smp_sanity_check(); 1351 1352 switch (apic_intr_mode) { 1353 case APIC_PIC: 1354 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1355 disable_smp(); 1356 return; 1357 case APIC_SYMMETRIC_IO_NO_ROUTING: 1358 disable_smp(); 1359 /* Setup local timer */ 1360 x86_init.timers.setup_percpu_clockev(); 1361 return; 1362 case APIC_VIRTUAL_WIRE: 1363 case APIC_SYMMETRIC_IO: 1364 break; 1365 } 1366 1367 /* Setup local timer */ 1368 x86_init.timers.setup_percpu_clockev(); 1369 1370 smp_get_logical_apicid(); 1371 1372 pr_info("CPU0: "); 1373 print_cpu_info(&cpu_data(0)); 1374 1375 uv_system_init(); 1376 1377 set_mtrr_aps_delayed_init(); 1378 1379 smp_quirk_init_udelay(); 1380 1381 speculative_store_bypass_ht_init(); 1382 } 1383 1384 void arch_thaw_secondary_cpus_begin(void) 1385 { 1386 set_mtrr_aps_delayed_init(); 1387 } 1388 1389 void arch_thaw_secondary_cpus_end(void) 1390 { 1391 mtrr_aps_init(); 1392 } 1393 1394 /* 1395 * Early setup to make printk work. 1396 */ 1397 void __init native_smp_prepare_boot_cpu(void) 1398 { 1399 int me = smp_processor_id(); 1400 switch_to_new_gdt(me); 1401 /* already set me in cpu_online_mask in boot_cpu_init() */ 1402 cpumask_set_cpu(me, cpu_callout_mask); 1403 cpu_set_state_online(me); 1404 native_pv_lock_init(); 1405 } 1406 1407 void __init calculate_max_logical_packages(void) 1408 { 1409 int ncpus; 1410 1411 /* 1412 * Today neither Intel nor AMD support heterogeneous systems so 1413 * extrapolate the boot cpu's data to all packages. 1414 */ 1415 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1416 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1417 pr_info("Max logical packages: %u\n", __max_logical_packages); 1418 } 1419 1420 void __init native_smp_cpus_done(unsigned int max_cpus) 1421 { 1422 pr_debug("Boot done\n"); 1423 1424 calculate_max_logical_packages(); 1425 1426 if (x86_has_numa_in_package) 1427 set_sched_topology(x86_numa_in_package_topology); 1428 1429 nmi_selftest(); 1430 impress_friends(); 1431 mtrr_aps_init(); 1432 } 1433 1434 static int __initdata setup_possible_cpus = -1; 1435 static int __init _setup_possible_cpus(char *str) 1436 { 1437 get_option(&str, &setup_possible_cpus); 1438 return 0; 1439 } 1440 early_param("possible_cpus", _setup_possible_cpus); 1441 1442 1443 /* 1444 * cpu_possible_mask should be static, it cannot change as cpu's 1445 * are onlined, or offlined. The reason is per-cpu data-structures 1446 * are allocated by some modules at init time, and don't expect to 1447 * do this dynamically on cpu arrival/departure. 1448 * cpu_present_mask on the other hand can change dynamically. 1449 * In case when cpu_hotplug is not compiled, then we resort to current 1450 * behaviour, which is cpu_possible == cpu_present. 1451 * - Ashok Raj 1452 * 1453 * Three ways to find out the number of additional hotplug CPUs: 1454 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1455 * - The user can overwrite it with possible_cpus=NUM 1456 * - Otherwise don't reserve additional CPUs. 1457 * We do this because additional CPUs waste a lot of memory. 1458 * -AK 1459 */ 1460 __init void prefill_possible_map(void) 1461 { 1462 int i, possible; 1463 1464 /* No boot processor was found in mptable or ACPI MADT */ 1465 if (!num_processors) { 1466 if (boot_cpu_has(X86_FEATURE_APIC)) { 1467 int apicid = boot_cpu_physical_apicid; 1468 int cpu = hard_smp_processor_id(); 1469 1470 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1471 1472 /* Make sure boot cpu is enumerated */ 1473 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1474 apic->apic_id_valid(apicid)) 1475 generic_processor_info(apicid, boot_cpu_apic_version); 1476 } 1477 1478 if (!num_processors) 1479 num_processors = 1; 1480 } 1481 1482 i = setup_max_cpus ?: 1; 1483 if (setup_possible_cpus == -1) { 1484 possible = num_processors; 1485 #ifdef CONFIG_HOTPLUG_CPU 1486 if (setup_max_cpus) 1487 possible += disabled_cpus; 1488 #else 1489 if (possible > i) 1490 possible = i; 1491 #endif 1492 } else 1493 possible = setup_possible_cpus; 1494 1495 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1496 1497 /* nr_cpu_ids could be reduced via nr_cpus= */ 1498 if (possible > nr_cpu_ids) { 1499 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1500 possible, nr_cpu_ids); 1501 possible = nr_cpu_ids; 1502 } 1503 1504 #ifdef CONFIG_HOTPLUG_CPU 1505 if (!setup_max_cpus) 1506 #endif 1507 if (possible > i) { 1508 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1509 possible, setup_max_cpus); 1510 possible = i; 1511 } 1512 1513 nr_cpu_ids = possible; 1514 1515 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1516 possible, max_t(int, possible - num_processors, 0)); 1517 1518 reset_cpu_possible_mask(); 1519 1520 for (i = 0; i < possible; i++) 1521 set_cpu_possible(i, true); 1522 } 1523 1524 #ifdef CONFIG_HOTPLUG_CPU 1525 1526 /* Recompute SMT state for all CPUs on offline */ 1527 static void recompute_smt_state(void) 1528 { 1529 int max_threads, cpu; 1530 1531 max_threads = 0; 1532 for_each_online_cpu (cpu) { 1533 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1534 1535 if (threads > max_threads) 1536 max_threads = threads; 1537 } 1538 __max_smt_threads = max_threads; 1539 } 1540 1541 static void remove_siblinginfo(int cpu) 1542 { 1543 int sibling; 1544 struct cpuinfo_x86 *c = &cpu_data(cpu); 1545 1546 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1547 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1548 /*/ 1549 * last thread sibling in this cpu core going down 1550 */ 1551 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1552 cpu_data(sibling).booted_cores--; 1553 } 1554 1555 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1556 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1557 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1558 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1559 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1560 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1561 cpumask_clear(cpu_llc_shared_mask(cpu)); 1562 cpumask_clear(topology_sibling_cpumask(cpu)); 1563 cpumask_clear(topology_core_cpumask(cpu)); 1564 cpumask_clear(topology_die_cpumask(cpu)); 1565 c->cpu_core_id = 0; 1566 c->booted_cores = 0; 1567 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1568 recompute_smt_state(); 1569 } 1570 1571 static void remove_cpu_from_maps(int cpu) 1572 { 1573 set_cpu_online(cpu, false); 1574 cpumask_clear_cpu(cpu, cpu_callout_mask); 1575 cpumask_clear_cpu(cpu, cpu_callin_mask); 1576 /* was set by cpu_init() */ 1577 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1578 numa_remove_cpu(cpu); 1579 } 1580 1581 void cpu_disable_common(void) 1582 { 1583 int cpu = smp_processor_id(); 1584 1585 remove_siblinginfo(cpu); 1586 1587 /* It's now safe to remove this processor from the online map */ 1588 lock_vector_lock(); 1589 remove_cpu_from_maps(cpu); 1590 unlock_vector_lock(); 1591 fixup_irqs(); 1592 lapic_offline(); 1593 } 1594 1595 int native_cpu_disable(void) 1596 { 1597 int ret; 1598 1599 ret = lapic_can_unplug_cpu(); 1600 if (ret) 1601 return ret; 1602 1603 cpu_disable_common(); 1604 1605 /* 1606 * Disable the local APIC. Otherwise IPI broadcasts will reach 1607 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1608 * messages. 1609 * 1610 * Disabling the APIC must happen after cpu_disable_common() 1611 * which invokes fixup_irqs(). 1612 * 1613 * Disabling the APIC preserves already set bits in IRR, but 1614 * an interrupt arriving after disabling the local APIC does not 1615 * set the corresponding IRR bit. 1616 * 1617 * fixup_irqs() scans IRR for set bits so it can raise a not 1618 * yet handled interrupt on the new destination CPU via an IPI 1619 * but obviously it can't do so for IRR bits which are not set. 1620 * IOW, interrupts arriving after disabling the local APIC will 1621 * be lost. 1622 */ 1623 apic_soft_disable(); 1624 1625 return 0; 1626 } 1627 1628 int common_cpu_die(unsigned int cpu) 1629 { 1630 int ret = 0; 1631 1632 /* We don't do anything here: idle task is faking death itself. */ 1633 1634 /* They ack this in play_dead() by setting CPU_DEAD */ 1635 if (cpu_wait_death(cpu, 5)) { 1636 if (system_state == SYSTEM_RUNNING) 1637 pr_info("CPU %u is now offline\n", cpu); 1638 } else { 1639 pr_err("CPU %u didn't die...\n", cpu); 1640 ret = -1; 1641 } 1642 1643 return ret; 1644 } 1645 1646 void native_cpu_die(unsigned int cpu) 1647 { 1648 common_cpu_die(cpu); 1649 } 1650 1651 void play_dead_common(void) 1652 { 1653 idle_task_exit(); 1654 1655 /* Ack it */ 1656 (void)cpu_report_death(); 1657 1658 /* 1659 * With physical CPU hotplug, we should halt the cpu 1660 */ 1661 local_irq_disable(); 1662 } 1663 1664 /** 1665 * cond_wakeup_cpu0 - Wake up CPU0 if needed. 1666 * 1667 * If NMI wants to wake up CPU0, start CPU0. 1668 */ 1669 void cond_wakeup_cpu0(void) 1670 { 1671 if (smp_processor_id() == 0 && enable_start_cpu0) 1672 start_cpu0(); 1673 } 1674 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0); 1675 1676 /* 1677 * We need to flush the caches before going to sleep, lest we have 1678 * dirty data in our caches when we come back up. 1679 */ 1680 static inline void mwait_play_dead(void) 1681 { 1682 unsigned int eax, ebx, ecx, edx; 1683 unsigned int highest_cstate = 0; 1684 unsigned int highest_subcstate = 0; 1685 void *mwait_ptr; 1686 int i; 1687 1688 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1689 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1690 return; 1691 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1692 return; 1693 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1694 return; 1695 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1696 return; 1697 1698 eax = CPUID_MWAIT_LEAF; 1699 ecx = 0; 1700 native_cpuid(&eax, &ebx, &ecx, &edx); 1701 1702 /* 1703 * eax will be 0 if EDX enumeration is not valid. 1704 * Initialized below to cstate, sub_cstate value when EDX is valid. 1705 */ 1706 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1707 eax = 0; 1708 } else { 1709 edx >>= MWAIT_SUBSTATE_SIZE; 1710 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1711 if (edx & MWAIT_SUBSTATE_MASK) { 1712 highest_cstate = i; 1713 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1714 } 1715 } 1716 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1717 (highest_subcstate - 1); 1718 } 1719 1720 /* 1721 * This should be a memory location in a cache line which is 1722 * unlikely to be touched by other processors. The actual 1723 * content is immaterial as it is not actually modified in any way. 1724 */ 1725 mwait_ptr = ¤t_thread_info()->flags; 1726 1727 wbinvd(); 1728 1729 while (1) { 1730 /* 1731 * The CLFLUSH is a workaround for erratum AAI65 for 1732 * the Xeon 7400 series. It's not clear it is actually 1733 * needed, but it should be harmless in either case. 1734 * The WBINVD is insufficient due to the spurious-wakeup 1735 * case where we return around the loop. 1736 */ 1737 mb(); 1738 clflush(mwait_ptr); 1739 mb(); 1740 __monitor(mwait_ptr, 0, 0); 1741 mb(); 1742 __mwait(eax, 0); 1743 1744 cond_wakeup_cpu0(); 1745 } 1746 } 1747 1748 void hlt_play_dead(void) 1749 { 1750 if (__this_cpu_read(cpu_info.x86) >= 4) 1751 wbinvd(); 1752 1753 while (1) { 1754 native_halt(); 1755 1756 cond_wakeup_cpu0(); 1757 } 1758 } 1759 1760 void native_play_dead(void) 1761 { 1762 play_dead_common(); 1763 tboot_shutdown(TB_SHUTDOWN_WFS); 1764 1765 mwait_play_dead(); /* Only returns on failure */ 1766 if (cpuidle_play_dead()) 1767 hlt_play_dead(); 1768 } 1769 1770 #else /* ... !CONFIG_HOTPLUG_CPU */ 1771 int native_cpu_disable(void) 1772 { 1773 return -ENOSYS; 1774 } 1775 1776 void native_cpu_die(unsigned int cpu) 1777 { 1778 /* We said "no" in __cpu_disable */ 1779 BUG(); 1780 } 1781 1782 void native_play_dead(void) 1783 { 1784 BUG(); 1785 } 1786 1787 #endif 1788 1789 #ifdef CONFIG_X86_64 1790 /* 1791 * APERF/MPERF frequency ratio computation. 1792 * 1793 * The scheduler wants to do frequency invariant accounting and needs a <1 1794 * ratio to account for the 'current' frequency, corresponding to 1795 * freq_curr / freq_max. 1796 * 1797 * Since the frequency freq_curr on x86 is controlled by micro-controller and 1798 * our P-state setting is little more than a request/hint, we need to observe 1799 * the effective frequency 'BusyMHz', i.e. the average frequency over a time 1800 * interval after discarding idle time. This is given by: 1801 * 1802 * BusyMHz = delta_APERF / delta_MPERF * freq_base 1803 * 1804 * where freq_base is the max non-turbo P-state. 1805 * 1806 * The freq_max term has to be set to a somewhat arbitrary value, because we 1807 * can't know which turbo states will be available at a given point in time: 1808 * it all depends on the thermal headroom of the entire package. We set it to 1809 * the turbo level with 4 cores active. 1810 * 1811 * Benchmarks show that's a good compromise between the 1C turbo ratio 1812 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, 1813 * which would ignore the entire turbo range (a conspicuous part, making 1814 * freq_curr/freq_max always maxed out). 1815 * 1816 * An exception to the heuristic above is the Atom uarch, where we choose the 1817 * highest turbo level for freq_max since Atom's are generally oriented towards 1818 * power efficiency. 1819 * 1820 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio 1821 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. 1822 */ 1823 1824 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); 1825 1826 static DEFINE_PER_CPU(u64, arch_prev_aperf); 1827 static DEFINE_PER_CPU(u64, arch_prev_mperf); 1828 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; 1829 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; 1830 1831 void arch_set_max_freq_ratio(bool turbo_disabled) 1832 { 1833 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : 1834 arch_turbo_freq_ratio; 1835 } 1836 EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio); 1837 1838 static bool turbo_disabled(void) 1839 { 1840 u64 misc_en; 1841 int err; 1842 1843 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); 1844 if (err) 1845 return false; 1846 1847 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 1848 } 1849 1850 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1851 { 1852 int err; 1853 1854 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); 1855 if (err) 1856 return false; 1857 1858 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); 1859 if (err) 1860 return false; 1861 1862 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ 1863 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ 1864 1865 return true; 1866 } 1867 1868 #define X86_MATCH(model) \ 1869 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ 1870 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) 1871 1872 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { 1873 X86_MATCH(XEON_PHI_KNL), 1874 X86_MATCH(XEON_PHI_KNM), 1875 {} 1876 }; 1877 1878 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { 1879 X86_MATCH(SKYLAKE_X), 1880 {} 1881 }; 1882 1883 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { 1884 X86_MATCH(ATOM_GOLDMONT), 1885 X86_MATCH(ATOM_GOLDMONT_D), 1886 X86_MATCH(ATOM_GOLDMONT_PLUS), 1887 {} 1888 }; 1889 1890 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, 1891 int num_delta_fratio) 1892 { 1893 int fratio, delta_fratio, found; 1894 int err, i; 1895 u64 msr; 1896 1897 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1898 if (err) 1899 return false; 1900 1901 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1902 1903 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 1904 if (err) 1905 return false; 1906 1907 fratio = (msr >> 8) & 0xFF; 1908 i = 16; 1909 found = 0; 1910 do { 1911 if (found >= num_delta_fratio) { 1912 *turbo_freq = fratio; 1913 return true; 1914 } 1915 1916 delta_fratio = (msr >> (i + 5)) & 0x7; 1917 1918 if (delta_fratio) { 1919 found += 1; 1920 fratio -= delta_fratio; 1921 } 1922 1923 i += 8; 1924 } while (i < 64); 1925 1926 return true; 1927 } 1928 1929 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) 1930 { 1931 u64 ratios, counts; 1932 u32 group_size; 1933 int err, i; 1934 1935 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1936 if (err) 1937 return false; 1938 1939 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1940 1941 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); 1942 if (err) 1943 return false; 1944 1945 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); 1946 if (err) 1947 return false; 1948 1949 for (i = 0; i < 64; i += 8) { 1950 group_size = (counts >> i) & 0xFF; 1951 if (group_size >= size) { 1952 *turbo_freq = (ratios >> i) & 0xFF; 1953 return true; 1954 } 1955 } 1956 1957 return false; 1958 } 1959 1960 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1961 { 1962 u64 msr; 1963 int err; 1964 1965 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1966 if (err) 1967 return false; 1968 1969 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 1970 if (err) 1971 return false; 1972 1973 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1974 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */ 1975 1976 /* The CPU may have less than 4 cores */ 1977 if (!*turbo_freq) 1978 *turbo_freq = msr & 0xFF; /* 1C turbo */ 1979 1980 return true; 1981 } 1982 1983 static bool intel_set_max_freq_ratio(void) 1984 { 1985 u64 base_freq, turbo_freq; 1986 u64 turbo_ratio; 1987 1988 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) 1989 goto out; 1990 1991 if (x86_match_cpu(has_glm_turbo_ratio_limits) && 1992 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 1993 goto out; 1994 1995 if (x86_match_cpu(has_knl_turbo_ratio_limits) && 1996 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 1997 goto out; 1998 1999 if (x86_match_cpu(has_skx_turbo_ratio_limits) && 2000 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) 2001 goto out; 2002 2003 if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) 2004 goto out; 2005 2006 return false; 2007 2008 out: 2009 /* 2010 * Some hypervisors advertise X86_FEATURE_APERFMPERF 2011 * but then fill all MSR's with zeroes. 2012 * Some CPUs have turbo boost but don't declare any turbo ratio 2013 * in MSR_TURBO_RATIO_LIMIT. 2014 */ 2015 if (!base_freq || !turbo_freq) { 2016 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n"); 2017 return false; 2018 } 2019 2020 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq); 2021 if (!turbo_ratio) { 2022 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n"); 2023 return false; 2024 } 2025 2026 arch_turbo_freq_ratio = turbo_ratio; 2027 arch_set_max_freq_ratio(turbo_disabled()); 2028 2029 return true; 2030 } 2031 2032 #ifdef CONFIG_ACPI_CPPC_LIB 2033 static bool amd_set_max_freq_ratio(void) 2034 { 2035 struct cppc_perf_caps perf_caps; 2036 u64 highest_perf, nominal_perf; 2037 u64 perf_ratio; 2038 int rc; 2039 2040 rc = cppc_get_perf_caps(0, &perf_caps); 2041 if (rc) { 2042 pr_debug("Could not retrieve perf counters (%d)\n", rc); 2043 return false; 2044 } 2045 2046 highest_perf = amd_get_highest_perf(); 2047 nominal_perf = perf_caps.nominal_perf; 2048 2049 if (!highest_perf || !nominal_perf) { 2050 pr_debug("Could not retrieve highest or nominal performance\n"); 2051 return false; 2052 } 2053 2054 perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf); 2055 /* midpoint between max_boost and max_P */ 2056 perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1; 2057 if (!perf_ratio) { 2058 pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n"); 2059 return false; 2060 } 2061 2062 arch_turbo_freq_ratio = perf_ratio; 2063 arch_set_max_freq_ratio(false); 2064 2065 return true; 2066 } 2067 #else 2068 static bool amd_set_max_freq_ratio(void) 2069 { 2070 return false; 2071 } 2072 #endif 2073 2074 static void init_counter_refs(void) 2075 { 2076 u64 aperf, mperf; 2077 2078 rdmsrl(MSR_IA32_APERF, aperf); 2079 rdmsrl(MSR_IA32_MPERF, mperf); 2080 2081 this_cpu_write(arch_prev_aperf, aperf); 2082 this_cpu_write(arch_prev_mperf, mperf); 2083 } 2084 2085 #ifdef CONFIG_PM_SLEEP 2086 static struct syscore_ops freq_invariance_syscore_ops = { 2087 .resume = init_counter_refs, 2088 }; 2089 2090 static void register_freq_invariance_syscore_ops(void) 2091 { 2092 /* Bail out if registered already. */ 2093 if (freq_invariance_syscore_ops.node.prev) 2094 return; 2095 2096 register_syscore_ops(&freq_invariance_syscore_ops); 2097 } 2098 #else 2099 static inline void register_freq_invariance_syscore_ops(void) {} 2100 #endif 2101 2102 static void init_freq_invariance(bool secondary, bool cppc_ready) 2103 { 2104 bool ret = false; 2105 2106 if (!boot_cpu_has(X86_FEATURE_APERFMPERF)) 2107 return; 2108 2109 if (secondary) { 2110 if (static_branch_likely(&arch_scale_freq_key)) { 2111 init_counter_refs(); 2112 } 2113 return; 2114 } 2115 2116 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 2117 ret = intel_set_max_freq_ratio(); 2118 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { 2119 if (!cppc_ready) { 2120 return; 2121 } 2122 ret = amd_set_max_freq_ratio(); 2123 } 2124 2125 if (ret) { 2126 init_counter_refs(); 2127 static_branch_enable(&arch_scale_freq_key); 2128 register_freq_invariance_syscore_ops(); 2129 pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); 2130 } else { 2131 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); 2132 } 2133 } 2134 2135 #ifdef CONFIG_ACPI_CPPC_LIB 2136 static DEFINE_MUTEX(freq_invariance_lock); 2137 2138 void init_freq_invariance_cppc(void) 2139 { 2140 static bool secondary; 2141 2142 mutex_lock(&freq_invariance_lock); 2143 2144 init_freq_invariance(secondary, true); 2145 secondary = true; 2146 2147 mutex_unlock(&freq_invariance_lock); 2148 } 2149 #endif 2150 2151 static void disable_freq_invariance_workfn(struct work_struct *work) 2152 { 2153 static_branch_disable(&arch_scale_freq_key); 2154 } 2155 2156 static DECLARE_WORK(disable_freq_invariance_work, 2157 disable_freq_invariance_workfn); 2158 2159 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; 2160 2161 void arch_scale_freq_tick(void) 2162 { 2163 u64 freq_scale = SCHED_CAPACITY_SCALE; 2164 u64 aperf, mperf; 2165 u64 acnt, mcnt; 2166 2167 if (!arch_scale_freq_invariant()) 2168 return; 2169 2170 rdmsrl(MSR_IA32_APERF, aperf); 2171 rdmsrl(MSR_IA32_MPERF, mperf); 2172 2173 acnt = aperf - this_cpu_read(arch_prev_aperf); 2174 mcnt = mperf - this_cpu_read(arch_prev_mperf); 2175 2176 this_cpu_write(arch_prev_aperf, aperf); 2177 this_cpu_write(arch_prev_mperf, mperf); 2178 2179 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt)) 2180 goto error; 2181 2182 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt) 2183 goto error; 2184 2185 freq_scale = div64_u64(acnt, mcnt); 2186 if (!freq_scale) 2187 goto error; 2188 2189 if (freq_scale > SCHED_CAPACITY_SCALE) 2190 freq_scale = SCHED_CAPACITY_SCALE; 2191 2192 this_cpu_write(arch_freq_scale, freq_scale); 2193 return; 2194 2195 error: 2196 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n"); 2197 schedule_work(&disable_freq_invariance_work); 2198 } 2199 #else 2200 static inline void init_freq_invariance(bool secondary, bool cppc_ready) 2201 { 2202 } 2203 #endif /* CONFIG_X86_64 */ 2204