xref: /linux/arch/x86/kernel/smp.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *	Intel SMP support routines.
4  *
5  *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6  *	(c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7  *      (c) 2002,2003 Andi Kleen, SuSE Labs.
8  *
9  *	i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
10  */
11 
12 #include <linux/init.h>
13 
14 #include <linux/mm.h>
15 #include <linux/delay.h>
16 #include <linux/spinlock.h>
17 #include <linux/export.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/cache.h>
21 #include <linux/interrupt.h>
22 #include <linux/cpu.h>
23 #include <linux/gfp.h>
24 #include <linux/kexec.h>
25 
26 #include <asm/mtrr.h>
27 #include <asm/tlbflush.h>
28 #include <asm/mmu_context.h>
29 #include <asm/proto.h>
30 #include <asm/apic.h>
31 #include <asm/cpu.h>
32 #include <asm/idtentry.h>
33 #include <asm/nmi.h>
34 #include <asm/mce.h>
35 #include <asm/trace/irq_vectors.h>
36 #include <asm/kexec.h>
37 #include <asm/reboot.h>
38 
39 /*
40  *	Some notes on x86 processor bugs affecting SMP operation:
41  *
42  *	Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
43  *	The Linux implications for SMP are handled as follows:
44  *
45  *	Pentium III / [Xeon]
46  *		None of the E1AP-E3AP errata are visible to the user.
47  *
48  *	E1AP.	see PII A1AP
49  *	E2AP.	see PII A2AP
50  *	E3AP.	see PII A3AP
51  *
52  *	Pentium II / [Xeon]
53  *		None of the A1AP-A3AP errata are visible to the user.
54  *
55  *	A1AP.	see PPro 1AP
56  *	A2AP.	see PPro 2AP
57  *	A3AP.	see PPro 7AP
58  *
59  *	Pentium Pro
60  *		None of 1AP-9AP errata are visible to the normal user,
61  *	except occasional delivery of 'spurious interrupt' as trap #15.
62  *	This is very rare and a non-problem.
63  *
64  *	1AP.	Linux maps APIC as non-cacheable
65  *	2AP.	worked around in hardware
66  *	3AP.	fixed in C0 and above steppings microcode update.
67  *		Linux does not use excessive STARTUP_IPIs.
68  *	4AP.	worked around in hardware
69  *	5AP.	symmetric IO mode (normal Linux operation) not affected.
70  *		'noapic' mode has vector 0xf filled out properly.
71  *	6AP.	'noapic' mode might be affected - fixed in later steppings
72  *	7AP.	We do not assume writes to the LVT deasserting IRQs
73  *	8AP.	We do not enable low power mode (deep sleep) during MP bootup
74  *	9AP.	We do not use mixed mode
75  *
76  *	Pentium
77  *		There is a marginal case where REP MOVS on 100MHz SMP
78  *	machines with B stepping processors can fail. XXX should provide
79  *	an L1cache=Writethrough or L1cache=off option.
80  *
81  *		B stepping CPUs may hang. There are hardware work arounds
82  *	for this. We warn about it in case your board doesn't have the work
83  *	arounds. Basically that's so I can tell anyone with a B stepping
84  *	CPU and SMP problems "tough".
85  *
86  *	Specific items [From Pentium Processor Specification Update]
87  *
88  *	1AP.	Linux doesn't use remote read
89  *	2AP.	Linux doesn't trust APIC errors
90  *	3AP.	We work around this
91  *	4AP.	Linux never generated 3 interrupts of the same priority
92  *		to cause a lost local interrupt.
93  *	5AP.	Remote read is never used
94  *	6AP.	not affected - worked around in hardware
95  *	7AP.	not affected - worked around in hardware
96  *	8AP.	worked around in hardware - we get explicit CS errors if not
97  *	9AP.	only 'noapic' mode affected. Might generate spurious
98  *		interrupts, we log only the first one and count the
99  *		rest silently.
100  *	10AP.	not affected - worked around in hardware
101  *	11AP.	Linux reads the APIC between writes to avoid this, as per
102  *		the documentation. Make sure you preserve this as it affects
103  *		the C stepping chips too.
104  *	12AP.	not affected - worked around in hardware
105  *	13AP.	not affected - worked around in hardware
106  *	14AP.	we always deassert INIT during bootup
107  *	15AP.	not affected - worked around in hardware
108  *	16AP.	not affected - worked around in hardware
109  *	17AP.	not affected - worked around in hardware
110  *	18AP.	not affected - worked around in hardware
111  *	19AP.	not affected - worked around in BIOS
112  *
113  *	If this sounds worrying believe me these bugs are either ___RARE___,
114  *	or are signal timing bugs worked around in hardware and there's
115  *	about nothing of note with C stepping upwards.
116  */
117 
118 static atomic_t stopping_cpu = ATOMIC_INIT(-1);
119 static bool smp_no_nmi_ipi = false;
120 
121 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
122 {
123 	/* We are registered on stopping cpu too, avoid spurious NMI */
124 	if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
125 		return NMI_HANDLED;
126 
127 	cpu_emergency_disable_virtualization();
128 	stop_this_cpu(NULL);
129 
130 	return NMI_HANDLED;
131 }
132 
133 /*
134  * this function calls the 'stop' function on all other CPUs in the system.
135  */
136 DEFINE_IDTENTRY_SYSVEC(sysvec_reboot)
137 {
138 	apic_eoi();
139 	cpu_emergency_disable_virtualization();
140 	stop_this_cpu(NULL);
141 }
142 
143 static int register_stop_handler(void)
144 {
145 	return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
146 				    NMI_FLAG_FIRST, "smp_stop");
147 }
148 
149 static void native_stop_other_cpus(int wait)
150 {
151 	unsigned int old_cpu, this_cpu;
152 	unsigned long flags, timeout;
153 
154 	if (reboot_force)
155 		return;
156 
157 	/* Only proceed if this is the first CPU to reach this code */
158 	old_cpu = -1;
159 	this_cpu = smp_processor_id();
160 	if (!atomic_try_cmpxchg(&stopping_cpu, &old_cpu, this_cpu))
161 		return;
162 
163 	/* For kexec, ensure that offline CPUs are out of MWAIT and in HLT */
164 	if (kexec_in_progress)
165 		smp_kick_mwait_play_dead();
166 
167 	/*
168 	 * 1) Send an IPI on the reboot vector to all other CPUs.
169 	 *
170 	 *    The other CPUs should react on it after leaving critical
171 	 *    sections and re-enabling interrupts. They might still hold
172 	 *    locks, but there is nothing which can be done about that.
173 	 *
174 	 * 2) Wait for all other CPUs to report that they reached the
175 	 *    HLT loop in stop_this_cpu()
176 	 *
177 	 * 3) If #2 timed out send an NMI to the CPUs which did not
178 	 *    yet report
179 	 *
180 	 * 4) Wait for all other CPUs to report that they reached the
181 	 *    HLT loop in stop_this_cpu()
182 	 *
183 	 * #3 can obviously race against a CPU reaching the HLT loop late.
184 	 * That CPU will have reported already and the "have all CPUs
185 	 * reached HLT" condition will be true despite the fact that the
186 	 * other CPU is still handling the NMI. Again, there is no
187 	 * protection against that as "disabled" APICs still respond to
188 	 * NMIs.
189 	 */
190 	cpumask_copy(&cpus_stop_mask, cpu_online_mask);
191 	cpumask_clear_cpu(this_cpu, &cpus_stop_mask);
192 
193 	if (!cpumask_empty(&cpus_stop_mask)) {
194 		apic_send_IPI_allbutself(REBOOT_VECTOR);
195 
196 		/*
197 		 * Don't wait longer than a second for IPI completion. The
198 		 * wait request is not checked here because that would
199 		 * prevent an NMI shutdown attempt in case that not all
200 		 * CPUs reach shutdown state.
201 		 */
202 		timeout = USEC_PER_SEC;
203 		while (!cpumask_empty(&cpus_stop_mask) && timeout--)
204 			udelay(1);
205 	}
206 
207 	/* if the REBOOT_VECTOR didn't work, try with the NMI */
208 	if (!cpumask_empty(&cpus_stop_mask)) {
209 		/*
210 		 * If NMI IPI is enabled, try to register the stop handler
211 		 * and send the IPI. In any case try to wait for the other
212 		 * CPUs to stop.
213 		 */
214 		if (!smp_no_nmi_ipi && !register_stop_handler()) {
215 			unsigned int cpu;
216 
217 			pr_emerg("Shutting down cpus with NMI\n");
218 
219 			for_each_cpu(cpu, &cpus_stop_mask)
220 				__apic_send_IPI(cpu, NMI_VECTOR);
221 		}
222 		/*
223 		 * Don't wait longer than 10 ms if the caller didn't
224 		 * request it. If wait is true, the machine hangs here if
225 		 * one or more CPUs do not reach shutdown state.
226 		 */
227 		timeout = USEC_PER_MSEC * 10;
228 		while (!cpumask_empty(&cpus_stop_mask) && (wait || timeout--))
229 			udelay(1);
230 	}
231 
232 	local_irq_save(flags);
233 	disable_local_APIC();
234 	mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
235 	local_irq_restore(flags);
236 
237 	/*
238 	 * Ensure that the cpus_stop_mask cache lines are invalidated on
239 	 * the other CPUs. See comment vs. SME in stop_this_cpu().
240 	 */
241 	cpumask_clear(&cpus_stop_mask);
242 }
243 
244 /*
245  * Reschedule call back. KVM uses this interrupt to force a cpu out of
246  * guest mode.
247  */
248 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi)
249 {
250 	apic_eoi();
251 	trace_reschedule_entry(RESCHEDULE_VECTOR);
252 	inc_irq_stat(irq_resched_count);
253 	scheduler_ipi();
254 	trace_reschedule_exit(RESCHEDULE_VECTOR);
255 }
256 
257 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function)
258 {
259 	apic_eoi();
260 	trace_call_function_entry(CALL_FUNCTION_VECTOR);
261 	inc_irq_stat(irq_call_count);
262 	generic_smp_call_function_interrupt();
263 	trace_call_function_exit(CALL_FUNCTION_VECTOR);
264 }
265 
266 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single)
267 {
268 	apic_eoi();
269 	trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
270 	inc_irq_stat(irq_call_count);
271 	generic_smp_call_function_single_interrupt();
272 	trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
273 }
274 
275 static int __init nonmi_ipi_setup(char *str)
276 {
277 	smp_no_nmi_ipi = true;
278 	return 1;
279 }
280 
281 __setup("nonmi_ipi", nonmi_ipi_setup);
282 
283 struct smp_ops smp_ops = {
284 	.smp_prepare_boot_cpu	= native_smp_prepare_boot_cpu,
285 	.smp_prepare_cpus	= native_smp_prepare_cpus,
286 	.smp_cpus_done		= native_smp_cpus_done,
287 
288 	.stop_other_cpus	= native_stop_other_cpus,
289 #if defined(CONFIG_CRASH_DUMP)
290 	.crash_stop_other_cpus	= kdump_nmi_shootdown_cpus,
291 #endif
292 	.smp_send_reschedule	= native_smp_send_reschedule,
293 
294 	.kick_ap_alive		= native_kick_ap,
295 	.cpu_disable		= native_cpu_disable,
296 	.play_dead		= native_play_dead,
297 
298 	.send_call_func_ipi	= native_send_call_func_ipi,
299 	.send_call_func_single_ipi = native_send_call_func_single_ipi,
300 };
301 EXPORT_SYMBOL_GPL(smp_ops);
302