1 /* 2 * Intel SMP support routines. 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * (c) 2002,2003 Andi Kleen, SuSE Labs. 7 * 8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> 9 * 10 * This code is released under the GNU General Public License version 2 or 11 * later. 12 */ 13 14 #include <linux/init.h> 15 16 #include <linux/mm.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/export.h> 20 #include <linux/kernel_stat.h> 21 #include <linux/mc146818rtc.h> 22 #include <linux/cache.h> 23 #include <linux/interrupt.h> 24 #include <linux/cpu.h> 25 #include <linux/gfp.h> 26 27 #include <asm/mtrr.h> 28 #include <asm/tlbflush.h> 29 #include <asm/mmu_context.h> 30 #include <asm/proto.h> 31 #include <asm/apic.h> 32 #include <asm/nmi.h> 33 #include <asm/mce.h> 34 #include <asm/trace/irq_vectors.h> 35 #include <asm/kexec.h> 36 37 /* 38 * Some notes on x86 processor bugs affecting SMP operation: 39 * 40 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. 41 * The Linux implications for SMP are handled as follows: 42 * 43 * Pentium III / [Xeon] 44 * None of the E1AP-E3AP errata are visible to the user. 45 * 46 * E1AP. see PII A1AP 47 * E2AP. see PII A2AP 48 * E3AP. see PII A3AP 49 * 50 * Pentium II / [Xeon] 51 * None of the A1AP-A3AP errata are visible to the user. 52 * 53 * A1AP. see PPro 1AP 54 * A2AP. see PPro 2AP 55 * A3AP. see PPro 7AP 56 * 57 * Pentium Pro 58 * None of 1AP-9AP errata are visible to the normal user, 59 * except occasional delivery of 'spurious interrupt' as trap #15. 60 * This is very rare and a non-problem. 61 * 62 * 1AP. Linux maps APIC as non-cacheable 63 * 2AP. worked around in hardware 64 * 3AP. fixed in C0 and above steppings microcode update. 65 * Linux does not use excessive STARTUP_IPIs. 66 * 4AP. worked around in hardware 67 * 5AP. symmetric IO mode (normal Linux operation) not affected. 68 * 'noapic' mode has vector 0xf filled out properly. 69 * 6AP. 'noapic' mode might be affected - fixed in later steppings 70 * 7AP. We do not assume writes to the LVT deassering IRQs 71 * 8AP. We do not enable low power mode (deep sleep) during MP bootup 72 * 9AP. We do not use mixed mode 73 * 74 * Pentium 75 * There is a marginal case where REP MOVS on 100MHz SMP 76 * machines with B stepping processors can fail. XXX should provide 77 * an L1cache=Writethrough or L1cache=off option. 78 * 79 * B stepping CPUs may hang. There are hardware work arounds 80 * for this. We warn about it in case your board doesn't have the work 81 * arounds. Basically that's so I can tell anyone with a B stepping 82 * CPU and SMP problems "tough". 83 * 84 * Specific items [From Pentium Processor Specification Update] 85 * 86 * 1AP. Linux doesn't use remote read 87 * 2AP. Linux doesn't trust APIC errors 88 * 3AP. We work around this 89 * 4AP. Linux never generated 3 interrupts of the same priority 90 * to cause a lost local interrupt. 91 * 5AP. Remote read is never used 92 * 6AP. not affected - worked around in hardware 93 * 7AP. not affected - worked around in hardware 94 * 8AP. worked around in hardware - we get explicit CS errors if not 95 * 9AP. only 'noapic' mode affected. Might generate spurious 96 * interrupts, we log only the first one and count the 97 * rest silently. 98 * 10AP. not affected - worked around in hardware 99 * 11AP. Linux reads the APIC between writes to avoid this, as per 100 * the documentation. Make sure you preserve this as it affects 101 * the C stepping chips too. 102 * 12AP. not affected - worked around in hardware 103 * 13AP. not affected - worked around in hardware 104 * 14AP. we always deassert INIT during bootup 105 * 15AP. not affected - worked around in hardware 106 * 16AP. not affected - worked around in hardware 107 * 17AP. not affected - worked around in hardware 108 * 18AP. not affected - worked around in hardware 109 * 19AP. not affected - worked around in BIOS 110 * 111 * If this sounds worrying believe me these bugs are either ___RARE___, 112 * or are signal timing bugs worked around in hardware and there's 113 * about nothing of note with C stepping upwards. 114 */ 115 116 static atomic_t stopping_cpu = ATOMIC_INIT(-1); 117 static bool smp_no_nmi_ipi = false; 118 119 /* 120 * this function sends a 'reschedule' IPI to another CPU. 121 * it goes straight through and wastes no time serializing 122 * anything. Worst case is that we lose a reschedule ... 123 */ 124 static void native_smp_send_reschedule(int cpu) 125 { 126 if (unlikely(cpu_is_offline(cpu))) { 127 WARN_ON(1); 128 return; 129 } 130 apic->send_IPI(cpu, RESCHEDULE_VECTOR); 131 } 132 133 void native_send_call_func_single_ipi(int cpu) 134 { 135 apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); 136 } 137 138 void native_send_call_func_ipi(const struct cpumask *mask) 139 { 140 cpumask_var_t allbutself; 141 142 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) { 143 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 144 return; 145 } 146 147 cpumask_copy(allbutself, cpu_online_mask); 148 cpumask_clear_cpu(smp_processor_id(), allbutself); 149 150 if (cpumask_equal(mask, allbutself) && 151 cpumask_equal(cpu_online_mask, cpu_callout_mask)) 152 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); 153 else 154 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 155 156 free_cpumask_var(allbutself); 157 } 158 159 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) 160 { 161 /* We are registered on stopping cpu too, avoid spurious NMI */ 162 if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) 163 return NMI_HANDLED; 164 165 stop_this_cpu(NULL); 166 167 return NMI_HANDLED; 168 } 169 170 /* 171 * this function calls the 'stop' function on all other CPUs in the system. 172 */ 173 174 asmlinkage __visible void smp_reboot_interrupt(void) 175 { 176 ipi_entering_ack_irq(); 177 stop_this_cpu(NULL); 178 irq_exit(); 179 } 180 181 static void native_stop_other_cpus(int wait) 182 { 183 unsigned long flags; 184 unsigned long timeout; 185 186 if (reboot_force) 187 return; 188 189 /* 190 * Use an own vector here because smp_call_function 191 * does lots of things not suitable in a panic situation. 192 */ 193 194 /* 195 * We start by using the REBOOT_VECTOR irq. 196 * The irq is treated as a sync point to allow critical 197 * regions of code on other cpus to release their spin locks 198 * and re-enable irqs. Jumping straight to an NMI might 199 * accidentally cause deadlocks with further shutdown/panic 200 * code. By syncing, we give the cpus up to one second to 201 * finish their work before we force them off with the NMI. 202 */ 203 if (num_online_cpus() > 1) { 204 /* did someone beat us here? */ 205 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1) 206 return; 207 208 /* sync above data before sending IRQ */ 209 wmb(); 210 211 apic->send_IPI_allbutself(REBOOT_VECTOR); 212 213 /* 214 * Don't wait longer than a second if the caller 215 * didn't ask us to wait. 216 */ 217 timeout = USEC_PER_SEC; 218 while (num_online_cpus() > 1 && (wait || timeout--)) 219 udelay(1); 220 } 221 222 /* if the REBOOT_VECTOR didn't work, try with the NMI */ 223 if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi)) { 224 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, 225 NMI_FLAG_FIRST, "smp_stop")) 226 /* Note: we ignore failures here */ 227 /* Hope the REBOOT_IRQ is good enough */ 228 goto finish; 229 230 /* sync above data before sending IRQ */ 231 wmb(); 232 233 pr_emerg("Shutting down cpus with NMI\n"); 234 235 apic->send_IPI_allbutself(NMI_VECTOR); 236 237 /* 238 * Don't wait longer than a 10 ms if the caller 239 * didn't ask us to wait. 240 */ 241 timeout = USEC_PER_MSEC * 10; 242 while (num_online_cpus() > 1 && (wait || timeout--)) 243 udelay(1); 244 } 245 246 finish: 247 local_irq_save(flags); 248 disable_local_APIC(); 249 mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); 250 local_irq_restore(flags); 251 } 252 253 /* 254 * Reschedule call back. 255 */ 256 static inline void __smp_reschedule_interrupt(void) 257 { 258 inc_irq_stat(irq_resched_count); 259 scheduler_ipi(); 260 } 261 262 __visible void smp_reschedule_interrupt(struct pt_regs *regs) 263 { 264 ack_APIC_irq(); 265 __smp_reschedule_interrupt(); 266 /* 267 * KVM uses this interrupt to force a cpu out of guest mode 268 */ 269 } 270 271 __visible void smp_trace_reschedule_interrupt(struct pt_regs *regs) 272 { 273 /* 274 * Need to call irq_enter() before calling the trace point. 275 * __smp_reschedule_interrupt() calls irq_enter/exit() too (in 276 * scheduler_ipi(). This is OK, since those functions are allowed 277 * to nest. 278 */ 279 ipi_entering_ack_irq(); 280 trace_reschedule_entry(RESCHEDULE_VECTOR); 281 __smp_reschedule_interrupt(); 282 trace_reschedule_exit(RESCHEDULE_VECTOR); 283 exiting_irq(); 284 /* 285 * KVM uses this interrupt to force a cpu out of guest mode 286 */ 287 } 288 289 static inline void __smp_call_function_interrupt(void) 290 { 291 generic_smp_call_function_interrupt(); 292 inc_irq_stat(irq_call_count); 293 } 294 295 __visible void smp_call_function_interrupt(struct pt_regs *regs) 296 { 297 ipi_entering_ack_irq(); 298 __smp_call_function_interrupt(); 299 exiting_irq(); 300 } 301 302 __visible void smp_trace_call_function_interrupt(struct pt_regs *regs) 303 { 304 ipi_entering_ack_irq(); 305 trace_call_function_entry(CALL_FUNCTION_VECTOR); 306 __smp_call_function_interrupt(); 307 trace_call_function_exit(CALL_FUNCTION_VECTOR); 308 exiting_irq(); 309 } 310 311 static inline void __smp_call_function_single_interrupt(void) 312 { 313 generic_smp_call_function_single_interrupt(); 314 inc_irq_stat(irq_call_count); 315 } 316 317 __visible void smp_call_function_single_interrupt(struct pt_regs *regs) 318 { 319 ipi_entering_ack_irq(); 320 __smp_call_function_single_interrupt(); 321 exiting_irq(); 322 } 323 324 __visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs) 325 { 326 ipi_entering_ack_irq(); 327 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); 328 __smp_call_function_single_interrupt(); 329 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR); 330 exiting_irq(); 331 } 332 333 static int __init nonmi_ipi_setup(char *str) 334 { 335 smp_no_nmi_ipi = true; 336 return 1; 337 } 338 339 __setup("nonmi_ipi", nonmi_ipi_setup); 340 341 struct smp_ops smp_ops = { 342 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 343 .smp_prepare_cpus = native_smp_prepare_cpus, 344 .smp_cpus_done = native_smp_cpus_done, 345 346 .stop_other_cpus = native_stop_other_cpus, 347 #if defined(CONFIG_KEXEC_CORE) 348 .crash_stop_other_cpus = kdump_nmi_shootdown_cpus, 349 #endif 350 .smp_send_reschedule = native_smp_send_reschedule, 351 352 .cpu_up = native_cpu_up, 353 .cpu_die = native_cpu_die, 354 .cpu_disable = native_cpu_disable, 355 .play_dead = native_play_dead, 356 357 .send_call_func_ipi = native_send_call_func_ipi, 358 .send_call_func_single_ipi = native_send_call_func_single_ipi, 359 }; 360 EXPORT_SYMBOL_GPL(smp_ops); 361