1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Intel SMP support routines. 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * (c) 2002,2003 Andi Kleen, SuSE Labs. 8 * 9 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> 10 */ 11 12 #include <linux/init.h> 13 14 #include <linux/mm.h> 15 #include <linux/delay.h> 16 #include <linux/spinlock.h> 17 #include <linux/export.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/cache.h> 21 #include <linux/interrupt.h> 22 #include <linux/cpu.h> 23 #include <linux/gfp.h> 24 25 #include <asm/mtrr.h> 26 #include <asm/tlbflush.h> 27 #include <asm/mmu_context.h> 28 #include <asm/proto.h> 29 #include <asm/apic.h> 30 #include <asm/nmi.h> 31 #include <asm/mce.h> 32 #include <asm/trace/irq_vectors.h> 33 #include <asm/kexec.h> 34 #include <asm/virtext.h> 35 36 /* 37 * Some notes on x86 processor bugs affecting SMP operation: 38 * 39 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. 40 * The Linux implications for SMP are handled as follows: 41 * 42 * Pentium III / [Xeon] 43 * None of the E1AP-E3AP errata are visible to the user. 44 * 45 * E1AP. see PII A1AP 46 * E2AP. see PII A2AP 47 * E3AP. see PII A3AP 48 * 49 * Pentium II / [Xeon] 50 * None of the A1AP-A3AP errata are visible to the user. 51 * 52 * A1AP. see PPro 1AP 53 * A2AP. see PPro 2AP 54 * A3AP. see PPro 7AP 55 * 56 * Pentium Pro 57 * None of 1AP-9AP errata are visible to the normal user, 58 * except occasional delivery of 'spurious interrupt' as trap #15. 59 * This is very rare and a non-problem. 60 * 61 * 1AP. Linux maps APIC as non-cacheable 62 * 2AP. worked around in hardware 63 * 3AP. fixed in C0 and above steppings microcode update. 64 * Linux does not use excessive STARTUP_IPIs. 65 * 4AP. worked around in hardware 66 * 5AP. symmetric IO mode (normal Linux operation) not affected. 67 * 'noapic' mode has vector 0xf filled out properly. 68 * 6AP. 'noapic' mode might be affected - fixed in later steppings 69 * 7AP. We do not assume writes to the LVT deassering IRQs 70 * 8AP. We do not enable low power mode (deep sleep) during MP bootup 71 * 9AP. We do not use mixed mode 72 * 73 * Pentium 74 * There is a marginal case where REP MOVS on 100MHz SMP 75 * machines with B stepping processors can fail. XXX should provide 76 * an L1cache=Writethrough or L1cache=off option. 77 * 78 * B stepping CPUs may hang. There are hardware work arounds 79 * for this. We warn about it in case your board doesn't have the work 80 * arounds. Basically that's so I can tell anyone with a B stepping 81 * CPU and SMP problems "tough". 82 * 83 * Specific items [From Pentium Processor Specification Update] 84 * 85 * 1AP. Linux doesn't use remote read 86 * 2AP. Linux doesn't trust APIC errors 87 * 3AP. We work around this 88 * 4AP. Linux never generated 3 interrupts of the same priority 89 * to cause a lost local interrupt. 90 * 5AP. Remote read is never used 91 * 6AP. not affected - worked around in hardware 92 * 7AP. not affected - worked around in hardware 93 * 8AP. worked around in hardware - we get explicit CS errors if not 94 * 9AP. only 'noapic' mode affected. Might generate spurious 95 * interrupts, we log only the first one and count the 96 * rest silently. 97 * 10AP. not affected - worked around in hardware 98 * 11AP. Linux reads the APIC between writes to avoid this, as per 99 * the documentation. Make sure you preserve this as it affects 100 * the C stepping chips too. 101 * 12AP. not affected - worked around in hardware 102 * 13AP. not affected - worked around in hardware 103 * 14AP. we always deassert INIT during bootup 104 * 15AP. not affected - worked around in hardware 105 * 16AP. not affected - worked around in hardware 106 * 17AP. not affected - worked around in hardware 107 * 18AP. not affected - worked around in hardware 108 * 19AP. not affected - worked around in BIOS 109 * 110 * If this sounds worrying believe me these bugs are either ___RARE___, 111 * or are signal timing bugs worked around in hardware and there's 112 * about nothing of note with C stepping upwards. 113 */ 114 115 static atomic_t stopping_cpu = ATOMIC_INIT(-1); 116 static bool smp_no_nmi_ipi = false; 117 118 /* 119 * this function sends a 'reschedule' IPI to another CPU. 120 * it goes straight through and wastes no time serializing 121 * anything. Worst case is that we lose a reschedule ... 122 */ 123 static void native_smp_send_reschedule(int cpu) 124 { 125 if (unlikely(cpu_is_offline(cpu))) { 126 WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu); 127 return; 128 } 129 apic->send_IPI(cpu, RESCHEDULE_VECTOR); 130 } 131 132 void native_send_call_func_single_ipi(int cpu) 133 { 134 apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); 135 } 136 137 void native_send_call_func_ipi(const struct cpumask *mask) 138 { 139 cpumask_var_t allbutself; 140 141 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) { 142 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 143 return; 144 } 145 146 cpumask_copy(allbutself, cpu_online_mask); 147 __cpumask_clear_cpu(smp_processor_id(), allbutself); 148 149 if (cpumask_equal(mask, allbutself) && 150 cpumask_equal(cpu_online_mask, cpu_callout_mask)) 151 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); 152 else 153 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 154 155 free_cpumask_var(allbutself); 156 } 157 158 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) 159 { 160 /* We are registered on stopping cpu too, avoid spurious NMI */ 161 if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) 162 return NMI_HANDLED; 163 164 cpu_emergency_vmxoff(); 165 stop_this_cpu(NULL); 166 167 return NMI_HANDLED; 168 } 169 170 /* 171 * this function calls the 'stop' function on all other CPUs in the system. 172 */ 173 174 asmlinkage __visible void smp_reboot_interrupt(void) 175 { 176 ipi_entering_ack_irq(); 177 cpu_emergency_vmxoff(); 178 stop_this_cpu(NULL); 179 irq_exit(); 180 } 181 182 static void native_stop_other_cpus(int wait) 183 { 184 unsigned long flags; 185 unsigned long timeout; 186 187 if (reboot_force) 188 return; 189 190 /* 191 * Use an own vector here because smp_call_function 192 * does lots of things not suitable in a panic situation. 193 */ 194 195 /* 196 * We start by using the REBOOT_VECTOR irq. 197 * The irq is treated as a sync point to allow critical 198 * regions of code on other cpus to release their spin locks 199 * and re-enable irqs. Jumping straight to an NMI might 200 * accidentally cause deadlocks with further shutdown/panic 201 * code. By syncing, we give the cpus up to one second to 202 * finish their work before we force them off with the NMI. 203 */ 204 if (num_online_cpus() > 1) { 205 /* did someone beat us here? */ 206 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1) 207 return; 208 209 /* sync above data before sending IRQ */ 210 wmb(); 211 212 apic->send_IPI_allbutself(REBOOT_VECTOR); 213 214 /* 215 * Don't wait longer than a second if the caller 216 * didn't ask us to wait. 217 */ 218 timeout = USEC_PER_SEC; 219 while (num_online_cpus() > 1 && (wait || timeout--)) 220 udelay(1); 221 } 222 223 /* if the REBOOT_VECTOR didn't work, try with the NMI */ 224 if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi)) { 225 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, 226 NMI_FLAG_FIRST, "smp_stop")) 227 /* Note: we ignore failures here */ 228 /* Hope the REBOOT_IRQ is good enough */ 229 goto finish; 230 231 /* sync above data before sending IRQ */ 232 wmb(); 233 234 pr_emerg("Shutting down cpus with NMI\n"); 235 236 apic->send_IPI_allbutself(NMI_VECTOR); 237 238 /* 239 * Don't wait longer than a 10 ms if the caller 240 * didn't ask us to wait. 241 */ 242 timeout = USEC_PER_MSEC * 10; 243 while (num_online_cpus() > 1 && (wait || timeout--)) 244 udelay(1); 245 } 246 247 finish: 248 local_irq_save(flags); 249 disable_local_APIC(); 250 mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); 251 local_irq_restore(flags); 252 } 253 254 /* 255 * Reschedule call back. KVM uses this interrupt to force a cpu out of 256 * guest mode 257 */ 258 __visible void __irq_entry smp_reschedule_interrupt(struct pt_regs *regs) 259 { 260 ack_APIC_irq(); 261 inc_irq_stat(irq_resched_count); 262 kvm_set_cpu_l1tf_flush_l1d(); 263 264 if (trace_resched_ipi_enabled()) { 265 /* 266 * scheduler_ipi() might call irq_enter() as well, but 267 * nested calls are fine. 268 */ 269 irq_enter(); 270 trace_reschedule_entry(RESCHEDULE_VECTOR); 271 scheduler_ipi(); 272 trace_reschedule_exit(RESCHEDULE_VECTOR); 273 irq_exit(); 274 return; 275 } 276 scheduler_ipi(); 277 } 278 279 __visible void __irq_entry smp_call_function_interrupt(struct pt_regs *regs) 280 { 281 ipi_entering_ack_irq(); 282 trace_call_function_entry(CALL_FUNCTION_VECTOR); 283 inc_irq_stat(irq_call_count); 284 generic_smp_call_function_interrupt(); 285 trace_call_function_exit(CALL_FUNCTION_VECTOR); 286 exiting_irq(); 287 } 288 289 __visible void __irq_entry smp_call_function_single_interrupt(struct pt_regs *r) 290 { 291 ipi_entering_ack_irq(); 292 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); 293 inc_irq_stat(irq_call_count); 294 generic_smp_call_function_single_interrupt(); 295 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR); 296 exiting_irq(); 297 } 298 299 static int __init nonmi_ipi_setup(char *str) 300 { 301 smp_no_nmi_ipi = true; 302 return 1; 303 } 304 305 __setup("nonmi_ipi", nonmi_ipi_setup); 306 307 struct smp_ops smp_ops = { 308 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 309 .smp_prepare_cpus = native_smp_prepare_cpus, 310 .smp_cpus_done = native_smp_cpus_done, 311 312 .stop_other_cpus = native_stop_other_cpus, 313 #if defined(CONFIG_KEXEC_CORE) 314 .crash_stop_other_cpus = kdump_nmi_shootdown_cpus, 315 #endif 316 .smp_send_reschedule = native_smp_send_reschedule, 317 318 .cpu_up = native_cpu_up, 319 .cpu_die = native_cpu_die, 320 .cpu_disable = native_cpu_disable, 321 .play_dead = native_play_dead, 322 323 .send_call_func_ipi = native_send_call_func_ipi, 324 .send_call_func_single_ipi = native_send_call_func_single_ipi, 325 }; 326 EXPORT_SYMBOL_GPL(smp_ops); 327