1 /* 2 * Intel SMP support routines. 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * (c) 2002,2003 Andi Kleen, SuSE Labs. 7 * 8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> 9 * 10 * This code is released under the GNU General Public License version 2 or 11 * later. 12 */ 13 14 #include <linux/init.h> 15 16 #include <linux/mm.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/export.h> 20 #include <linux/kernel_stat.h> 21 #include <linux/mc146818rtc.h> 22 #include <linux/cache.h> 23 #include <linux/interrupt.h> 24 #include <linux/cpu.h> 25 #include <linux/gfp.h> 26 27 #include <asm/mtrr.h> 28 #include <asm/tlbflush.h> 29 #include <asm/mmu_context.h> 30 #include <asm/proto.h> 31 #include <asm/apic.h> 32 /* 33 * Some notes on x86 processor bugs affecting SMP operation: 34 * 35 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. 36 * The Linux implications for SMP are handled as follows: 37 * 38 * Pentium III / [Xeon] 39 * None of the E1AP-E3AP errata are visible to the user. 40 * 41 * E1AP. see PII A1AP 42 * E2AP. see PII A2AP 43 * E3AP. see PII A3AP 44 * 45 * Pentium II / [Xeon] 46 * None of the A1AP-A3AP errata are visible to the user. 47 * 48 * A1AP. see PPro 1AP 49 * A2AP. see PPro 2AP 50 * A3AP. see PPro 7AP 51 * 52 * Pentium Pro 53 * None of 1AP-9AP errata are visible to the normal user, 54 * except occasional delivery of 'spurious interrupt' as trap #15. 55 * This is very rare and a non-problem. 56 * 57 * 1AP. Linux maps APIC as non-cacheable 58 * 2AP. worked around in hardware 59 * 3AP. fixed in C0 and above steppings microcode update. 60 * Linux does not use excessive STARTUP_IPIs. 61 * 4AP. worked around in hardware 62 * 5AP. symmetric IO mode (normal Linux operation) not affected. 63 * 'noapic' mode has vector 0xf filled out properly. 64 * 6AP. 'noapic' mode might be affected - fixed in later steppings 65 * 7AP. We do not assume writes to the LVT deassering IRQs 66 * 8AP. We do not enable low power mode (deep sleep) during MP bootup 67 * 9AP. We do not use mixed mode 68 * 69 * Pentium 70 * There is a marginal case where REP MOVS on 100MHz SMP 71 * machines with B stepping processors can fail. XXX should provide 72 * an L1cache=Writethrough or L1cache=off option. 73 * 74 * B stepping CPUs may hang. There are hardware work arounds 75 * for this. We warn about it in case your board doesn't have the work 76 * arounds. Basically that's so I can tell anyone with a B stepping 77 * CPU and SMP problems "tough". 78 * 79 * Specific items [From Pentium Processor Specification Update] 80 * 81 * 1AP. Linux doesn't use remote read 82 * 2AP. Linux doesn't trust APIC errors 83 * 3AP. We work around this 84 * 4AP. Linux never generated 3 interrupts of the same priority 85 * to cause a lost local interrupt. 86 * 5AP. Remote read is never used 87 * 6AP. not affected - worked around in hardware 88 * 7AP. not affected - worked around in hardware 89 * 8AP. worked around in hardware - we get explicit CS errors if not 90 * 9AP. only 'noapic' mode affected. Might generate spurious 91 * interrupts, we log only the first one and count the 92 * rest silently. 93 * 10AP. not affected - worked around in hardware 94 * 11AP. Linux reads the APIC between writes to avoid this, as per 95 * the documentation. Make sure you preserve this as it affects 96 * the C stepping chips too. 97 * 12AP. not affected - worked around in hardware 98 * 13AP. not affected - worked around in hardware 99 * 14AP. we always deassert INIT during bootup 100 * 15AP. not affected - worked around in hardware 101 * 16AP. not affected - worked around in hardware 102 * 17AP. not affected - worked around in hardware 103 * 18AP. not affected - worked around in hardware 104 * 19AP. not affected - worked around in BIOS 105 * 106 * If this sounds worrying believe me these bugs are either ___RARE___, 107 * or are signal timing bugs worked around in hardware and there's 108 * about nothing of note with C stepping upwards. 109 */ 110 111 /* 112 * this function sends a 'reschedule' IPI to another CPU. 113 * it goes straight through and wastes no time serializing 114 * anything. Worst case is that we lose a reschedule ... 115 */ 116 static void native_smp_send_reschedule(int cpu) 117 { 118 if (unlikely(cpu_is_offline(cpu))) { 119 WARN_ON(1); 120 return; 121 } 122 apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR); 123 } 124 125 void native_send_call_func_single_ipi(int cpu) 126 { 127 apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR); 128 } 129 130 void native_send_call_func_ipi(const struct cpumask *mask) 131 { 132 cpumask_var_t allbutself; 133 134 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) { 135 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 136 return; 137 } 138 139 cpumask_copy(allbutself, cpu_online_mask); 140 cpumask_clear_cpu(smp_processor_id(), allbutself); 141 142 if (cpumask_equal(mask, allbutself) && 143 cpumask_equal(cpu_online_mask, cpu_callout_mask)) 144 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); 145 else 146 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 147 148 free_cpumask_var(allbutself); 149 } 150 151 /* 152 * this function calls the 'stop' function on all other CPUs in the system. 153 */ 154 155 asmlinkage void smp_reboot_interrupt(void) 156 { 157 ack_APIC_irq(); 158 irq_enter(); 159 stop_this_cpu(NULL); 160 irq_exit(); 161 } 162 163 static void native_stop_other_cpus(int wait) 164 { 165 unsigned long flags; 166 unsigned long timeout; 167 168 if (reboot_force) 169 return; 170 171 /* 172 * Use an own vector here because smp_call_function 173 * does lots of things not suitable in a panic situation. 174 * On most systems we could also use an NMI here, 175 * but there are a few systems around where NMI 176 * is problematic so stay with an non NMI for now 177 * (this implies we cannot stop CPUs spinning with irq off 178 * currently) 179 */ 180 if (num_online_cpus() > 1) { 181 apic->send_IPI_allbutself(REBOOT_VECTOR); 182 183 /* 184 * Don't wait longer than a second if the caller 185 * didn't ask us to wait. 186 */ 187 timeout = USEC_PER_SEC; 188 while (num_online_cpus() > 1 && (wait || timeout--)) 189 udelay(1); 190 } 191 192 local_irq_save(flags); 193 disable_local_APIC(); 194 local_irq_restore(flags); 195 } 196 197 /* 198 * Reschedule call back. 199 */ 200 void smp_reschedule_interrupt(struct pt_regs *regs) 201 { 202 ack_APIC_irq(); 203 inc_irq_stat(irq_resched_count); 204 scheduler_ipi(); 205 /* 206 * KVM uses this interrupt to force a cpu out of guest mode 207 */ 208 } 209 210 void smp_call_function_interrupt(struct pt_regs *regs) 211 { 212 ack_APIC_irq(); 213 irq_enter(); 214 generic_smp_call_function_interrupt(); 215 inc_irq_stat(irq_call_count); 216 irq_exit(); 217 } 218 219 void smp_call_function_single_interrupt(struct pt_regs *regs) 220 { 221 ack_APIC_irq(); 222 irq_enter(); 223 generic_smp_call_function_single_interrupt(); 224 inc_irq_stat(irq_call_count); 225 irq_exit(); 226 } 227 228 struct smp_ops smp_ops = { 229 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 230 .smp_prepare_cpus = native_smp_prepare_cpus, 231 .smp_cpus_done = native_smp_cpus_done, 232 233 .stop_other_cpus = native_stop_other_cpus, 234 .smp_send_reschedule = native_smp_send_reschedule, 235 236 .cpu_up = native_cpu_up, 237 .cpu_die = native_cpu_die, 238 .cpu_disable = native_cpu_disable, 239 .play_dead = native_play_dead, 240 241 .send_call_func_ipi = native_send_call_func_ipi, 242 .send_call_func_single_ipi = native_send_call_func_single_ipi, 243 }; 244 EXPORT_SYMBOL_GPL(smp_ops); 245