1 /* 2 * This file contains work-arounds for x86 and x86_64 platform bugs. 3 */ 4 #include <linux/pci.h> 5 #include <linux/irq.h> 6 7 #include <asm/hpet.h> 8 9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) 10 11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) 12 { 13 u8 config, rev; 14 u16 word; 15 16 /* BIOS may enable hardware IRQ balancing for 17 * E7520/E7320/E7525(revision ID 0x9 and below) 18 * based platforms. 19 * Disable SW irqbalance/affinity on those platforms. 20 */ 21 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 22 if (rev > 0x9) 23 return; 24 25 /* enable access to config space*/ 26 pci_read_config_byte(dev, 0xf4, &config); 27 pci_write_config_byte(dev, 0xf4, config|0x2); 28 29 /* 30 * read xTPR register. We may not have a pci_dev for device 8 31 * because it might be hidden until the above write. 32 */ 33 pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word); 34 35 if (!(word & (1 << 13))) { 36 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " 37 "disabling irq balancing and affinity\n"); 38 noirqdebug_setup(""); 39 #ifdef CONFIG_PROC_FS 40 no_irq_affinity = 1; 41 #endif 42 } 43 44 /* put back the original value for config space*/ 45 if (!(config & 0x2)) 46 pci_write_config_byte(dev, 0xf4, config); 47 } 48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, 49 quirk_intel_irqbalance); 50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, 51 quirk_intel_irqbalance); 52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, 53 quirk_intel_irqbalance); 54 #endif 55 56 #if defined(CONFIG_HPET_TIMER) 57 unsigned long force_hpet_address; 58 59 static enum { 60 NONE_FORCE_HPET_RESUME, 61 OLD_ICH_FORCE_HPET_RESUME, 62 ICH_FORCE_HPET_RESUME, 63 VT8237_FORCE_HPET_RESUME, 64 NVIDIA_FORCE_HPET_RESUME, 65 ATI_FORCE_HPET_RESUME, 66 } force_hpet_resume_type; 67 68 static void __iomem *rcba_base; 69 70 static void ich_force_hpet_resume(void) 71 { 72 u32 val; 73 74 if (!force_hpet_address) 75 return; 76 77 if (rcba_base == NULL) 78 BUG(); 79 80 /* read the Function Disable register, dword mode only */ 81 val = readl(rcba_base + 0x3404); 82 if (!(val & 0x80)) { 83 /* HPET disabled in HPTC. Trying to enable */ 84 writel(val | 0x80, rcba_base + 0x3404); 85 } 86 87 val = readl(rcba_base + 0x3404); 88 if (!(val & 0x80)) 89 BUG(); 90 else 91 printk(KERN_DEBUG "Force enabled HPET at resume\n"); 92 93 return; 94 } 95 96 static void ich_force_enable_hpet(struct pci_dev *dev) 97 { 98 u32 val; 99 u32 uninitialized_var(rcba); 100 int err = 0; 101 102 if (hpet_address || force_hpet_address) 103 return; 104 105 pci_read_config_dword(dev, 0xF0, &rcba); 106 rcba &= 0xFFFFC000; 107 if (rcba == 0) { 108 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; " 109 "cannot force enable HPET\n"); 110 return; 111 } 112 113 /* use bits 31:14, 16 kB aligned */ 114 rcba_base = ioremap_nocache(rcba, 0x4000); 115 if (rcba_base == NULL) { 116 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " 117 "cannot force enable HPET\n"); 118 return; 119 } 120 121 /* read the Function Disable register, dword mode only */ 122 val = readl(rcba_base + 0x3404); 123 124 if (val & 0x80) { 125 /* HPET is enabled in HPTC. Just not reported by BIOS */ 126 val = val & 0x3; 127 force_hpet_address = 0xFED00000 | (val << 12); 128 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 129 "0x%lx\n", force_hpet_address); 130 iounmap(rcba_base); 131 return; 132 } 133 134 /* HPET disabled in HPTC. Trying to enable */ 135 writel(val | 0x80, rcba_base + 0x3404); 136 137 val = readl(rcba_base + 0x3404); 138 if (!(val & 0x80)) { 139 err = 1; 140 } else { 141 val = val & 0x3; 142 force_hpet_address = 0xFED00000 | (val << 12); 143 } 144 145 if (err) { 146 force_hpet_address = 0; 147 iounmap(rcba_base); 148 dev_printk(KERN_DEBUG, &dev->dev, 149 "Failed to force enable HPET\n"); 150 } else { 151 force_hpet_resume_type = ICH_FORCE_HPET_RESUME; 152 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 153 "0x%lx\n", force_hpet_address); 154 } 155 } 156 157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, 158 ich_force_enable_hpet); 159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, 160 ich_force_enable_hpet); 161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, 162 ich_force_enable_hpet); 163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, 164 ich_force_enable_hpet); 165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, 166 ich_force_enable_hpet); 167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, 168 ich_force_enable_hpet); 169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, 170 ich_force_enable_hpet); 171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, 172 ich_force_enable_hpet); 173 174 175 static struct pci_dev *cached_dev; 176 177 static void hpet_print_force_info(void) 178 { 179 printk(KERN_INFO "HPET not enabled in BIOS. " 180 "You might try hpet=force boot option\n"); 181 } 182 183 static void old_ich_force_hpet_resume(void) 184 { 185 u32 val; 186 u32 uninitialized_var(gen_cntl); 187 188 if (!force_hpet_address || !cached_dev) 189 return; 190 191 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); 192 gen_cntl &= (~(0x7 << 15)); 193 gen_cntl |= (0x4 << 15); 194 195 pci_write_config_dword(cached_dev, 0xD0, gen_cntl); 196 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); 197 val = gen_cntl >> 15; 198 val &= 0x7; 199 if (val == 0x4) 200 printk(KERN_DEBUG "Force enabled HPET at resume\n"); 201 else 202 BUG(); 203 } 204 205 static void old_ich_force_enable_hpet(struct pci_dev *dev) 206 { 207 u32 val; 208 u32 uninitialized_var(gen_cntl); 209 210 if (hpet_address || force_hpet_address) 211 return; 212 213 pci_read_config_dword(dev, 0xD0, &gen_cntl); 214 /* 215 * Bit 17 is HPET enable bit. 216 * Bit 16:15 control the HPET base address. 217 */ 218 val = gen_cntl >> 15; 219 val &= 0x7; 220 if (val & 0x4) { 221 val &= 0x3; 222 force_hpet_address = 0xFED00000 | (val << 12); 223 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", 224 force_hpet_address); 225 return; 226 } 227 228 /* 229 * HPET is disabled. Trying enabling at FED00000 and check 230 * whether it sticks 231 */ 232 gen_cntl &= (~(0x7 << 15)); 233 gen_cntl |= (0x4 << 15); 234 pci_write_config_dword(dev, 0xD0, gen_cntl); 235 236 pci_read_config_dword(dev, 0xD0, &gen_cntl); 237 238 val = gen_cntl >> 15; 239 val &= 0x7; 240 if (val & 0x4) { 241 /* HPET is enabled in HPTC. Just not reported by BIOS */ 242 val &= 0x3; 243 force_hpet_address = 0xFED00000 | (val << 12); 244 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 245 "0x%lx\n", force_hpet_address); 246 cached_dev = dev; 247 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; 248 return; 249 } 250 251 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); 252 } 253 254 /* 255 * Undocumented chipset features. Make sure that the user enforced 256 * this. 257 */ 258 static void old_ich_force_enable_hpet_user(struct pci_dev *dev) 259 { 260 if (hpet_force_user) 261 old_ich_force_enable_hpet(dev); 262 else 263 hpet_print_force_info(); 264 } 265 266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, 267 old_ich_force_enable_hpet_user); 268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, 269 old_ich_force_enable_hpet_user); 270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, 271 old_ich_force_enable_hpet_user); 272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, 273 old_ich_force_enable_hpet_user); 274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, 275 old_ich_force_enable_hpet_user); 276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, 277 old_ich_force_enable_hpet); 278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12, 279 old_ich_force_enable_hpet); 280 281 282 static void vt8237_force_hpet_resume(void) 283 { 284 u32 val; 285 286 if (!force_hpet_address || !cached_dev) 287 return; 288 289 val = 0xfed00000 | 0x80; 290 pci_write_config_dword(cached_dev, 0x68, val); 291 292 pci_read_config_dword(cached_dev, 0x68, &val); 293 if (val & 0x80) 294 printk(KERN_DEBUG "Force enabled HPET at resume\n"); 295 else 296 BUG(); 297 } 298 299 static void vt8237_force_enable_hpet(struct pci_dev *dev) 300 { 301 u32 uninitialized_var(val); 302 303 if (hpet_address || force_hpet_address) 304 return; 305 306 if (!hpet_force_user) { 307 hpet_print_force_info(); 308 return; 309 } 310 311 pci_read_config_dword(dev, 0x68, &val); 312 /* 313 * Bit 7 is HPET enable bit. 314 * Bit 31:10 is HPET base address (contrary to what datasheet claims) 315 */ 316 if (val & 0x80) { 317 force_hpet_address = (val & ~0x3ff); 318 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", 319 force_hpet_address); 320 return; 321 } 322 323 /* 324 * HPET is disabled. Trying enabling at FED00000 and check 325 * whether it sticks 326 */ 327 val = 0xfed00000 | 0x80; 328 pci_write_config_dword(dev, 0x68, val); 329 330 pci_read_config_dword(dev, 0x68, &val); 331 if (val & 0x80) { 332 force_hpet_address = (val & ~0x3ff); 333 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 334 "0x%lx\n", force_hpet_address); 335 cached_dev = dev; 336 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; 337 return; 338 } 339 340 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); 341 } 342 343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 344 vt8237_force_enable_hpet); 345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, 346 vt8237_force_enable_hpet); 347 348 static void ati_force_hpet_resume(void) 349 { 350 pci_write_config_dword(cached_dev, 0x14, 0xfed00000); 351 printk(KERN_DEBUG "Force enabled HPET at resume\n"); 352 } 353 354 static u32 ati_ixp4x0_rev(struct pci_dev *dev) 355 { 356 u32 d; 357 u8 b; 358 359 pci_read_config_byte(dev, 0xac, &b); 360 b &= ~(1<<5); 361 pci_write_config_byte(dev, 0xac, b); 362 pci_read_config_dword(dev, 0x70, &d); 363 d |= 1<<8; 364 pci_write_config_dword(dev, 0x70, d); 365 pci_read_config_dword(dev, 0x8, &d); 366 d &= 0xff; 367 dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d); 368 return d; 369 } 370 371 static void ati_force_enable_hpet(struct pci_dev *dev) 372 { 373 u32 d, val; 374 u8 b; 375 376 if (hpet_address || force_hpet_address) 377 return; 378 379 if (!hpet_force_user) { 380 hpet_print_force_info(); 381 return; 382 } 383 384 d = ati_ixp4x0_rev(dev); 385 if (d < 0x82) 386 return; 387 388 /* base address */ 389 pci_write_config_dword(dev, 0x14, 0xfed00000); 390 pci_read_config_dword(dev, 0x14, &val); 391 392 /* enable interrupt */ 393 outb(0x72, 0xcd6); b = inb(0xcd7); 394 b |= 0x1; 395 outb(0x72, 0xcd6); outb(b, 0xcd7); 396 outb(0x72, 0xcd6); b = inb(0xcd7); 397 if (!(b & 0x1)) 398 return; 399 pci_read_config_dword(dev, 0x64, &d); 400 d |= (1<<10); 401 pci_write_config_dword(dev, 0x64, d); 402 pci_read_config_dword(dev, 0x64, &d); 403 if (!(d & (1<<10))) 404 return; 405 406 force_hpet_address = val; 407 force_hpet_resume_type = ATI_FORCE_HPET_RESUME; 408 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", 409 force_hpet_address); 410 cached_dev = dev; 411 } 412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, 413 ati_force_enable_hpet); 414 415 /* 416 * Undocumented chipset feature taken from LinuxBIOS. 417 */ 418 static void nvidia_force_hpet_resume(void) 419 { 420 pci_write_config_dword(cached_dev, 0x44, 0xfed00001); 421 printk(KERN_DEBUG "Force enabled HPET at resume\n"); 422 } 423 424 static void nvidia_force_enable_hpet(struct pci_dev *dev) 425 { 426 u32 uninitialized_var(val); 427 428 if (hpet_address || force_hpet_address) 429 return; 430 431 if (!hpet_force_user) { 432 hpet_print_force_info(); 433 return; 434 } 435 436 pci_write_config_dword(dev, 0x44, 0xfed00001); 437 pci_read_config_dword(dev, 0x44, &val); 438 force_hpet_address = val & 0xfffffffe; 439 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; 440 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", 441 force_hpet_address); 442 cached_dev = dev; 443 return; 444 } 445 446 /* ISA Bridges */ 447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050, 448 nvidia_force_enable_hpet); 449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051, 450 nvidia_force_enable_hpet); 451 452 /* LPC bridges */ 453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260, 454 nvidia_force_enable_hpet); 455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360, 456 nvidia_force_enable_hpet); 457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361, 458 nvidia_force_enable_hpet); 459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362, 460 nvidia_force_enable_hpet); 461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363, 462 nvidia_force_enable_hpet); 463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364, 464 nvidia_force_enable_hpet); 465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365, 466 nvidia_force_enable_hpet); 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366, 468 nvidia_force_enable_hpet); 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367, 470 nvidia_force_enable_hpet); 471 472 void force_hpet_resume(void) 473 { 474 switch (force_hpet_resume_type) { 475 case ICH_FORCE_HPET_RESUME: 476 ich_force_hpet_resume(); 477 return; 478 case OLD_ICH_FORCE_HPET_RESUME: 479 old_ich_force_hpet_resume(); 480 return; 481 case VT8237_FORCE_HPET_RESUME: 482 vt8237_force_hpet_resume(); 483 return; 484 case NVIDIA_FORCE_HPET_RESUME: 485 nvidia_force_hpet_resume(); 486 return; 487 case ATI_FORCE_HPET_RESUME: 488 ati_force_hpet_resume(); 489 return; 490 default: 491 break; 492 } 493 } 494 495 #endif 496