1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/errno.h> 5 #include <linux/kernel.h> 6 #include <linux/mm.h> 7 #include <linux/smp.h> 8 #include <linux/prctl.h> 9 #include <linux/slab.h> 10 #include <linux/sched.h> 11 #include <linux/sched/idle.h> 12 #include <linux/sched/debug.h> 13 #include <linux/sched/task.h> 14 #include <linux/sched/task_stack.h> 15 #include <linux/init.h> 16 #include <linux/export.h> 17 #include <linux/pm.h> 18 #include <linux/tick.h> 19 #include <linux/random.h> 20 #include <linux/user-return-notifier.h> 21 #include <linux/dmi.h> 22 #include <linux/utsname.h> 23 #include <linux/stackprotector.h> 24 #include <linux/cpuidle.h> 25 #include <linux/acpi.h> 26 #include <linux/elf-randomize.h> 27 #include <trace/events/power.h> 28 #include <linux/hw_breakpoint.h> 29 #include <asm/cpu.h> 30 #include <asm/apic.h> 31 #include <linux/uaccess.h> 32 #include <asm/mwait.h> 33 #include <asm/fpu/internal.h> 34 #include <asm/debugreg.h> 35 #include <asm/nmi.h> 36 #include <asm/tlbflush.h> 37 #include <asm/mce.h> 38 #include <asm/vm86.h> 39 #include <asm/switch_to.h> 40 #include <asm/desc.h> 41 #include <asm/prctl.h> 42 #include <asm/spec-ctrl.h> 43 #include <asm/io_bitmap.h> 44 #include <asm/proto.h> 45 #include <asm/frame.h> 46 47 #include "process.h" 48 49 /* 50 * per-CPU TSS segments. Threads are completely 'soft' on Linux, 51 * no more per-task TSS's. The TSS size is kept cacheline-aligned 52 * so they are allowed to end up in the .data..cacheline_aligned 53 * section. Since TSS's are completely CPU-local, we want them 54 * on exact cacheline boundaries, to eliminate cacheline ping-pong. 55 */ 56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { 57 .x86_tss = { 58 /* 59 * .sp0 is only used when entering ring 0 from a lower 60 * privilege level. Since the init task never runs anything 61 * but ring 0 code, there is no need for a valid value here. 62 * Poison it. 63 */ 64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, 65 66 #ifdef CONFIG_X86_32 67 .sp1 = TOP_OF_INIT_STACK, 68 69 .ss0 = __KERNEL_DS, 70 .ss1 = __KERNEL_CS, 71 #endif 72 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, 73 }, 74 }; 75 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); 76 77 DEFINE_PER_CPU(bool, __tss_limit_invalid); 78 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); 79 80 /* 81 * this gets called so that we can store lazy state into memory and copy the 82 * current task into the new thread. 83 */ 84 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 85 { 86 memcpy(dst, src, arch_task_struct_size); 87 #ifdef CONFIG_VM86 88 dst->thread.vm86 = NULL; 89 #endif 90 91 return fpu__copy(dst, src); 92 } 93 94 /* 95 * Free thread data structures etc.. 96 */ 97 void exit_thread(struct task_struct *tsk) 98 { 99 struct thread_struct *t = &tsk->thread; 100 struct fpu *fpu = &t->fpu; 101 102 if (test_thread_flag(TIF_IO_BITMAP)) 103 io_bitmap_exit(tsk); 104 105 free_vm86(t); 106 107 fpu__drop(fpu); 108 } 109 110 static int set_new_tls(struct task_struct *p, unsigned long tls) 111 { 112 struct user_desc __user *utls = (struct user_desc __user *)tls; 113 114 if (in_ia32_syscall()) 115 return do_set_thread_area(p, -1, utls, 0); 116 else 117 return do_set_thread_area_64(p, ARCH_SET_FS, tls); 118 } 119 120 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, 121 struct task_struct *p, unsigned long tls) 122 { 123 struct inactive_task_frame *frame; 124 struct fork_frame *fork_frame; 125 struct pt_regs *childregs; 126 int ret = 0; 127 128 childregs = task_pt_regs(p); 129 fork_frame = container_of(childregs, struct fork_frame, regs); 130 frame = &fork_frame->frame; 131 132 frame->bp = encode_frame_pointer(childregs); 133 frame->ret_addr = (unsigned long) ret_from_fork; 134 p->thread.sp = (unsigned long) fork_frame; 135 p->thread.io_bitmap = NULL; 136 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 137 138 #ifdef CONFIG_X86_64 139 current_save_fsgs(); 140 p->thread.fsindex = current->thread.fsindex; 141 p->thread.fsbase = current->thread.fsbase; 142 p->thread.gsindex = current->thread.gsindex; 143 p->thread.gsbase = current->thread.gsbase; 144 145 savesegment(es, p->thread.es); 146 savesegment(ds, p->thread.ds); 147 #else 148 p->thread.sp0 = (unsigned long) (childregs + 1); 149 /* 150 * Clear all status flags including IF and set fixed bit. 64bit 151 * does not have this initialization as the frame does not contain 152 * flags. The flags consistency (especially vs. AC) is there 153 * ensured via objtool, which lacks 32bit support. 154 */ 155 frame->flags = X86_EFLAGS_FIXED; 156 #endif 157 158 /* Kernel thread ? */ 159 if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) { 160 memset(childregs, 0, sizeof(struct pt_regs)); 161 kthread_frame_init(frame, sp, arg); 162 return 0; 163 } 164 165 frame->bx = 0; 166 *childregs = *current_pt_regs(); 167 childregs->ax = 0; 168 if (sp) 169 childregs->sp = sp; 170 171 #ifdef CONFIG_X86_32 172 task_user_gs(p) = get_user_gs(current_pt_regs()); 173 #endif 174 175 /* Set a new TLS for the child thread? */ 176 if (clone_flags & CLONE_SETTLS) 177 ret = set_new_tls(p, tls); 178 179 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) 180 io_bitmap_share(p); 181 182 return ret; 183 } 184 185 void flush_thread(void) 186 { 187 struct task_struct *tsk = current; 188 189 flush_ptrace_hw_breakpoint(tsk); 190 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 191 192 fpu__clear_all(&tsk->thread.fpu); 193 } 194 195 void disable_TSC(void) 196 { 197 preempt_disable(); 198 if (!test_and_set_thread_flag(TIF_NOTSC)) 199 /* 200 * Must flip the CPU state synchronously with 201 * TIF_NOTSC in the current running context. 202 */ 203 cr4_set_bits(X86_CR4_TSD); 204 preempt_enable(); 205 } 206 207 static void enable_TSC(void) 208 { 209 preempt_disable(); 210 if (test_and_clear_thread_flag(TIF_NOTSC)) 211 /* 212 * Must flip the CPU state synchronously with 213 * TIF_NOTSC in the current running context. 214 */ 215 cr4_clear_bits(X86_CR4_TSD); 216 preempt_enable(); 217 } 218 219 int get_tsc_mode(unsigned long adr) 220 { 221 unsigned int val; 222 223 if (test_thread_flag(TIF_NOTSC)) 224 val = PR_TSC_SIGSEGV; 225 else 226 val = PR_TSC_ENABLE; 227 228 return put_user(val, (unsigned int __user *)adr); 229 } 230 231 int set_tsc_mode(unsigned int val) 232 { 233 if (val == PR_TSC_SIGSEGV) 234 disable_TSC(); 235 else if (val == PR_TSC_ENABLE) 236 enable_TSC(); 237 else 238 return -EINVAL; 239 240 return 0; 241 } 242 243 DEFINE_PER_CPU(u64, msr_misc_features_shadow); 244 245 static void set_cpuid_faulting(bool on) 246 { 247 u64 msrval; 248 249 msrval = this_cpu_read(msr_misc_features_shadow); 250 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 251 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 252 this_cpu_write(msr_misc_features_shadow, msrval); 253 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); 254 } 255 256 static void disable_cpuid(void) 257 { 258 preempt_disable(); 259 if (!test_and_set_thread_flag(TIF_NOCPUID)) { 260 /* 261 * Must flip the CPU state synchronously with 262 * TIF_NOCPUID in the current running context. 263 */ 264 set_cpuid_faulting(true); 265 } 266 preempt_enable(); 267 } 268 269 static void enable_cpuid(void) 270 { 271 preempt_disable(); 272 if (test_and_clear_thread_flag(TIF_NOCPUID)) { 273 /* 274 * Must flip the CPU state synchronously with 275 * TIF_NOCPUID in the current running context. 276 */ 277 set_cpuid_faulting(false); 278 } 279 preempt_enable(); 280 } 281 282 static int get_cpuid_mode(void) 283 { 284 return !test_thread_flag(TIF_NOCPUID); 285 } 286 287 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) 288 { 289 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) 290 return -ENODEV; 291 292 if (cpuid_enabled) 293 enable_cpuid(); 294 else 295 disable_cpuid(); 296 297 return 0; 298 } 299 300 /* 301 * Called immediately after a successful exec. 302 */ 303 void arch_setup_new_exec(void) 304 { 305 /* If cpuid was previously disabled for this task, re-enable it. */ 306 if (test_thread_flag(TIF_NOCPUID)) 307 enable_cpuid(); 308 309 /* 310 * Don't inherit TIF_SSBD across exec boundary when 311 * PR_SPEC_DISABLE_NOEXEC is used. 312 */ 313 if (test_thread_flag(TIF_SSBD) && 314 task_spec_ssb_noexec(current)) { 315 clear_thread_flag(TIF_SSBD); 316 task_clear_spec_ssb_disable(current); 317 task_clear_spec_ssb_noexec(current); 318 speculation_ctrl_update(task_thread_info(current)->flags); 319 } 320 } 321 322 #ifdef CONFIG_X86_IOPL_IOPERM 323 static inline void switch_to_bitmap(unsigned long tifp) 324 { 325 /* 326 * Invalidate I/O bitmap if the previous task used it. This prevents 327 * any possible leakage of an active I/O bitmap. 328 * 329 * If the next task has an I/O bitmap it will handle it on exit to 330 * user mode. 331 */ 332 if (tifp & _TIF_IO_BITMAP) 333 tss_invalidate_io_bitmap(); 334 } 335 336 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) 337 { 338 /* 339 * Copy at least the byte range of the incoming tasks bitmap which 340 * covers the permitted I/O ports. 341 * 342 * If the previous task which used an I/O bitmap had more bits 343 * permitted, then the copy needs to cover those as well so they 344 * get turned off. 345 */ 346 memcpy(tss->io_bitmap.bitmap, iobm->bitmap, 347 max(tss->io_bitmap.prev_max, iobm->max)); 348 349 /* 350 * Store the new max and the sequence number of this bitmap 351 * and a pointer to the bitmap itself. 352 */ 353 tss->io_bitmap.prev_max = iobm->max; 354 tss->io_bitmap.prev_sequence = iobm->sequence; 355 } 356 357 /** 358 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode 359 */ 360 void native_tss_update_io_bitmap(void) 361 { 362 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 363 struct thread_struct *t = ¤t->thread; 364 u16 *base = &tss->x86_tss.io_bitmap_base; 365 366 if (!test_thread_flag(TIF_IO_BITMAP)) { 367 native_tss_invalidate_io_bitmap(); 368 return; 369 } 370 371 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { 372 *base = IO_BITMAP_OFFSET_VALID_ALL; 373 } else { 374 struct io_bitmap *iobm = t->io_bitmap; 375 376 /* 377 * Only copy bitmap data when the sequence number differs. The 378 * update time is accounted to the incoming task. 379 */ 380 if (tss->io_bitmap.prev_sequence != iobm->sequence) 381 tss_copy_io_bitmap(tss, iobm); 382 383 /* Enable the bitmap */ 384 *base = IO_BITMAP_OFFSET_VALID_MAP; 385 } 386 387 /* 388 * Make sure that the TSS limit is covering the IO bitmap. It might have 389 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 390 * access from user space to trigger a #GP because tbe bitmap is outside 391 * the TSS limit. 392 */ 393 refresh_tss_limit(); 394 } 395 #else /* CONFIG_X86_IOPL_IOPERM */ 396 static inline void switch_to_bitmap(unsigned long tifp) { } 397 #endif 398 399 #ifdef CONFIG_SMP 400 401 struct ssb_state { 402 struct ssb_state *shared_state; 403 raw_spinlock_t lock; 404 unsigned int disable_state; 405 unsigned long local_state; 406 }; 407 408 #define LSTATE_SSB 0 409 410 static DEFINE_PER_CPU(struct ssb_state, ssb_state); 411 412 void speculative_store_bypass_ht_init(void) 413 { 414 struct ssb_state *st = this_cpu_ptr(&ssb_state); 415 unsigned int this_cpu = smp_processor_id(); 416 unsigned int cpu; 417 418 st->local_state = 0; 419 420 /* 421 * Shared state setup happens once on the first bringup 422 * of the CPU. It's not destroyed on CPU hotunplug. 423 */ 424 if (st->shared_state) 425 return; 426 427 raw_spin_lock_init(&st->lock); 428 429 /* 430 * Go over HT siblings and check whether one of them has set up the 431 * shared state pointer already. 432 */ 433 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { 434 if (cpu == this_cpu) 435 continue; 436 437 if (!per_cpu(ssb_state, cpu).shared_state) 438 continue; 439 440 /* Link it to the state of the sibling: */ 441 st->shared_state = per_cpu(ssb_state, cpu).shared_state; 442 return; 443 } 444 445 /* 446 * First HT sibling to come up on the core. Link shared state of 447 * the first HT sibling to itself. The siblings on the same core 448 * which come up later will see the shared state pointer and link 449 * themselves to the state of this CPU. 450 */ 451 st->shared_state = st; 452 } 453 454 /* 455 * Logic is: First HT sibling enables SSBD for both siblings in the core 456 * and last sibling to disable it, disables it for the whole core. This how 457 * MSR_SPEC_CTRL works in "hardware": 458 * 459 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL 460 */ 461 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 462 { 463 struct ssb_state *st = this_cpu_ptr(&ssb_state); 464 u64 msr = x86_amd_ls_cfg_base; 465 466 if (!static_cpu_has(X86_FEATURE_ZEN)) { 467 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 468 wrmsrl(MSR_AMD64_LS_CFG, msr); 469 return; 470 } 471 472 if (tifn & _TIF_SSBD) { 473 /* 474 * Since this can race with prctl(), block reentry on the 475 * same CPU. 476 */ 477 if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) 478 return; 479 480 msr |= x86_amd_ls_cfg_ssbd_mask; 481 482 raw_spin_lock(&st->shared_state->lock); 483 /* First sibling enables SSBD: */ 484 if (!st->shared_state->disable_state) 485 wrmsrl(MSR_AMD64_LS_CFG, msr); 486 st->shared_state->disable_state++; 487 raw_spin_unlock(&st->shared_state->lock); 488 } else { 489 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) 490 return; 491 492 raw_spin_lock(&st->shared_state->lock); 493 st->shared_state->disable_state--; 494 if (!st->shared_state->disable_state) 495 wrmsrl(MSR_AMD64_LS_CFG, msr); 496 raw_spin_unlock(&st->shared_state->lock); 497 } 498 } 499 #else 500 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 501 { 502 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 503 504 wrmsrl(MSR_AMD64_LS_CFG, msr); 505 } 506 #endif 507 508 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) 509 { 510 /* 511 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 512 * so ssbd_tif_to_spec_ctrl() just works. 513 */ 514 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 515 } 516 517 /* 518 * Update the MSRs managing speculation control, during context switch. 519 * 520 * tifp: Previous task's thread flags 521 * tifn: Next task's thread flags 522 */ 523 static __always_inline void __speculation_ctrl_update(unsigned long tifp, 524 unsigned long tifn) 525 { 526 unsigned long tif_diff = tifp ^ tifn; 527 u64 msr = x86_spec_ctrl_base; 528 bool updmsr = false; 529 530 lockdep_assert_irqs_disabled(); 531 532 /* Handle change of TIF_SSBD depending on the mitigation method. */ 533 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { 534 if (tif_diff & _TIF_SSBD) 535 amd_set_ssb_virt_state(tifn); 536 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { 537 if (tif_diff & _TIF_SSBD) 538 amd_set_core_ssb_state(tifn); 539 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 540 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 541 updmsr |= !!(tif_diff & _TIF_SSBD); 542 msr |= ssbd_tif_to_spec_ctrl(tifn); 543 } 544 545 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ 546 if (IS_ENABLED(CONFIG_SMP) && 547 static_branch_unlikely(&switch_to_cond_stibp)) { 548 updmsr |= !!(tif_diff & _TIF_SPEC_IB); 549 msr |= stibp_tif_to_spec_ctrl(tifn); 550 } 551 552 if (updmsr) 553 wrmsrl(MSR_IA32_SPEC_CTRL, msr); 554 } 555 556 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) 557 { 558 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { 559 if (task_spec_ssb_disable(tsk)) 560 set_tsk_thread_flag(tsk, TIF_SSBD); 561 else 562 clear_tsk_thread_flag(tsk, TIF_SSBD); 563 564 if (task_spec_ib_disable(tsk)) 565 set_tsk_thread_flag(tsk, TIF_SPEC_IB); 566 else 567 clear_tsk_thread_flag(tsk, TIF_SPEC_IB); 568 } 569 /* Return the updated threadinfo flags*/ 570 return task_thread_info(tsk)->flags; 571 } 572 573 void speculation_ctrl_update(unsigned long tif) 574 { 575 unsigned long flags; 576 577 /* Forced update. Make sure all relevant TIF flags are different */ 578 local_irq_save(flags); 579 __speculation_ctrl_update(~tif, tif); 580 local_irq_restore(flags); 581 } 582 583 /* Called from seccomp/prctl update */ 584 void speculation_ctrl_update_current(void) 585 { 586 preempt_disable(); 587 speculation_ctrl_update(speculation_ctrl_update_tif(current)); 588 preempt_enable(); 589 } 590 591 static inline void cr4_toggle_bits_irqsoff(unsigned long mask) 592 { 593 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 594 595 newval = cr4 ^ mask; 596 if (newval != cr4) { 597 this_cpu_write(cpu_tlbstate.cr4, newval); 598 __write_cr4(newval); 599 } 600 } 601 602 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) 603 { 604 unsigned long tifp, tifn; 605 606 tifn = READ_ONCE(task_thread_info(next_p)->flags); 607 tifp = READ_ONCE(task_thread_info(prev_p)->flags); 608 609 switch_to_bitmap(tifp); 610 611 propagate_user_return_notify(prev_p, next_p); 612 613 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && 614 arch_has_block_step()) { 615 unsigned long debugctl, msk; 616 617 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 618 debugctl &= ~DEBUGCTLMSR_BTF; 619 msk = tifn & _TIF_BLOCKSTEP; 620 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 621 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 622 } 623 624 if ((tifp ^ tifn) & _TIF_NOTSC) 625 cr4_toggle_bits_irqsoff(X86_CR4_TSD); 626 627 if ((tifp ^ tifn) & _TIF_NOCPUID) 628 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); 629 630 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { 631 __speculation_ctrl_update(tifp, tifn); 632 } else { 633 speculation_ctrl_update_tif(prev_p); 634 tifn = speculation_ctrl_update_tif(next_p); 635 636 /* Enforce MSR update to ensure consistent state */ 637 __speculation_ctrl_update(~tifn, tifn); 638 } 639 640 if ((tifp ^ tifn) & _TIF_SLD) 641 switch_to_sld(tifn); 642 } 643 644 /* 645 * Idle related variables and functions 646 */ 647 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; 648 EXPORT_SYMBOL(boot_option_idle_override); 649 650 static void (*x86_idle)(void); 651 652 #ifndef CONFIG_SMP 653 static inline void play_dead(void) 654 { 655 BUG(); 656 } 657 #endif 658 659 void arch_cpu_idle_enter(void) 660 { 661 tsc_verify_tsc_adjust(false); 662 local_touch_nmi(); 663 } 664 665 void arch_cpu_idle_dead(void) 666 { 667 play_dead(); 668 } 669 670 /* 671 * Called from the generic idle code. 672 */ 673 void arch_cpu_idle(void) 674 { 675 x86_idle(); 676 } 677 678 /* 679 * We use this if we don't have any better idle routine.. 680 */ 681 void __cpuidle default_idle(void) 682 { 683 raw_safe_halt(); 684 } 685 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) 686 EXPORT_SYMBOL(default_idle); 687 #endif 688 689 #ifdef CONFIG_XEN 690 bool xen_set_default_idle(void) 691 { 692 bool ret = !!x86_idle; 693 694 x86_idle = default_idle; 695 696 return ret; 697 } 698 #endif 699 700 void stop_this_cpu(void *dummy) 701 { 702 local_irq_disable(); 703 /* 704 * Remove this CPU: 705 */ 706 set_cpu_online(smp_processor_id(), false); 707 disable_local_APIC(); 708 mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); 709 710 /* 711 * Use wbinvd on processors that support SME. This provides support 712 * for performing a successful kexec when going from SME inactive 713 * to SME active (or vice-versa). The cache must be cleared so that 714 * if there are entries with the same physical address, both with and 715 * without the encryption bit, they don't race each other when flushed 716 * and potentially end up with the wrong entry being committed to 717 * memory. 718 */ 719 if (boot_cpu_has(X86_FEATURE_SME)) 720 native_wbinvd(); 721 for (;;) { 722 /* 723 * Use native_halt() so that memory contents don't change 724 * (stack usage and variables) after possibly issuing the 725 * native_wbinvd() above. 726 */ 727 native_halt(); 728 } 729 } 730 731 /* 732 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power 733 * states (local apic timer and TSC stop). 734 * 735 * XXX this function is completely buggered vs RCU and tracing. 736 */ 737 static void amd_e400_idle(void) 738 { 739 /* 740 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E 741 * gets set after static_cpu_has() places have been converted via 742 * alternatives. 743 */ 744 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 745 default_idle(); 746 return; 747 } 748 749 tick_broadcast_enter(); 750 751 default_idle(); 752 753 /* 754 * The switch back from broadcast mode needs to be called with 755 * interrupts disabled. 756 */ 757 raw_local_irq_disable(); 758 tick_broadcast_exit(); 759 raw_local_irq_enable(); 760 } 761 762 /* 763 * Intel Core2 and older machines prefer MWAIT over HALT for C1. 764 * We can't rely on cpuidle installing MWAIT, because it will not load 765 * on systems that support only C1 -- so the boot default must be MWAIT. 766 * 767 * Some AMD machines are the opposite, they depend on using HALT. 768 * 769 * So for default C1, which is used during boot until cpuidle loads, 770 * use MWAIT-C1 on Intel HW that has it, else use HALT. 771 */ 772 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) 773 { 774 if (c->x86_vendor != X86_VENDOR_INTEL) 775 return 0; 776 777 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) 778 return 0; 779 780 return 1; 781 } 782 783 /* 784 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT 785 * with interrupts enabled and no flags, which is backwards compatible with the 786 * original MWAIT implementation. 787 */ 788 static __cpuidle void mwait_idle(void) 789 { 790 if (!current_set_polling_and_test()) { 791 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { 792 mb(); /* quirk */ 793 clflush((void *)¤t_thread_info()->flags); 794 mb(); /* quirk */ 795 } 796 797 __monitor((void *)¤t_thread_info()->flags, 0, 0); 798 if (!need_resched()) 799 __sti_mwait(0, 0); 800 else 801 raw_local_irq_enable(); 802 } else { 803 raw_local_irq_enable(); 804 } 805 __current_clr_polling(); 806 } 807 808 void select_idle_routine(const struct cpuinfo_x86 *c) 809 { 810 #ifdef CONFIG_SMP 811 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) 812 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); 813 #endif 814 if (x86_idle || boot_option_idle_override == IDLE_POLL) 815 return; 816 817 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { 818 pr_info("using AMD E400 aware idle routine\n"); 819 x86_idle = amd_e400_idle; 820 } else if (prefer_mwait_c1_over_halt(c)) { 821 pr_info("using mwait in idle threads\n"); 822 x86_idle = mwait_idle; 823 } else 824 x86_idle = default_idle; 825 } 826 827 void amd_e400_c1e_apic_setup(void) 828 { 829 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 830 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); 831 local_irq_disable(); 832 tick_broadcast_force(); 833 local_irq_enable(); 834 } 835 } 836 837 void __init arch_post_acpi_subsys_init(void) 838 { 839 u32 lo, hi; 840 841 if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) 842 return; 843 844 /* 845 * AMD E400 detection needs to happen after ACPI has been enabled. If 846 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in 847 * MSR_K8_INT_PENDING_MSG. 848 */ 849 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 850 if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) 851 return; 852 853 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); 854 855 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 856 mark_tsc_unstable("TSC halt in AMD C1E"); 857 pr_info("System has AMD C1E enabled\n"); 858 } 859 860 static int __init idle_setup(char *str) 861 { 862 if (!str) 863 return -EINVAL; 864 865 if (!strcmp(str, "poll")) { 866 pr_info("using polling idle threads\n"); 867 boot_option_idle_override = IDLE_POLL; 868 cpu_idle_poll_ctrl(true); 869 } else if (!strcmp(str, "halt")) { 870 /* 871 * When the boot option of idle=halt is added, halt is 872 * forced to be used for CPU idle. In such case CPU C2/C3 873 * won't be used again. 874 * To continue to load the CPU idle driver, don't touch 875 * the boot_option_idle_override. 876 */ 877 x86_idle = default_idle; 878 boot_option_idle_override = IDLE_HALT; 879 } else if (!strcmp(str, "nomwait")) { 880 /* 881 * If the boot option of "idle=nomwait" is added, 882 * it means that mwait will be disabled for CPU C2/C3 883 * states. In such case it won't touch the variable 884 * of boot_option_idle_override. 885 */ 886 boot_option_idle_override = IDLE_NOMWAIT; 887 } else 888 return -1; 889 890 return 0; 891 } 892 early_param("idle", idle_setup); 893 894 unsigned long arch_align_stack(unsigned long sp) 895 { 896 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 897 sp -= get_random_int() % 8192; 898 return sp & ~0xf; 899 } 900 901 unsigned long arch_randomize_brk(struct mm_struct *mm) 902 { 903 return randomize_page(mm->brk, 0x02000000); 904 } 905 906 /* 907 * Called from fs/proc with a reference on @p to find the function 908 * which called into schedule(). This needs to be done carefully 909 * because the task might wake up and we might look at a stack 910 * changing under us. 911 */ 912 unsigned long get_wchan(struct task_struct *p) 913 { 914 unsigned long start, bottom, top, sp, fp, ip, ret = 0; 915 int count = 0; 916 917 if (p == current || p->state == TASK_RUNNING) 918 return 0; 919 920 if (!try_get_task_stack(p)) 921 return 0; 922 923 start = (unsigned long)task_stack_page(p); 924 if (!start) 925 goto out; 926 927 /* 928 * Layout of the stack page: 929 * 930 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) 931 * PADDING 932 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING 933 * stack 934 * ----------- bottom = start 935 * 936 * The tasks stack pointer points at the location where the 937 * framepointer is stored. The data on the stack is: 938 * ... IP FP ... IP FP 939 * 940 * We need to read FP and IP, so we need to adjust the upper 941 * bound by another unsigned long. 942 */ 943 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; 944 top -= 2 * sizeof(unsigned long); 945 bottom = start; 946 947 sp = READ_ONCE(p->thread.sp); 948 if (sp < bottom || sp > top) 949 goto out; 950 951 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); 952 do { 953 if (fp < bottom || fp > top) 954 goto out; 955 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); 956 if (!in_sched_functions(ip)) { 957 ret = ip; 958 goto out; 959 } 960 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); 961 } while (count++ < 16 && p->state != TASK_RUNNING); 962 963 out: 964 put_task_stack(p); 965 return ret; 966 } 967 968 long do_arch_prctl_common(struct task_struct *task, int option, 969 unsigned long cpuid_enabled) 970 { 971 switch (option) { 972 case ARCH_GET_CPUID: 973 return get_cpuid_mode(); 974 case ARCH_SET_CPUID: 975 return set_cpuid_mode(task, cpuid_enabled); 976 } 977 978 return -EINVAL; 979 } 980