1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/errno.h> 5 #include <linux/kernel.h> 6 #include <linux/mm.h> 7 #include <linux/smp.h> 8 #include <linux/cpu.h> 9 #include <linux/prctl.h> 10 #include <linux/slab.h> 11 #include <linux/sched.h> 12 #include <linux/sched/idle.h> 13 #include <linux/sched/debug.h> 14 #include <linux/sched/task.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 #include <linux/pm.h> 19 #include <linux/tick.h> 20 #include <linux/random.h> 21 #include <linux/user-return-notifier.h> 22 #include <linux/dmi.h> 23 #include <linux/utsname.h> 24 #include <linux/stackprotector.h> 25 #include <linux/cpuidle.h> 26 #include <linux/acpi.h> 27 #include <linux/elf-randomize.h> 28 #include <linux/static_call.h> 29 #include <trace/events/power.h> 30 #include <linux/hw_breakpoint.h> 31 #include <linux/entry-common.h> 32 #include <asm/cpu.h> 33 #include <asm/cpuid.h> 34 #include <asm/apic.h> 35 #include <linux/uaccess.h> 36 #include <asm/mwait.h> 37 #include <asm/fpu/api.h> 38 #include <asm/fpu/sched.h> 39 #include <asm/fpu/xstate.h> 40 #include <asm/debugreg.h> 41 #include <asm/nmi.h> 42 #include <asm/tlbflush.h> 43 #include <asm/mce.h> 44 #include <asm/vm86.h> 45 #include <asm/switch_to.h> 46 #include <asm/desc.h> 47 #include <asm/prctl.h> 48 #include <asm/spec-ctrl.h> 49 #include <asm/io_bitmap.h> 50 #include <asm/proto.h> 51 #include <asm/frame.h> 52 #include <asm/unwind.h> 53 #include <asm/tdx.h> 54 #include <asm/mmu_context.h> 55 #include <asm/shstk.h> 56 57 #include "process.h" 58 59 /* 60 * per-CPU TSS segments. Threads are completely 'soft' on Linux, 61 * no more per-task TSS's. The TSS size is kept cacheline-aligned 62 * so they are allowed to end up in the .data..cacheline_aligned 63 * section. Since TSS's are completely CPU-local, we want them 64 * on exact cacheline boundaries, to eliminate cacheline ping-pong. 65 */ 66 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { 67 .x86_tss = { 68 /* 69 * .sp0 is only used when entering ring 0 from a lower 70 * privilege level. Since the init task never runs anything 71 * but ring 0 code, there is no need for a valid value here. 72 * Poison it. 73 */ 74 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, 75 76 #ifdef CONFIG_X86_32 77 .sp1 = TOP_OF_INIT_STACK, 78 79 .ss0 = __KERNEL_DS, 80 .ss1 = __KERNEL_CS, 81 #endif 82 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, 83 }, 84 }; 85 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); 86 87 DEFINE_PER_CPU(bool, __tss_limit_invalid); 88 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); 89 90 /* 91 * this gets called so that we can store lazy state into memory and copy the 92 * current task into the new thread. 93 */ 94 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 95 { 96 memcpy(dst, src, arch_task_struct_size); 97 #ifdef CONFIG_VM86 98 dst->thread.vm86 = NULL; 99 #endif 100 /* Drop the copied pointer to current's fpstate */ 101 dst->thread.fpu.fpstate = NULL; 102 103 return 0; 104 } 105 106 #ifdef CONFIG_X86_64 107 void arch_release_task_struct(struct task_struct *tsk) 108 { 109 if (fpu_state_size_dynamic()) 110 fpstate_free(&tsk->thread.fpu); 111 } 112 #endif 113 114 /* 115 * Free thread data structures etc.. 116 */ 117 void exit_thread(struct task_struct *tsk) 118 { 119 struct thread_struct *t = &tsk->thread; 120 struct fpu *fpu = &t->fpu; 121 122 if (test_thread_flag(TIF_IO_BITMAP)) 123 io_bitmap_exit(tsk); 124 125 free_vm86(t); 126 127 shstk_free(tsk); 128 fpu__drop(fpu); 129 } 130 131 static int set_new_tls(struct task_struct *p, unsigned long tls) 132 { 133 struct user_desc __user *utls = (struct user_desc __user *)tls; 134 135 if (in_ia32_syscall()) 136 return do_set_thread_area(p, -1, utls, 0); 137 else 138 return do_set_thread_area_64(p, ARCH_SET_FS, tls); 139 } 140 141 __visible void ret_from_fork(struct task_struct *prev, struct pt_regs *regs, 142 int (*fn)(void *), void *fn_arg) 143 { 144 schedule_tail(prev); 145 146 /* Is this a kernel thread? */ 147 if (unlikely(fn)) { 148 fn(fn_arg); 149 /* 150 * A kernel thread is allowed to return here after successfully 151 * calling kernel_execve(). Exit to userspace to complete the 152 * execve() syscall. 153 */ 154 regs->ax = 0; 155 } 156 157 syscall_exit_to_user_mode(regs); 158 } 159 160 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) 161 { 162 unsigned long clone_flags = args->flags; 163 unsigned long sp = args->stack; 164 unsigned long tls = args->tls; 165 struct inactive_task_frame *frame; 166 struct fork_frame *fork_frame; 167 struct pt_regs *childregs; 168 unsigned long new_ssp; 169 int ret = 0; 170 171 childregs = task_pt_regs(p); 172 fork_frame = container_of(childregs, struct fork_frame, regs); 173 frame = &fork_frame->frame; 174 175 frame->bp = encode_frame_pointer(childregs); 176 frame->ret_addr = (unsigned long) ret_from_fork_asm; 177 p->thread.sp = (unsigned long) fork_frame; 178 p->thread.io_bitmap = NULL; 179 p->thread.iopl_warn = 0; 180 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 181 182 #ifdef CONFIG_X86_64 183 current_save_fsgs(); 184 p->thread.fsindex = current->thread.fsindex; 185 p->thread.fsbase = current->thread.fsbase; 186 p->thread.gsindex = current->thread.gsindex; 187 p->thread.gsbase = current->thread.gsbase; 188 189 savesegment(es, p->thread.es); 190 savesegment(ds, p->thread.ds); 191 192 if (p->mm && (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM) 193 set_bit(MM_CONTEXT_LOCK_LAM, &p->mm->context.flags); 194 #else 195 p->thread.sp0 = (unsigned long) (childregs + 1); 196 savesegment(gs, p->thread.gs); 197 /* 198 * Clear all status flags including IF and set fixed bit. 64bit 199 * does not have this initialization as the frame does not contain 200 * flags. The flags consistency (especially vs. AC) is there 201 * ensured via objtool, which lacks 32bit support. 202 */ 203 frame->flags = X86_EFLAGS_FIXED; 204 #endif 205 206 /* 207 * Allocate a new shadow stack for thread if needed. If shadow stack, 208 * is disabled, new_ssp will remain 0, and fpu_clone() will know not to 209 * update it. 210 */ 211 new_ssp = shstk_alloc_thread_stack(p, clone_flags, args->stack_size); 212 if (IS_ERR_VALUE(new_ssp)) 213 return PTR_ERR((void *)new_ssp); 214 215 fpu_clone(p, clone_flags, args->fn, new_ssp); 216 217 /* Kernel thread ? */ 218 if (unlikely(p->flags & PF_KTHREAD)) { 219 p->thread.pkru = pkru_get_init_value(); 220 memset(childregs, 0, sizeof(struct pt_regs)); 221 kthread_frame_init(frame, args->fn, args->fn_arg); 222 return 0; 223 } 224 225 /* 226 * Clone current's PKRU value from hardware. tsk->thread.pkru 227 * is only valid when scheduled out. 228 */ 229 p->thread.pkru = read_pkru(); 230 231 frame->bx = 0; 232 *childregs = *current_pt_regs(); 233 childregs->ax = 0; 234 if (sp) 235 childregs->sp = sp; 236 237 if (unlikely(args->fn)) { 238 /* 239 * A user space thread, but it doesn't return to 240 * ret_after_fork(). 241 * 242 * In order to indicate that to tools like gdb, 243 * we reset the stack and instruction pointers. 244 * 245 * It does the same kernel frame setup to return to a kernel 246 * function that a kernel thread does. 247 */ 248 childregs->sp = 0; 249 childregs->ip = 0; 250 kthread_frame_init(frame, args->fn, args->fn_arg); 251 return 0; 252 } 253 254 /* Set a new TLS for the child thread? */ 255 if (clone_flags & CLONE_SETTLS) 256 ret = set_new_tls(p, tls); 257 258 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) 259 io_bitmap_share(p); 260 261 return ret; 262 } 263 264 static void pkru_flush_thread(void) 265 { 266 /* 267 * If PKRU is enabled the default PKRU value has to be loaded into 268 * the hardware right here (similar to context switch). 269 */ 270 pkru_write_default(); 271 } 272 273 void flush_thread(void) 274 { 275 struct task_struct *tsk = current; 276 277 flush_ptrace_hw_breakpoint(tsk); 278 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 279 280 fpu_flush_thread(); 281 pkru_flush_thread(); 282 } 283 284 void disable_TSC(void) 285 { 286 preempt_disable(); 287 if (!test_and_set_thread_flag(TIF_NOTSC)) 288 /* 289 * Must flip the CPU state synchronously with 290 * TIF_NOTSC in the current running context. 291 */ 292 cr4_set_bits(X86_CR4_TSD); 293 preempt_enable(); 294 } 295 296 static void enable_TSC(void) 297 { 298 preempt_disable(); 299 if (test_and_clear_thread_flag(TIF_NOTSC)) 300 /* 301 * Must flip the CPU state synchronously with 302 * TIF_NOTSC in the current running context. 303 */ 304 cr4_clear_bits(X86_CR4_TSD); 305 preempt_enable(); 306 } 307 308 int get_tsc_mode(unsigned long adr) 309 { 310 unsigned int val; 311 312 if (test_thread_flag(TIF_NOTSC)) 313 val = PR_TSC_SIGSEGV; 314 else 315 val = PR_TSC_ENABLE; 316 317 return put_user(val, (unsigned int __user *)adr); 318 } 319 320 int set_tsc_mode(unsigned int val) 321 { 322 if (val == PR_TSC_SIGSEGV) 323 disable_TSC(); 324 else if (val == PR_TSC_ENABLE) 325 enable_TSC(); 326 else 327 return -EINVAL; 328 329 return 0; 330 } 331 332 DEFINE_PER_CPU(u64, msr_misc_features_shadow); 333 334 static void set_cpuid_faulting(bool on) 335 { 336 u64 msrval; 337 338 msrval = this_cpu_read(msr_misc_features_shadow); 339 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 340 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 341 this_cpu_write(msr_misc_features_shadow, msrval); 342 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); 343 } 344 345 static void disable_cpuid(void) 346 { 347 preempt_disable(); 348 if (!test_and_set_thread_flag(TIF_NOCPUID)) { 349 /* 350 * Must flip the CPU state synchronously with 351 * TIF_NOCPUID in the current running context. 352 */ 353 set_cpuid_faulting(true); 354 } 355 preempt_enable(); 356 } 357 358 static void enable_cpuid(void) 359 { 360 preempt_disable(); 361 if (test_and_clear_thread_flag(TIF_NOCPUID)) { 362 /* 363 * Must flip the CPU state synchronously with 364 * TIF_NOCPUID in the current running context. 365 */ 366 set_cpuid_faulting(false); 367 } 368 preempt_enable(); 369 } 370 371 static int get_cpuid_mode(void) 372 { 373 return !test_thread_flag(TIF_NOCPUID); 374 } 375 376 static int set_cpuid_mode(unsigned long cpuid_enabled) 377 { 378 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) 379 return -ENODEV; 380 381 if (cpuid_enabled) 382 enable_cpuid(); 383 else 384 disable_cpuid(); 385 386 return 0; 387 } 388 389 /* 390 * Called immediately after a successful exec. 391 */ 392 void arch_setup_new_exec(void) 393 { 394 /* If cpuid was previously disabled for this task, re-enable it. */ 395 if (test_thread_flag(TIF_NOCPUID)) 396 enable_cpuid(); 397 398 /* 399 * Don't inherit TIF_SSBD across exec boundary when 400 * PR_SPEC_DISABLE_NOEXEC is used. 401 */ 402 if (test_thread_flag(TIF_SSBD) && 403 task_spec_ssb_noexec(current)) { 404 clear_thread_flag(TIF_SSBD); 405 task_clear_spec_ssb_disable(current); 406 task_clear_spec_ssb_noexec(current); 407 speculation_ctrl_update(read_thread_flags()); 408 } 409 410 mm_reset_untag_mask(current->mm); 411 } 412 413 #ifdef CONFIG_X86_IOPL_IOPERM 414 static inline void switch_to_bitmap(unsigned long tifp) 415 { 416 /* 417 * Invalidate I/O bitmap if the previous task used it. This prevents 418 * any possible leakage of an active I/O bitmap. 419 * 420 * If the next task has an I/O bitmap it will handle it on exit to 421 * user mode. 422 */ 423 if (tifp & _TIF_IO_BITMAP) 424 tss_invalidate_io_bitmap(); 425 } 426 427 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) 428 { 429 /* 430 * Copy at least the byte range of the incoming tasks bitmap which 431 * covers the permitted I/O ports. 432 * 433 * If the previous task which used an I/O bitmap had more bits 434 * permitted, then the copy needs to cover those as well so they 435 * get turned off. 436 */ 437 memcpy(tss->io_bitmap.bitmap, iobm->bitmap, 438 max(tss->io_bitmap.prev_max, iobm->max)); 439 440 /* 441 * Store the new max and the sequence number of this bitmap 442 * and a pointer to the bitmap itself. 443 */ 444 tss->io_bitmap.prev_max = iobm->max; 445 tss->io_bitmap.prev_sequence = iobm->sequence; 446 } 447 448 /** 449 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode 450 */ 451 void native_tss_update_io_bitmap(void) 452 { 453 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 454 struct thread_struct *t = ¤t->thread; 455 u16 *base = &tss->x86_tss.io_bitmap_base; 456 457 if (!test_thread_flag(TIF_IO_BITMAP)) { 458 native_tss_invalidate_io_bitmap(); 459 return; 460 } 461 462 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { 463 *base = IO_BITMAP_OFFSET_VALID_ALL; 464 } else { 465 struct io_bitmap *iobm = t->io_bitmap; 466 467 /* 468 * Only copy bitmap data when the sequence number differs. The 469 * update time is accounted to the incoming task. 470 */ 471 if (tss->io_bitmap.prev_sequence != iobm->sequence) 472 tss_copy_io_bitmap(tss, iobm); 473 474 /* Enable the bitmap */ 475 *base = IO_BITMAP_OFFSET_VALID_MAP; 476 } 477 478 /* 479 * Make sure that the TSS limit is covering the IO bitmap. It might have 480 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 481 * access from user space to trigger a #GP because the bitmap is outside 482 * the TSS limit. 483 */ 484 refresh_tss_limit(); 485 } 486 #else /* CONFIG_X86_IOPL_IOPERM */ 487 static inline void switch_to_bitmap(unsigned long tifp) { } 488 #endif 489 490 #ifdef CONFIG_SMP 491 492 struct ssb_state { 493 struct ssb_state *shared_state; 494 raw_spinlock_t lock; 495 unsigned int disable_state; 496 unsigned long local_state; 497 }; 498 499 #define LSTATE_SSB 0 500 501 static DEFINE_PER_CPU(struct ssb_state, ssb_state); 502 503 void speculative_store_bypass_ht_init(void) 504 { 505 struct ssb_state *st = this_cpu_ptr(&ssb_state); 506 unsigned int this_cpu = smp_processor_id(); 507 unsigned int cpu; 508 509 st->local_state = 0; 510 511 /* 512 * Shared state setup happens once on the first bringup 513 * of the CPU. It's not destroyed on CPU hotunplug. 514 */ 515 if (st->shared_state) 516 return; 517 518 raw_spin_lock_init(&st->lock); 519 520 /* 521 * Go over HT siblings and check whether one of them has set up the 522 * shared state pointer already. 523 */ 524 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { 525 if (cpu == this_cpu) 526 continue; 527 528 if (!per_cpu(ssb_state, cpu).shared_state) 529 continue; 530 531 /* Link it to the state of the sibling: */ 532 st->shared_state = per_cpu(ssb_state, cpu).shared_state; 533 return; 534 } 535 536 /* 537 * First HT sibling to come up on the core. Link shared state of 538 * the first HT sibling to itself. The siblings on the same core 539 * which come up later will see the shared state pointer and link 540 * themselves to the state of this CPU. 541 */ 542 st->shared_state = st; 543 } 544 545 /* 546 * Logic is: First HT sibling enables SSBD for both siblings in the core 547 * and last sibling to disable it, disables it for the whole core. This how 548 * MSR_SPEC_CTRL works in "hardware": 549 * 550 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL 551 */ 552 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 553 { 554 struct ssb_state *st = this_cpu_ptr(&ssb_state); 555 u64 msr = x86_amd_ls_cfg_base; 556 557 if (!static_cpu_has(X86_FEATURE_ZEN)) { 558 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 559 wrmsrl(MSR_AMD64_LS_CFG, msr); 560 return; 561 } 562 563 if (tifn & _TIF_SSBD) { 564 /* 565 * Since this can race with prctl(), block reentry on the 566 * same CPU. 567 */ 568 if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) 569 return; 570 571 msr |= x86_amd_ls_cfg_ssbd_mask; 572 573 raw_spin_lock(&st->shared_state->lock); 574 /* First sibling enables SSBD: */ 575 if (!st->shared_state->disable_state) 576 wrmsrl(MSR_AMD64_LS_CFG, msr); 577 st->shared_state->disable_state++; 578 raw_spin_unlock(&st->shared_state->lock); 579 } else { 580 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) 581 return; 582 583 raw_spin_lock(&st->shared_state->lock); 584 st->shared_state->disable_state--; 585 if (!st->shared_state->disable_state) 586 wrmsrl(MSR_AMD64_LS_CFG, msr); 587 raw_spin_unlock(&st->shared_state->lock); 588 } 589 } 590 #else 591 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 592 { 593 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 594 595 wrmsrl(MSR_AMD64_LS_CFG, msr); 596 } 597 #endif 598 599 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) 600 { 601 /* 602 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 603 * so ssbd_tif_to_spec_ctrl() just works. 604 */ 605 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 606 } 607 608 /* 609 * Update the MSRs managing speculation control, during context switch. 610 * 611 * tifp: Previous task's thread flags 612 * tifn: Next task's thread flags 613 */ 614 static __always_inline void __speculation_ctrl_update(unsigned long tifp, 615 unsigned long tifn) 616 { 617 unsigned long tif_diff = tifp ^ tifn; 618 u64 msr = x86_spec_ctrl_base; 619 bool updmsr = false; 620 621 lockdep_assert_irqs_disabled(); 622 623 /* Handle change of TIF_SSBD depending on the mitigation method. */ 624 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { 625 if (tif_diff & _TIF_SSBD) 626 amd_set_ssb_virt_state(tifn); 627 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { 628 if (tif_diff & _TIF_SSBD) 629 amd_set_core_ssb_state(tifn); 630 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 631 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 632 updmsr |= !!(tif_diff & _TIF_SSBD); 633 msr |= ssbd_tif_to_spec_ctrl(tifn); 634 } 635 636 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ 637 if (IS_ENABLED(CONFIG_SMP) && 638 static_branch_unlikely(&switch_to_cond_stibp)) { 639 updmsr |= !!(tif_diff & _TIF_SPEC_IB); 640 msr |= stibp_tif_to_spec_ctrl(tifn); 641 } 642 643 if (updmsr) 644 update_spec_ctrl_cond(msr); 645 } 646 647 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) 648 { 649 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { 650 if (task_spec_ssb_disable(tsk)) 651 set_tsk_thread_flag(tsk, TIF_SSBD); 652 else 653 clear_tsk_thread_flag(tsk, TIF_SSBD); 654 655 if (task_spec_ib_disable(tsk)) 656 set_tsk_thread_flag(tsk, TIF_SPEC_IB); 657 else 658 clear_tsk_thread_flag(tsk, TIF_SPEC_IB); 659 } 660 /* Return the updated threadinfo flags*/ 661 return read_task_thread_flags(tsk); 662 } 663 664 void speculation_ctrl_update(unsigned long tif) 665 { 666 unsigned long flags; 667 668 /* Forced update. Make sure all relevant TIF flags are different */ 669 local_irq_save(flags); 670 __speculation_ctrl_update(~tif, tif); 671 local_irq_restore(flags); 672 } 673 674 /* Called from seccomp/prctl update */ 675 void speculation_ctrl_update_current(void) 676 { 677 preempt_disable(); 678 speculation_ctrl_update(speculation_ctrl_update_tif(current)); 679 preempt_enable(); 680 } 681 682 static inline void cr4_toggle_bits_irqsoff(unsigned long mask) 683 { 684 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 685 686 newval = cr4 ^ mask; 687 if (newval != cr4) { 688 this_cpu_write(cpu_tlbstate.cr4, newval); 689 __write_cr4(newval); 690 } 691 } 692 693 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) 694 { 695 unsigned long tifp, tifn; 696 697 tifn = read_task_thread_flags(next_p); 698 tifp = read_task_thread_flags(prev_p); 699 700 switch_to_bitmap(tifp); 701 702 propagate_user_return_notify(prev_p, next_p); 703 704 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && 705 arch_has_block_step()) { 706 unsigned long debugctl, msk; 707 708 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 709 debugctl &= ~DEBUGCTLMSR_BTF; 710 msk = tifn & _TIF_BLOCKSTEP; 711 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 712 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 713 } 714 715 if ((tifp ^ tifn) & _TIF_NOTSC) 716 cr4_toggle_bits_irqsoff(X86_CR4_TSD); 717 718 if ((tifp ^ tifn) & _TIF_NOCPUID) 719 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); 720 721 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { 722 __speculation_ctrl_update(tifp, tifn); 723 } else { 724 speculation_ctrl_update_tif(prev_p); 725 tifn = speculation_ctrl_update_tif(next_p); 726 727 /* Enforce MSR update to ensure consistent state */ 728 __speculation_ctrl_update(~tifn, tifn); 729 } 730 } 731 732 /* 733 * Idle related variables and functions 734 */ 735 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; 736 EXPORT_SYMBOL(boot_option_idle_override); 737 738 /* 739 * We use this if we don't have any better idle routine.. 740 */ 741 void __cpuidle default_idle(void) 742 { 743 raw_safe_halt(); 744 raw_local_irq_disable(); 745 } 746 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) 747 EXPORT_SYMBOL(default_idle); 748 #endif 749 750 DEFINE_STATIC_CALL_NULL(x86_idle, default_idle); 751 752 static bool x86_idle_set(void) 753 { 754 return !!static_call_query(x86_idle); 755 } 756 757 #ifndef CONFIG_SMP 758 static inline void __noreturn play_dead(void) 759 { 760 BUG(); 761 } 762 #endif 763 764 void arch_cpu_idle_enter(void) 765 { 766 tsc_verify_tsc_adjust(false); 767 local_touch_nmi(); 768 } 769 770 void __noreturn arch_cpu_idle_dead(void) 771 { 772 play_dead(); 773 } 774 775 /* 776 * Called from the generic idle code. 777 */ 778 void __cpuidle arch_cpu_idle(void) 779 { 780 static_call(x86_idle)(); 781 } 782 EXPORT_SYMBOL_GPL(arch_cpu_idle); 783 784 #ifdef CONFIG_XEN 785 bool xen_set_default_idle(void) 786 { 787 bool ret = x86_idle_set(); 788 789 static_call_update(x86_idle, default_idle); 790 791 return ret; 792 } 793 #endif 794 795 struct cpumask cpus_stop_mask; 796 797 void __noreturn stop_this_cpu(void *dummy) 798 { 799 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 800 unsigned int cpu = smp_processor_id(); 801 802 local_irq_disable(); 803 804 /* 805 * Remove this CPU from the online mask and disable it 806 * unconditionally. This might be redundant in case that the reboot 807 * vector was handled late and stop_other_cpus() sent an NMI. 808 * 809 * According to SDM and APM NMIs can be accepted even after soft 810 * disabling the local APIC. 811 */ 812 set_cpu_online(cpu, false); 813 disable_local_APIC(); 814 mcheck_cpu_clear(c); 815 816 /* 817 * Use wbinvd on processors that support SME. This provides support 818 * for performing a successful kexec when going from SME inactive 819 * to SME active (or vice-versa). The cache must be cleared so that 820 * if there are entries with the same physical address, both with and 821 * without the encryption bit, they don't race each other when flushed 822 * and potentially end up with the wrong entry being committed to 823 * memory. 824 * 825 * Test the CPUID bit directly because the machine might've cleared 826 * X86_FEATURE_SME due to cmdline options. 827 */ 828 if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0))) 829 wbinvd(); 830 831 /* 832 * This brings a cache line back and dirties it, but 833 * native_stop_other_cpus() will overwrite cpus_stop_mask after it 834 * observed that all CPUs reported stop. This write will invalidate 835 * the related cache line on this CPU. 836 */ 837 cpumask_clear_cpu(cpu, &cpus_stop_mask); 838 839 #ifdef CONFIG_SMP 840 if (smp_ops.stop_this_cpu) { 841 smp_ops.stop_this_cpu(); 842 BUG(); 843 } 844 #endif 845 846 for (;;) { 847 /* 848 * Use native_halt() so that memory contents don't change 849 * (stack usage and variables) after possibly issuing the 850 * wbinvd() above. 851 */ 852 native_halt(); 853 } 854 } 855 856 /* 857 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf 858 * exists and whenever MONITOR/MWAIT extensions are present there is at 859 * least one C1 substate. 860 * 861 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait 862 * is passed to kernel commandline parameter. 863 */ 864 static __init bool prefer_mwait_c1_over_halt(void) 865 { 866 const struct cpuinfo_x86 *c = &boot_cpu_data; 867 u32 eax, ebx, ecx, edx; 868 869 /* If override is enforced on the command line, fall back to HALT. */ 870 if (boot_option_idle_override != IDLE_NO_OVERRIDE) 871 return false; 872 873 /* MWAIT is not supported on this platform. Fallback to HALT */ 874 if (!cpu_has(c, X86_FEATURE_MWAIT)) 875 return false; 876 877 /* Monitor has a bug or APIC stops in C1E. Fallback to HALT */ 878 if (boot_cpu_has_bug(X86_BUG_MONITOR) || boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) 879 return false; 880 881 cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); 882 883 /* 884 * If MWAIT extensions are not available, it is safe to use MWAIT 885 * with EAX=0, ECX=0. 886 */ 887 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) 888 return true; 889 890 /* 891 * If MWAIT extensions are available, there should be at least one 892 * MWAIT C1 substate present. 893 */ 894 return !!(edx & MWAIT_C1_SUBSTATE_MASK); 895 } 896 897 /* 898 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT 899 * with interrupts enabled and no flags, which is backwards compatible with the 900 * original MWAIT implementation. 901 */ 902 static __cpuidle void mwait_idle(void) 903 { 904 if (!current_set_polling_and_test()) { 905 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { 906 mb(); /* quirk */ 907 clflush((void *)¤t_thread_info()->flags); 908 mb(); /* quirk */ 909 } 910 911 __monitor((void *)¤t_thread_info()->flags, 0, 0); 912 if (!need_resched()) { 913 __sti_mwait(0, 0); 914 raw_local_irq_disable(); 915 } 916 } 917 __current_clr_polling(); 918 } 919 920 void __init select_idle_routine(void) 921 { 922 if (boot_option_idle_override == IDLE_POLL) { 923 if (IS_ENABLED(CONFIG_SMP) && __max_threads_per_core > 1) 924 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); 925 return; 926 } 927 928 /* Required to guard against xen_set_default_idle() */ 929 if (x86_idle_set()) 930 return; 931 932 if (prefer_mwait_c1_over_halt()) { 933 pr_info("using mwait in idle threads\n"); 934 static_call_update(x86_idle, mwait_idle); 935 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { 936 pr_info("using TDX aware idle routine\n"); 937 static_call_update(x86_idle, tdx_safe_halt); 938 } else { 939 static_call_update(x86_idle, default_idle); 940 } 941 } 942 943 void amd_e400_c1e_apic_setup(void) 944 { 945 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 946 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); 947 local_irq_disable(); 948 tick_broadcast_force(); 949 local_irq_enable(); 950 } 951 } 952 953 void __init arch_post_acpi_subsys_init(void) 954 { 955 u32 lo, hi; 956 957 if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) 958 return; 959 960 /* 961 * AMD E400 detection needs to happen after ACPI has been enabled. If 962 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in 963 * MSR_K8_INT_PENDING_MSG. 964 */ 965 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 966 if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) 967 return; 968 969 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); 970 971 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 972 mark_tsc_unstable("TSC halt in AMD C1E"); 973 974 if (IS_ENABLED(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE)) 975 static_branch_enable(&arch_needs_tick_broadcast); 976 pr_info("System has AMD C1E erratum E400. Workaround enabled.\n"); 977 } 978 979 static int __init idle_setup(char *str) 980 { 981 if (!str) 982 return -EINVAL; 983 984 if (!strcmp(str, "poll")) { 985 pr_info("using polling idle threads\n"); 986 boot_option_idle_override = IDLE_POLL; 987 cpu_idle_poll_ctrl(true); 988 } else if (!strcmp(str, "halt")) { 989 /* 'idle=halt' HALT for idle. C-states are disabled. */ 990 boot_option_idle_override = IDLE_HALT; 991 } else if (!strcmp(str, "nomwait")) { 992 /* 'idle=nomwait' disables MWAIT for idle */ 993 boot_option_idle_override = IDLE_NOMWAIT; 994 } else { 995 return -EINVAL; 996 } 997 998 return 0; 999 } 1000 early_param("idle", idle_setup); 1001 1002 unsigned long arch_align_stack(unsigned long sp) 1003 { 1004 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1005 sp -= get_random_u32_below(8192); 1006 return sp & ~0xf; 1007 } 1008 1009 unsigned long arch_randomize_brk(struct mm_struct *mm) 1010 { 1011 if (mmap_is_ia32()) 1012 return randomize_page(mm->brk, SZ_32M); 1013 1014 return randomize_page(mm->brk, SZ_1G); 1015 } 1016 1017 /* 1018 * Called from fs/proc with a reference on @p to find the function 1019 * which called into schedule(). This needs to be done carefully 1020 * because the task might wake up and we might look at a stack 1021 * changing under us. 1022 */ 1023 unsigned long __get_wchan(struct task_struct *p) 1024 { 1025 struct unwind_state state; 1026 unsigned long addr = 0; 1027 1028 if (!try_get_task_stack(p)) 1029 return 0; 1030 1031 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); 1032 unwind_next_frame(&state)) { 1033 addr = unwind_get_return_address(&state); 1034 if (!addr) 1035 break; 1036 if (in_sched_functions(addr)) 1037 continue; 1038 break; 1039 } 1040 1041 put_task_stack(p); 1042 1043 return addr; 1044 } 1045 1046 long do_arch_prctl_common(int option, unsigned long arg2) 1047 { 1048 switch (option) { 1049 case ARCH_GET_CPUID: 1050 return get_cpuid_mode(); 1051 case ARCH_SET_CPUID: 1052 return set_cpuid_mode(arg2); 1053 case ARCH_GET_XCOMP_SUPP: 1054 case ARCH_GET_XCOMP_PERM: 1055 case ARCH_REQ_XCOMP_PERM: 1056 case ARCH_GET_XCOMP_GUEST_PERM: 1057 case ARCH_REQ_XCOMP_GUEST_PERM: 1058 return fpu_xstate_prctl(option, arg2); 1059 } 1060 1061 return -EINVAL; 1062 } 1063