1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/errno.h> 5 #include <linux/kernel.h> 6 #include <linux/mm.h> 7 #include <linux/smp.h> 8 #include <linux/prctl.h> 9 #include <linux/slab.h> 10 #include <linux/sched.h> 11 #include <linux/sched/idle.h> 12 #include <linux/sched/debug.h> 13 #include <linux/sched/task.h> 14 #include <linux/sched/task_stack.h> 15 #include <linux/init.h> 16 #include <linux/export.h> 17 #include <linux/pm.h> 18 #include <linux/tick.h> 19 #include <linux/random.h> 20 #include <linux/user-return-notifier.h> 21 #include <linux/dmi.h> 22 #include <linux/utsname.h> 23 #include <linux/stackprotector.h> 24 #include <linux/cpuidle.h> 25 #include <linux/acpi.h> 26 #include <linux/elf-randomize.h> 27 #include <trace/events/power.h> 28 #include <linux/hw_breakpoint.h> 29 #include <asm/cpu.h> 30 #include <asm/apic.h> 31 #include <linux/uaccess.h> 32 #include <asm/mwait.h> 33 #include <asm/fpu/internal.h> 34 #include <asm/debugreg.h> 35 #include <asm/nmi.h> 36 #include <asm/tlbflush.h> 37 #include <asm/mce.h> 38 #include <asm/vm86.h> 39 #include <asm/switch_to.h> 40 #include <asm/desc.h> 41 #include <asm/prctl.h> 42 #include <asm/spec-ctrl.h> 43 #include <asm/io_bitmap.h> 44 #include <asm/proto.h> 45 46 #include "process.h" 47 48 /* 49 * per-CPU TSS segments. Threads are completely 'soft' on Linux, 50 * no more per-task TSS's. The TSS size is kept cacheline-aligned 51 * so they are allowed to end up in the .data..cacheline_aligned 52 * section. Since TSS's are completely CPU-local, we want them 53 * on exact cacheline boundaries, to eliminate cacheline ping-pong. 54 */ 55 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { 56 .x86_tss = { 57 /* 58 * .sp0 is only used when entering ring 0 from a lower 59 * privilege level. Since the init task never runs anything 60 * but ring 0 code, there is no need for a valid value here. 61 * Poison it. 62 */ 63 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, 64 65 /* 66 * .sp1 is cpu_current_top_of_stack. The init task never 67 * runs user code, but cpu_current_top_of_stack should still 68 * be well defined before the first context switch. 69 */ 70 .sp1 = TOP_OF_INIT_STACK, 71 72 #ifdef CONFIG_X86_32 73 .ss0 = __KERNEL_DS, 74 .ss1 = __KERNEL_CS, 75 #endif 76 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, 77 }, 78 }; 79 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); 80 81 DEFINE_PER_CPU(bool, __tss_limit_invalid); 82 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); 83 84 /* 85 * this gets called so that we can store lazy state into memory and copy the 86 * current task into the new thread. 87 */ 88 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 89 { 90 memcpy(dst, src, arch_task_struct_size); 91 #ifdef CONFIG_VM86 92 dst->thread.vm86 = NULL; 93 #endif 94 95 return fpu__copy(dst, src); 96 } 97 98 /* 99 * Free thread data structures etc.. 100 */ 101 void exit_thread(struct task_struct *tsk) 102 { 103 struct thread_struct *t = &tsk->thread; 104 struct fpu *fpu = &t->fpu; 105 106 if (test_thread_flag(TIF_IO_BITMAP)) 107 io_bitmap_exit(tsk); 108 109 free_vm86(t); 110 111 fpu__drop(fpu); 112 } 113 114 static int set_new_tls(struct task_struct *p, unsigned long tls) 115 { 116 struct user_desc __user *utls = (struct user_desc __user *)tls; 117 118 if (in_ia32_syscall()) 119 return do_set_thread_area(p, -1, utls, 0); 120 else 121 return do_set_thread_area_64(p, ARCH_SET_FS, tls); 122 } 123 124 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, 125 struct task_struct *p, unsigned long tls) 126 { 127 struct inactive_task_frame *frame; 128 struct fork_frame *fork_frame; 129 struct pt_regs *childregs; 130 int ret = 0; 131 132 childregs = task_pt_regs(p); 133 fork_frame = container_of(childregs, struct fork_frame, regs); 134 frame = &fork_frame->frame; 135 136 frame->bp = 0; 137 frame->ret_addr = (unsigned long) ret_from_fork; 138 p->thread.sp = (unsigned long) fork_frame; 139 p->thread.io_bitmap = NULL; 140 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 141 142 #ifdef CONFIG_X86_64 143 current_save_fsgs(); 144 p->thread.fsindex = current->thread.fsindex; 145 p->thread.fsbase = current->thread.fsbase; 146 p->thread.gsindex = current->thread.gsindex; 147 p->thread.gsbase = current->thread.gsbase; 148 149 savesegment(es, p->thread.es); 150 savesegment(ds, p->thread.ds); 151 #else 152 p->thread.sp0 = (unsigned long) (childregs + 1); 153 /* 154 * Clear all status flags including IF and set fixed bit. 64bit 155 * does not have this initialization as the frame does not contain 156 * flags. The flags consistency (especially vs. AC) is there 157 * ensured via objtool, which lacks 32bit support. 158 */ 159 frame->flags = X86_EFLAGS_FIXED; 160 #endif 161 162 /* Kernel thread ? */ 163 if (unlikely(p->flags & PF_KTHREAD)) { 164 memset(childregs, 0, sizeof(struct pt_regs)); 165 kthread_frame_init(frame, sp, arg); 166 return 0; 167 } 168 169 frame->bx = 0; 170 *childregs = *current_pt_regs(); 171 childregs->ax = 0; 172 if (sp) 173 childregs->sp = sp; 174 175 #ifdef CONFIG_X86_32 176 task_user_gs(p) = get_user_gs(current_pt_regs()); 177 #endif 178 179 /* Set a new TLS for the child thread? */ 180 if (clone_flags & CLONE_SETTLS) 181 ret = set_new_tls(p, tls); 182 183 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) 184 io_bitmap_share(p); 185 186 return ret; 187 } 188 189 void flush_thread(void) 190 { 191 struct task_struct *tsk = current; 192 193 flush_ptrace_hw_breakpoint(tsk); 194 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 195 196 fpu__clear_all(&tsk->thread.fpu); 197 } 198 199 void disable_TSC(void) 200 { 201 preempt_disable(); 202 if (!test_and_set_thread_flag(TIF_NOTSC)) 203 /* 204 * Must flip the CPU state synchronously with 205 * TIF_NOTSC in the current running context. 206 */ 207 cr4_set_bits(X86_CR4_TSD); 208 preempt_enable(); 209 } 210 211 static void enable_TSC(void) 212 { 213 preempt_disable(); 214 if (test_and_clear_thread_flag(TIF_NOTSC)) 215 /* 216 * Must flip the CPU state synchronously with 217 * TIF_NOTSC in the current running context. 218 */ 219 cr4_clear_bits(X86_CR4_TSD); 220 preempt_enable(); 221 } 222 223 int get_tsc_mode(unsigned long adr) 224 { 225 unsigned int val; 226 227 if (test_thread_flag(TIF_NOTSC)) 228 val = PR_TSC_SIGSEGV; 229 else 230 val = PR_TSC_ENABLE; 231 232 return put_user(val, (unsigned int __user *)adr); 233 } 234 235 int set_tsc_mode(unsigned int val) 236 { 237 if (val == PR_TSC_SIGSEGV) 238 disable_TSC(); 239 else if (val == PR_TSC_ENABLE) 240 enable_TSC(); 241 else 242 return -EINVAL; 243 244 return 0; 245 } 246 247 DEFINE_PER_CPU(u64, msr_misc_features_shadow); 248 249 static void set_cpuid_faulting(bool on) 250 { 251 u64 msrval; 252 253 msrval = this_cpu_read(msr_misc_features_shadow); 254 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 255 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 256 this_cpu_write(msr_misc_features_shadow, msrval); 257 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); 258 } 259 260 static void disable_cpuid(void) 261 { 262 preempt_disable(); 263 if (!test_and_set_thread_flag(TIF_NOCPUID)) { 264 /* 265 * Must flip the CPU state synchronously with 266 * TIF_NOCPUID in the current running context. 267 */ 268 set_cpuid_faulting(true); 269 } 270 preempt_enable(); 271 } 272 273 static void enable_cpuid(void) 274 { 275 preempt_disable(); 276 if (test_and_clear_thread_flag(TIF_NOCPUID)) { 277 /* 278 * Must flip the CPU state synchronously with 279 * TIF_NOCPUID in the current running context. 280 */ 281 set_cpuid_faulting(false); 282 } 283 preempt_enable(); 284 } 285 286 static int get_cpuid_mode(void) 287 { 288 return !test_thread_flag(TIF_NOCPUID); 289 } 290 291 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) 292 { 293 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) 294 return -ENODEV; 295 296 if (cpuid_enabled) 297 enable_cpuid(); 298 else 299 disable_cpuid(); 300 301 return 0; 302 } 303 304 /* 305 * Called immediately after a successful exec. 306 */ 307 void arch_setup_new_exec(void) 308 { 309 /* If cpuid was previously disabled for this task, re-enable it. */ 310 if (test_thread_flag(TIF_NOCPUID)) 311 enable_cpuid(); 312 313 /* 314 * Don't inherit TIF_SSBD across exec boundary when 315 * PR_SPEC_DISABLE_NOEXEC is used. 316 */ 317 if (test_thread_flag(TIF_SSBD) && 318 task_spec_ssb_noexec(current)) { 319 clear_thread_flag(TIF_SSBD); 320 task_clear_spec_ssb_disable(current); 321 task_clear_spec_ssb_noexec(current); 322 speculation_ctrl_update(task_thread_info(current)->flags); 323 } 324 } 325 326 #ifdef CONFIG_X86_IOPL_IOPERM 327 static inline void switch_to_bitmap(unsigned long tifp) 328 { 329 /* 330 * Invalidate I/O bitmap if the previous task used it. This prevents 331 * any possible leakage of an active I/O bitmap. 332 * 333 * If the next task has an I/O bitmap it will handle it on exit to 334 * user mode. 335 */ 336 if (tifp & _TIF_IO_BITMAP) 337 tss_invalidate_io_bitmap(); 338 } 339 340 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) 341 { 342 /* 343 * Copy at least the byte range of the incoming tasks bitmap which 344 * covers the permitted I/O ports. 345 * 346 * If the previous task which used an I/O bitmap had more bits 347 * permitted, then the copy needs to cover those as well so they 348 * get turned off. 349 */ 350 memcpy(tss->io_bitmap.bitmap, iobm->bitmap, 351 max(tss->io_bitmap.prev_max, iobm->max)); 352 353 /* 354 * Store the new max and the sequence number of this bitmap 355 * and a pointer to the bitmap itself. 356 */ 357 tss->io_bitmap.prev_max = iobm->max; 358 tss->io_bitmap.prev_sequence = iobm->sequence; 359 } 360 361 /** 362 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode 363 */ 364 void native_tss_update_io_bitmap(void) 365 { 366 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 367 struct thread_struct *t = ¤t->thread; 368 u16 *base = &tss->x86_tss.io_bitmap_base; 369 370 if (!test_thread_flag(TIF_IO_BITMAP)) { 371 native_tss_invalidate_io_bitmap(); 372 return; 373 } 374 375 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { 376 *base = IO_BITMAP_OFFSET_VALID_ALL; 377 } else { 378 struct io_bitmap *iobm = t->io_bitmap; 379 380 /* 381 * Only copy bitmap data when the sequence number differs. The 382 * update time is accounted to the incoming task. 383 */ 384 if (tss->io_bitmap.prev_sequence != iobm->sequence) 385 tss_copy_io_bitmap(tss, iobm); 386 387 /* Enable the bitmap */ 388 *base = IO_BITMAP_OFFSET_VALID_MAP; 389 } 390 391 /* 392 * Make sure that the TSS limit is covering the IO bitmap. It might have 393 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 394 * access from user space to trigger a #GP because tbe bitmap is outside 395 * the TSS limit. 396 */ 397 refresh_tss_limit(); 398 } 399 #else /* CONFIG_X86_IOPL_IOPERM */ 400 static inline void switch_to_bitmap(unsigned long tifp) { } 401 #endif 402 403 #ifdef CONFIG_SMP 404 405 struct ssb_state { 406 struct ssb_state *shared_state; 407 raw_spinlock_t lock; 408 unsigned int disable_state; 409 unsigned long local_state; 410 }; 411 412 #define LSTATE_SSB 0 413 414 static DEFINE_PER_CPU(struct ssb_state, ssb_state); 415 416 void speculative_store_bypass_ht_init(void) 417 { 418 struct ssb_state *st = this_cpu_ptr(&ssb_state); 419 unsigned int this_cpu = smp_processor_id(); 420 unsigned int cpu; 421 422 st->local_state = 0; 423 424 /* 425 * Shared state setup happens once on the first bringup 426 * of the CPU. It's not destroyed on CPU hotunplug. 427 */ 428 if (st->shared_state) 429 return; 430 431 raw_spin_lock_init(&st->lock); 432 433 /* 434 * Go over HT siblings and check whether one of them has set up the 435 * shared state pointer already. 436 */ 437 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { 438 if (cpu == this_cpu) 439 continue; 440 441 if (!per_cpu(ssb_state, cpu).shared_state) 442 continue; 443 444 /* Link it to the state of the sibling: */ 445 st->shared_state = per_cpu(ssb_state, cpu).shared_state; 446 return; 447 } 448 449 /* 450 * First HT sibling to come up on the core. Link shared state of 451 * the first HT sibling to itself. The siblings on the same core 452 * which come up later will see the shared state pointer and link 453 * themself to the state of this CPU. 454 */ 455 st->shared_state = st; 456 } 457 458 /* 459 * Logic is: First HT sibling enables SSBD for both siblings in the core 460 * and last sibling to disable it, disables it for the whole core. This how 461 * MSR_SPEC_CTRL works in "hardware": 462 * 463 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL 464 */ 465 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 466 { 467 struct ssb_state *st = this_cpu_ptr(&ssb_state); 468 u64 msr = x86_amd_ls_cfg_base; 469 470 if (!static_cpu_has(X86_FEATURE_ZEN)) { 471 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 472 wrmsrl(MSR_AMD64_LS_CFG, msr); 473 return; 474 } 475 476 if (tifn & _TIF_SSBD) { 477 /* 478 * Since this can race with prctl(), block reentry on the 479 * same CPU. 480 */ 481 if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) 482 return; 483 484 msr |= x86_amd_ls_cfg_ssbd_mask; 485 486 raw_spin_lock(&st->shared_state->lock); 487 /* First sibling enables SSBD: */ 488 if (!st->shared_state->disable_state) 489 wrmsrl(MSR_AMD64_LS_CFG, msr); 490 st->shared_state->disable_state++; 491 raw_spin_unlock(&st->shared_state->lock); 492 } else { 493 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) 494 return; 495 496 raw_spin_lock(&st->shared_state->lock); 497 st->shared_state->disable_state--; 498 if (!st->shared_state->disable_state) 499 wrmsrl(MSR_AMD64_LS_CFG, msr); 500 raw_spin_unlock(&st->shared_state->lock); 501 } 502 } 503 #else 504 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 505 { 506 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 507 508 wrmsrl(MSR_AMD64_LS_CFG, msr); 509 } 510 #endif 511 512 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) 513 { 514 /* 515 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 516 * so ssbd_tif_to_spec_ctrl() just works. 517 */ 518 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 519 } 520 521 /* 522 * Update the MSRs managing speculation control, during context switch. 523 * 524 * tifp: Previous task's thread flags 525 * tifn: Next task's thread flags 526 */ 527 static __always_inline void __speculation_ctrl_update(unsigned long tifp, 528 unsigned long tifn) 529 { 530 unsigned long tif_diff = tifp ^ tifn; 531 u64 msr = x86_spec_ctrl_base; 532 bool updmsr = false; 533 534 lockdep_assert_irqs_disabled(); 535 536 /* Handle change of TIF_SSBD depending on the mitigation method. */ 537 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { 538 if (tif_diff & _TIF_SSBD) 539 amd_set_ssb_virt_state(tifn); 540 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { 541 if (tif_diff & _TIF_SSBD) 542 amd_set_core_ssb_state(tifn); 543 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 544 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 545 updmsr |= !!(tif_diff & _TIF_SSBD); 546 msr |= ssbd_tif_to_spec_ctrl(tifn); 547 } 548 549 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ 550 if (IS_ENABLED(CONFIG_SMP) && 551 static_branch_unlikely(&switch_to_cond_stibp)) { 552 updmsr |= !!(tif_diff & _TIF_SPEC_IB); 553 msr |= stibp_tif_to_spec_ctrl(tifn); 554 } 555 556 if (updmsr) 557 wrmsrl(MSR_IA32_SPEC_CTRL, msr); 558 } 559 560 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) 561 { 562 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { 563 if (task_spec_ssb_disable(tsk)) 564 set_tsk_thread_flag(tsk, TIF_SSBD); 565 else 566 clear_tsk_thread_flag(tsk, TIF_SSBD); 567 568 if (task_spec_ib_disable(tsk)) 569 set_tsk_thread_flag(tsk, TIF_SPEC_IB); 570 else 571 clear_tsk_thread_flag(tsk, TIF_SPEC_IB); 572 } 573 /* Return the updated threadinfo flags*/ 574 return task_thread_info(tsk)->flags; 575 } 576 577 void speculation_ctrl_update(unsigned long tif) 578 { 579 unsigned long flags; 580 581 /* Forced update. Make sure all relevant TIF flags are different */ 582 local_irq_save(flags); 583 __speculation_ctrl_update(~tif, tif); 584 local_irq_restore(flags); 585 } 586 587 /* Called from seccomp/prctl update */ 588 void speculation_ctrl_update_current(void) 589 { 590 preempt_disable(); 591 speculation_ctrl_update(speculation_ctrl_update_tif(current)); 592 preempt_enable(); 593 } 594 595 static inline void cr4_toggle_bits_irqsoff(unsigned long mask) 596 { 597 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 598 599 newval = cr4 ^ mask; 600 if (newval != cr4) { 601 this_cpu_write(cpu_tlbstate.cr4, newval); 602 __write_cr4(newval); 603 } 604 } 605 606 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) 607 { 608 unsigned long tifp, tifn; 609 610 tifn = READ_ONCE(task_thread_info(next_p)->flags); 611 tifp = READ_ONCE(task_thread_info(prev_p)->flags); 612 613 switch_to_bitmap(tifp); 614 615 propagate_user_return_notify(prev_p, next_p); 616 617 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && 618 arch_has_block_step()) { 619 unsigned long debugctl, msk; 620 621 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 622 debugctl &= ~DEBUGCTLMSR_BTF; 623 msk = tifn & _TIF_BLOCKSTEP; 624 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 625 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 626 } 627 628 if ((tifp ^ tifn) & _TIF_NOTSC) 629 cr4_toggle_bits_irqsoff(X86_CR4_TSD); 630 631 if ((tifp ^ tifn) & _TIF_NOCPUID) 632 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); 633 634 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { 635 __speculation_ctrl_update(tifp, tifn); 636 } else { 637 speculation_ctrl_update_tif(prev_p); 638 tifn = speculation_ctrl_update_tif(next_p); 639 640 /* Enforce MSR update to ensure consistent state */ 641 __speculation_ctrl_update(~tifn, tifn); 642 } 643 644 if ((tifp ^ tifn) & _TIF_SLD) 645 switch_to_sld(tifn); 646 } 647 648 /* 649 * Idle related variables and functions 650 */ 651 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; 652 EXPORT_SYMBOL(boot_option_idle_override); 653 654 static void (*x86_idle)(void); 655 656 #ifndef CONFIG_SMP 657 static inline void play_dead(void) 658 { 659 BUG(); 660 } 661 #endif 662 663 void arch_cpu_idle_enter(void) 664 { 665 tsc_verify_tsc_adjust(false); 666 local_touch_nmi(); 667 } 668 669 void arch_cpu_idle_dead(void) 670 { 671 play_dead(); 672 } 673 674 /* 675 * Called from the generic idle code. 676 */ 677 void arch_cpu_idle(void) 678 { 679 x86_idle(); 680 } 681 682 /* 683 * We use this if we don't have any better idle routine.. 684 */ 685 void __cpuidle default_idle(void) 686 { 687 safe_halt(); 688 } 689 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) 690 EXPORT_SYMBOL(default_idle); 691 #endif 692 693 #ifdef CONFIG_XEN 694 bool xen_set_default_idle(void) 695 { 696 bool ret = !!x86_idle; 697 698 x86_idle = default_idle; 699 700 return ret; 701 } 702 #endif 703 704 void stop_this_cpu(void *dummy) 705 { 706 local_irq_disable(); 707 /* 708 * Remove this CPU: 709 */ 710 set_cpu_online(smp_processor_id(), false); 711 disable_local_APIC(); 712 mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); 713 714 /* 715 * Use wbinvd on processors that support SME. This provides support 716 * for performing a successful kexec when going from SME inactive 717 * to SME active (or vice-versa). The cache must be cleared so that 718 * if there are entries with the same physical address, both with and 719 * without the encryption bit, they don't race each other when flushed 720 * and potentially end up with the wrong entry being committed to 721 * memory. 722 */ 723 if (boot_cpu_has(X86_FEATURE_SME)) 724 native_wbinvd(); 725 for (;;) { 726 /* 727 * Use native_halt() so that memory contents don't change 728 * (stack usage and variables) after possibly issuing the 729 * native_wbinvd() above. 730 */ 731 native_halt(); 732 } 733 } 734 735 /* 736 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power 737 * states (local apic timer and TSC stop). 738 */ 739 static void amd_e400_idle(void) 740 { 741 /* 742 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E 743 * gets set after static_cpu_has() places have been converted via 744 * alternatives. 745 */ 746 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 747 default_idle(); 748 return; 749 } 750 751 tick_broadcast_enter(); 752 753 default_idle(); 754 755 /* 756 * The switch back from broadcast mode needs to be called with 757 * interrupts disabled. 758 */ 759 local_irq_disable(); 760 tick_broadcast_exit(); 761 local_irq_enable(); 762 } 763 764 /* 765 * Intel Core2 and older machines prefer MWAIT over HALT for C1. 766 * We can't rely on cpuidle installing MWAIT, because it will not load 767 * on systems that support only C1 -- so the boot default must be MWAIT. 768 * 769 * Some AMD machines are the opposite, they depend on using HALT. 770 * 771 * So for default C1, which is used during boot until cpuidle loads, 772 * use MWAIT-C1 on Intel HW that has it, else use HALT. 773 */ 774 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) 775 { 776 if (c->x86_vendor != X86_VENDOR_INTEL) 777 return 0; 778 779 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) 780 return 0; 781 782 return 1; 783 } 784 785 /* 786 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT 787 * with interrupts enabled and no flags, which is backwards compatible with the 788 * original MWAIT implementation. 789 */ 790 static __cpuidle void mwait_idle(void) 791 { 792 if (!current_set_polling_and_test()) { 793 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { 794 mb(); /* quirk */ 795 clflush((void *)¤t_thread_info()->flags); 796 mb(); /* quirk */ 797 } 798 799 __monitor((void *)¤t_thread_info()->flags, 0, 0); 800 if (!need_resched()) 801 __sti_mwait(0, 0); 802 else 803 local_irq_enable(); 804 } else { 805 local_irq_enable(); 806 } 807 __current_clr_polling(); 808 } 809 810 void select_idle_routine(const struct cpuinfo_x86 *c) 811 { 812 #ifdef CONFIG_SMP 813 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) 814 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); 815 #endif 816 if (x86_idle || boot_option_idle_override == IDLE_POLL) 817 return; 818 819 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { 820 pr_info("using AMD E400 aware idle routine\n"); 821 x86_idle = amd_e400_idle; 822 } else if (prefer_mwait_c1_over_halt(c)) { 823 pr_info("using mwait in idle threads\n"); 824 x86_idle = mwait_idle; 825 } else 826 x86_idle = default_idle; 827 } 828 829 void amd_e400_c1e_apic_setup(void) 830 { 831 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 832 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); 833 local_irq_disable(); 834 tick_broadcast_force(); 835 local_irq_enable(); 836 } 837 } 838 839 void __init arch_post_acpi_subsys_init(void) 840 { 841 u32 lo, hi; 842 843 if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) 844 return; 845 846 /* 847 * AMD E400 detection needs to happen after ACPI has been enabled. If 848 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in 849 * MSR_K8_INT_PENDING_MSG. 850 */ 851 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 852 if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) 853 return; 854 855 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); 856 857 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 858 mark_tsc_unstable("TSC halt in AMD C1E"); 859 pr_info("System has AMD C1E enabled\n"); 860 } 861 862 static int __init idle_setup(char *str) 863 { 864 if (!str) 865 return -EINVAL; 866 867 if (!strcmp(str, "poll")) { 868 pr_info("using polling idle threads\n"); 869 boot_option_idle_override = IDLE_POLL; 870 cpu_idle_poll_ctrl(true); 871 } else if (!strcmp(str, "halt")) { 872 /* 873 * When the boot option of idle=halt is added, halt is 874 * forced to be used for CPU idle. In such case CPU C2/C3 875 * won't be used again. 876 * To continue to load the CPU idle driver, don't touch 877 * the boot_option_idle_override. 878 */ 879 x86_idle = default_idle; 880 boot_option_idle_override = IDLE_HALT; 881 } else if (!strcmp(str, "nomwait")) { 882 /* 883 * If the boot option of "idle=nomwait" is added, 884 * it means that mwait will be disabled for CPU C2/C3 885 * states. In such case it won't touch the variable 886 * of boot_option_idle_override. 887 */ 888 boot_option_idle_override = IDLE_NOMWAIT; 889 } else 890 return -1; 891 892 return 0; 893 } 894 early_param("idle", idle_setup); 895 896 unsigned long arch_align_stack(unsigned long sp) 897 { 898 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 899 sp -= get_random_int() % 8192; 900 return sp & ~0xf; 901 } 902 903 unsigned long arch_randomize_brk(struct mm_struct *mm) 904 { 905 return randomize_page(mm->brk, 0x02000000); 906 } 907 908 /* 909 * Called from fs/proc with a reference on @p to find the function 910 * which called into schedule(). This needs to be done carefully 911 * because the task might wake up and we might look at a stack 912 * changing under us. 913 */ 914 unsigned long get_wchan(struct task_struct *p) 915 { 916 unsigned long start, bottom, top, sp, fp, ip, ret = 0; 917 int count = 0; 918 919 if (p == current || p->state == TASK_RUNNING) 920 return 0; 921 922 if (!try_get_task_stack(p)) 923 return 0; 924 925 start = (unsigned long)task_stack_page(p); 926 if (!start) 927 goto out; 928 929 /* 930 * Layout of the stack page: 931 * 932 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) 933 * PADDING 934 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING 935 * stack 936 * ----------- bottom = start 937 * 938 * The tasks stack pointer points at the location where the 939 * framepointer is stored. The data on the stack is: 940 * ... IP FP ... IP FP 941 * 942 * We need to read FP and IP, so we need to adjust the upper 943 * bound by another unsigned long. 944 */ 945 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; 946 top -= 2 * sizeof(unsigned long); 947 bottom = start; 948 949 sp = READ_ONCE(p->thread.sp); 950 if (sp < bottom || sp > top) 951 goto out; 952 953 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); 954 do { 955 if (fp < bottom || fp > top) 956 goto out; 957 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); 958 if (!in_sched_functions(ip)) { 959 ret = ip; 960 goto out; 961 } 962 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); 963 } while (count++ < 16 && p->state != TASK_RUNNING); 964 965 out: 966 put_task_stack(p); 967 return ret; 968 } 969 970 long do_arch_prctl_common(struct task_struct *task, int option, 971 unsigned long cpuid_enabled) 972 { 973 switch (option) { 974 case ARCH_GET_CPUID: 975 return get_cpuid_mode(); 976 case ARCH_SET_CPUID: 977 return set_cpuid_mode(task, cpuid_enabled); 978 } 979 980 return -EINVAL; 981 } 982