1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/errno.h> 5 #include <linux/kernel.h> 6 #include <linux/mm.h> 7 #include <linux/smp.h> 8 #include <linux/cpu.h> 9 #include <linux/prctl.h> 10 #include <linux/slab.h> 11 #include <linux/sched.h> 12 #include <linux/sched/idle.h> 13 #include <linux/sched/debug.h> 14 #include <linux/sched/task.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 #include <linux/pm.h> 19 #include <linux/tick.h> 20 #include <linux/random.h> 21 #include <linux/user-return-notifier.h> 22 #include <linux/dmi.h> 23 #include <linux/utsname.h> 24 #include <linux/stackprotector.h> 25 #include <linux/cpuidle.h> 26 #include <linux/acpi.h> 27 #include <linux/elf-randomize.h> 28 #include <linux/static_call.h> 29 #include <trace/events/power.h> 30 #include <linux/hw_breakpoint.h> 31 #include <linux/entry-common.h> 32 #include <asm/cpu.h> 33 #include <asm/cpuid/api.h> 34 #include <asm/apic.h> 35 #include <linux/uaccess.h> 36 #include <asm/mwait.h> 37 #include <asm/fpu/api.h> 38 #include <asm/fpu/sched.h> 39 #include <asm/fpu/xstate.h> 40 #include <asm/debugreg.h> 41 #include <asm/nmi.h> 42 #include <asm/tlbflush.h> 43 #include <asm/mce.h> 44 #include <asm/vm86.h> 45 #include <asm/switch_to.h> 46 #include <asm/desc.h> 47 #include <asm/prctl.h> 48 #include <asm/spec-ctrl.h> 49 #include <asm/io_bitmap.h> 50 #include <asm/proto.h> 51 #include <asm/frame.h> 52 #include <asm/unwind.h> 53 #include <asm/tdx.h> 54 #include <asm/mmu_context.h> 55 #include <asm/msr.h> 56 #include <asm/shstk.h> 57 58 #include "process.h" 59 60 /* 61 * per-CPU TSS segments. Threads are completely 'soft' on Linux, 62 * no more per-task TSS's. The TSS size is kept cacheline-aligned 63 * so they are allowed to end up in the .data..cacheline_aligned 64 * section. Since TSS's are completely CPU-local, we want them 65 * on exact cacheline boundaries, to eliminate cacheline ping-pong. 66 */ 67 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { 68 .x86_tss = { 69 /* 70 * .sp0 is only used when entering ring 0 from a lower 71 * privilege level. Since the init task never runs anything 72 * but ring 0 code, there is no need for a valid value here. 73 * Poison it. 74 */ 75 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, 76 77 #ifdef CONFIG_X86_32 78 .sp1 = TOP_OF_INIT_STACK, 79 80 .ss0 = __KERNEL_DS, 81 .ss1 = __KERNEL_CS, 82 #endif 83 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, 84 }, 85 }; 86 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); 87 88 DEFINE_PER_CPU(bool, __tss_limit_invalid); 89 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); 90 91 /* 92 * this gets called so that we can store lazy state into memory and copy the 93 * current task into the new thread. 94 */ 95 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 96 { 97 /* fpu_clone() will initialize the "dst_fpu" memory */ 98 memcpy_and_pad(dst, arch_task_struct_size, src, sizeof(*dst), 0); 99 100 #ifdef CONFIG_VM86 101 dst->thread.vm86 = NULL; 102 #endif 103 104 return 0; 105 } 106 107 #ifdef CONFIG_X86_64 108 void arch_release_task_struct(struct task_struct *tsk) 109 { 110 if (fpu_state_size_dynamic() && !(tsk->flags & (PF_KTHREAD | PF_USER_WORKER))) 111 fpstate_free(x86_task_fpu(tsk)); 112 } 113 #endif 114 115 /* 116 * Free thread data structures etc.. 117 */ 118 void exit_thread(struct task_struct *tsk) 119 { 120 struct thread_struct *t = &tsk->thread; 121 122 if (test_thread_flag(TIF_IO_BITMAP)) 123 io_bitmap_exit(tsk); 124 125 free_vm86(t); 126 127 shstk_free(tsk); 128 fpu__drop(tsk); 129 } 130 131 static int set_new_tls(struct task_struct *p, unsigned long tls) 132 { 133 struct user_desc __user *utls = (struct user_desc __user *)tls; 134 135 if (in_ia32_syscall()) 136 return do_set_thread_area(p, -1, utls, 0); 137 else 138 return do_set_thread_area_64(p, ARCH_SET_FS, tls); 139 } 140 141 __visible void ret_from_fork(struct task_struct *prev, struct pt_regs *regs, 142 int (*fn)(void *), void *fn_arg) 143 { 144 schedule_tail(prev); 145 146 /* Is this a kernel thread? */ 147 if (unlikely(fn)) { 148 fn(fn_arg); 149 /* 150 * A kernel thread is allowed to return here after successfully 151 * calling kernel_execve(). Exit to userspace to complete the 152 * execve() syscall. 153 */ 154 regs->ax = 0; 155 } 156 157 syscall_exit_to_user_mode(regs); 158 } 159 160 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) 161 { 162 unsigned long clone_flags = args->flags; 163 unsigned long sp = args->stack; 164 unsigned long tls = args->tls; 165 struct inactive_task_frame *frame; 166 struct fork_frame *fork_frame; 167 struct pt_regs *childregs; 168 unsigned long new_ssp; 169 int ret = 0; 170 171 childregs = task_pt_regs(p); 172 fork_frame = container_of(childregs, struct fork_frame, regs); 173 frame = &fork_frame->frame; 174 175 frame->bp = encode_frame_pointer(childregs); 176 frame->ret_addr = (unsigned long) ret_from_fork_asm; 177 p->thread.sp = (unsigned long) fork_frame; 178 p->thread.io_bitmap = NULL; 179 clear_tsk_thread_flag(p, TIF_IO_BITMAP); 180 p->thread.iopl_warn = 0; 181 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 182 183 #ifdef CONFIG_X86_64 184 current_save_fsgs(); 185 p->thread.fsindex = current->thread.fsindex; 186 p->thread.fsbase = current->thread.fsbase; 187 p->thread.gsindex = current->thread.gsindex; 188 p->thread.gsbase = current->thread.gsbase; 189 190 savesegment(es, p->thread.es); 191 savesegment(ds, p->thread.ds); 192 193 if (p->mm && (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM) 194 set_bit(MM_CONTEXT_LOCK_LAM, &p->mm->context.flags); 195 #else 196 p->thread.sp0 = (unsigned long) (childregs + 1); 197 savesegment(gs, p->thread.gs); 198 /* 199 * Clear all status flags including IF and set fixed bit. 64bit 200 * does not have this initialization as the frame does not contain 201 * flags. The flags consistency (especially vs. AC) is there 202 * ensured via objtool, which lacks 32bit support. 203 */ 204 frame->flags = X86_EFLAGS_FIXED; 205 #endif 206 207 /* 208 * Allocate a new shadow stack for thread if needed. If shadow stack, 209 * is disabled, new_ssp will remain 0, and fpu_clone() will know not to 210 * update it. 211 */ 212 new_ssp = shstk_alloc_thread_stack(p, clone_flags, args->stack_size); 213 if (IS_ERR_VALUE(new_ssp)) 214 return PTR_ERR((void *)new_ssp); 215 216 fpu_clone(p, clone_flags, args->fn, new_ssp); 217 218 /* Kernel thread ? */ 219 if (unlikely(p->flags & PF_KTHREAD)) { 220 p->thread.pkru = pkru_get_init_value(); 221 memset(childregs, 0, sizeof(struct pt_regs)); 222 kthread_frame_init(frame, args->fn, args->fn_arg); 223 return 0; 224 } 225 226 /* 227 * Clone current's PKRU value from hardware. tsk->thread.pkru 228 * is only valid when scheduled out. 229 */ 230 p->thread.pkru = read_pkru(); 231 232 frame->bx = 0; 233 *childregs = *current_pt_regs(); 234 childregs->ax = 0; 235 if (sp) 236 childregs->sp = sp; 237 238 if (unlikely(args->fn)) { 239 /* 240 * A user space thread, but it doesn't return to 241 * ret_after_fork(). 242 * 243 * In order to indicate that to tools like gdb, 244 * we reset the stack and instruction pointers. 245 * 246 * It does the same kernel frame setup to return to a kernel 247 * function that a kernel thread does. 248 */ 249 childregs->sp = 0; 250 childregs->ip = 0; 251 kthread_frame_init(frame, args->fn, args->fn_arg); 252 return 0; 253 } 254 255 /* Set a new TLS for the child thread? */ 256 if (clone_flags & CLONE_SETTLS) 257 ret = set_new_tls(p, tls); 258 259 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) 260 io_bitmap_share(p); 261 262 return ret; 263 } 264 265 static void pkru_flush_thread(void) 266 { 267 /* 268 * If PKRU is enabled the default PKRU value has to be loaded into 269 * the hardware right here (similar to context switch). 270 */ 271 pkru_write_default(); 272 } 273 274 void flush_thread(void) 275 { 276 struct task_struct *tsk = current; 277 278 flush_ptrace_hw_breakpoint(tsk); 279 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 280 281 fpu_flush_thread(); 282 pkru_flush_thread(); 283 } 284 285 void disable_TSC(void) 286 { 287 preempt_disable(); 288 if (!test_and_set_thread_flag(TIF_NOTSC)) 289 /* 290 * Must flip the CPU state synchronously with 291 * TIF_NOTSC in the current running context. 292 */ 293 cr4_set_bits(X86_CR4_TSD); 294 preempt_enable(); 295 } 296 297 static void enable_TSC(void) 298 { 299 preempt_disable(); 300 if (test_and_clear_thread_flag(TIF_NOTSC)) 301 /* 302 * Must flip the CPU state synchronously with 303 * TIF_NOTSC in the current running context. 304 */ 305 cr4_clear_bits(X86_CR4_TSD); 306 preempt_enable(); 307 } 308 309 int get_tsc_mode(unsigned long adr) 310 { 311 unsigned int val; 312 313 if (test_thread_flag(TIF_NOTSC)) 314 val = PR_TSC_SIGSEGV; 315 else 316 val = PR_TSC_ENABLE; 317 318 return put_user(val, (unsigned int __user *)adr); 319 } 320 321 int set_tsc_mode(unsigned int val) 322 { 323 if (val == PR_TSC_SIGSEGV) 324 disable_TSC(); 325 else if (val == PR_TSC_ENABLE) 326 enable_TSC(); 327 else 328 return -EINVAL; 329 330 return 0; 331 } 332 333 DEFINE_PER_CPU(u64, msr_misc_features_shadow); 334 335 static void set_cpuid_faulting(bool on) 336 { 337 u64 msrval; 338 339 msrval = this_cpu_read(msr_misc_features_shadow); 340 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 341 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 342 this_cpu_write(msr_misc_features_shadow, msrval); 343 wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval); 344 } 345 346 static void disable_cpuid(void) 347 { 348 preempt_disable(); 349 if (!test_and_set_thread_flag(TIF_NOCPUID)) { 350 /* 351 * Must flip the CPU state synchronously with 352 * TIF_NOCPUID in the current running context. 353 */ 354 set_cpuid_faulting(true); 355 } 356 preempt_enable(); 357 } 358 359 static void enable_cpuid(void) 360 { 361 preempt_disable(); 362 if (test_and_clear_thread_flag(TIF_NOCPUID)) { 363 /* 364 * Must flip the CPU state synchronously with 365 * TIF_NOCPUID in the current running context. 366 */ 367 set_cpuid_faulting(false); 368 } 369 preempt_enable(); 370 } 371 372 static int get_cpuid_mode(void) 373 { 374 return !test_thread_flag(TIF_NOCPUID); 375 } 376 377 static int set_cpuid_mode(unsigned long cpuid_enabled) 378 { 379 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) 380 return -ENODEV; 381 382 if (cpuid_enabled) 383 enable_cpuid(); 384 else 385 disable_cpuid(); 386 387 return 0; 388 } 389 390 /* 391 * Called immediately after a successful exec. 392 */ 393 void arch_setup_new_exec(void) 394 { 395 /* If cpuid was previously disabled for this task, re-enable it. */ 396 if (test_thread_flag(TIF_NOCPUID)) 397 enable_cpuid(); 398 399 /* 400 * Don't inherit TIF_SSBD across exec boundary when 401 * PR_SPEC_DISABLE_NOEXEC is used. 402 */ 403 if (test_thread_flag(TIF_SSBD) && 404 task_spec_ssb_noexec(current)) { 405 clear_thread_flag(TIF_SSBD); 406 task_clear_spec_ssb_disable(current); 407 task_clear_spec_ssb_noexec(current); 408 speculation_ctrl_update(read_thread_flags()); 409 } 410 411 mm_reset_untag_mask(current->mm); 412 } 413 414 #ifdef CONFIG_X86_IOPL_IOPERM 415 static inline void switch_to_bitmap(unsigned long tifp) 416 { 417 /* 418 * Invalidate I/O bitmap if the previous task used it. This prevents 419 * any possible leakage of an active I/O bitmap. 420 * 421 * If the next task has an I/O bitmap it will handle it on exit to 422 * user mode. 423 */ 424 if (tifp & _TIF_IO_BITMAP) 425 tss_invalidate_io_bitmap(); 426 } 427 428 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) 429 { 430 /* 431 * Copy at least the byte range of the incoming tasks bitmap which 432 * covers the permitted I/O ports. 433 * 434 * If the previous task which used an I/O bitmap had more bits 435 * permitted, then the copy needs to cover those as well so they 436 * get turned off. 437 */ 438 memcpy(tss->io_bitmap.bitmap, iobm->bitmap, 439 max(tss->io_bitmap.prev_max, iobm->max)); 440 441 /* 442 * Store the new max and the sequence number of this bitmap 443 * and a pointer to the bitmap itself. 444 */ 445 tss->io_bitmap.prev_max = iobm->max; 446 tss->io_bitmap.prev_sequence = iobm->sequence; 447 } 448 449 /** 450 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode 451 */ 452 void native_tss_update_io_bitmap(void) 453 { 454 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 455 struct thread_struct *t = ¤t->thread; 456 u16 *base = &tss->x86_tss.io_bitmap_base; 457 458 if (!test_thread_flag(TIF_IO_BITMAP)) { 459 native_tss_invalidate_io_bitmap(); 460 return; 461 } 462 463 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { 464 *base = IO_BITMAP_OFFSET_VALID_ALL; 465 } else { 466 struct io_bitmap *iobm = t->io_bitmap; 467 468 if (WARN_ON_ONCE(!iobm)) { 469 clear_thread_flag(TIF_IO_BITMAP); 470 native_tss_invalidate_io_bitmap(); 471 } 472 473 /* 474 * Only copy bitmap data when the sequence number differs. The 475 * update time is accounted to the incoming task. 476 */ 477 if (tss->io_bitmap.prev_sequence != iobm->sequence) 478 tss_copy_io_bitmap(tss, iobm); 479 480 /* Enable the bitmap */ 481 *base = IO_BITMAP_OFFSET_VALID_MAP; 482 } 483 484 /* 485 * Make sure that the TSS limit is covering the IO bitmap. It might have 486 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 487 * access from user space to trigger a #GP because the bitmap is outside 488 * the TSS limit. 489 */ 490 refresh_tss_limit(); 491 } 492 #else /* CONFIG_X86_IOPL_IOPERM */ 493 static inline void switch_to_bitmap(unsigned long tifp) { } 494 #endif 495 496 #ifdef CONFIG_SMP 497 498 struct ssb_state { 499 struct ssb_state *shared_state; 500 raw_spinlock_t lock; 501 unsigned int disable_state; 502 unsigned long local_state; 503 }; 504 505 #define LSTATE_SSB 0 506 507 static DEFINE_PER_CPU(struct ssb_state, ssb_state); 508 509 void speculative_store_bypass_ht_init(void) 510 { 511 struct ssb_state *st = this_cpu_ptr(&ssb_state); 512 unsigned int this_cpu = smp_processor_id(); 513 unsigned int cpu; 514 515 st->local_state = 0; 516 517 /* 518 * Shared state setup happens once on the first bringup 519 * of the CPU. It's not destroyed on CPU hotunplug. 520 */ 521 if (st->shared_state) 522 return; 523 524 raw_spin_lock_init(&st->lock); 525 526 /* 527 * Go over HT siblings and check whether one of them has set up the 528 * shared state pointer already. 529 */ 530 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { 531 if (cpu == this_cpu) 532 continue; 533 534 if (!per_cpu(ssb_state, cpu).shared_state) 535 continue; 536 537 /* Link it to the state of the sibling: */ 538 st->shared_state = per_cpu(ssb_state, cpu).shared_state; 539 return; 540 } 541 542 /* 543 * First HT sibling to come up on the core. Link shared state of 544 * the first HT sibling to itself. The siblings on the same core 545 * which come up later will see the shared state pointer and link 546 * themselves to the state of this CPU. 547 */ 548 st->shared_state = st; 549 } 550 551 /* 552 * Logic is: First HT sibling enables SSBD for both siblings in the core 553 * and last sibling to disable it, disables it for the whole core. This how 554 * MSR_SPEC_CTRL works in "hardware": 555 * 556 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL 557 */ 558 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 559 { 560 struct ssb_state *st = this_cpu_ptr(&ssb_state); 561 u64 msr = x86_amd_ls_cfg_base; 562 563 if (!static_cpu_has(X86_FEATURE_ZEN)) { 564 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 565 wrmsrq(MSR_AMD64_LS_CFG, msr); 566 return; 567 } 568 569 if (tifn & _TIF_SSBD) { 570 /* 571 * Since this can race with prctl(), block reentry on the 572 * same CPU. 573 */ 574 if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) 575 return; 576 577 msr |= x86_amd_ls_cfg_ssbd_mask; 578 579 raw_spin_lock(&st->shared_state->lock); 580 /* First sibling enables SSBD: */ 581 if (!st->shared_state->disable_state) 582 wrmsrq(MSR_AMD64_LS_CFG, msr); 583 st->shared_state->disable_state++; 584 raw_spin_unlock(&st->shared_state->lock); 585 } else { 586 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) 587 return; 588 589 raw_spin_lock(&st->shared_state->lock); 590 st->shared_state->disable_state--; 591 if (!st->shared_state->disable_state) 592 wrmsrq(MSR_AMD64_LS_CFG, msr); 593 raw_spin_unlock(&st->shared_state->lock); 594 } 595 } 596 #else 597 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 598 { 599 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 600 601 wrmsrq(MSR_AMD64_LS_CFG, msr); 602 } 603 #endif 604 605 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) 606 { 607 /* 608 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 609 * so ssbd_tif_to_spec_ctrl() just works. 610 */ 611 wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 612 } 613 614 /* 615 * Update the MSRs managing speculation control, during context switch. 616 * 617 * tifp: Previous task's thread flags 618 * tifn: Next task's thread flags 619 */ 620 static __always_inline void __speculation_ctrl_update(unsigned long tifp, 621 unsigned long tifn) 622 { 623 unsigned long tif_diff = tifp ^ tifn; 624 u64 msr = x86_spec_ctrl_base; 625 bool updmsr = false; 626 627 lockdep_assert_irqs_disabled(); 628 629 /* Handle change of TIF_SSBD depending on the mitigation method. */ 630 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { 631 if (tif_diff & _TIF_SSBD) 632 amd_set_ssb_virt_state(tifn); 633 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { 634 if (tif_diff & _TIF_SSBD) 635 amd_set_core_ssb_state(tifn); 636 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 637 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 638 updmsr |= !!(tif_diff & _TIF_SSBD); 639 msr |= ssbd_tif_to_spec_ctrl(tifn); 640 } 641 642 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ 643 if (IS_ENABLED(CONFIG_SMP) && 644 static_branch_unlikely(&switch_to_cond_stibp)) { 645 updmsr |= !!(tif_diff & _TIF_SPEC_IB); 646 msr |= stibp_tif_to_spec_ctrl(tifn); 647 } 648 649 if (updmsr) 650 update_spec_ctrl_cond(msr); 651 } 652 653 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) 654 { 655 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { 656 if (task_spec_ssb_disable(tsk)) 657 set_tsk_thread_flag(tsk, TIF_SSBD); 658 else 659 clear_tsk_thread_flag(tsk, TIF_SSBD); 660 661 if (task_spec_ib_disable(tsk)) 662 set_tsk_thread_flag(tsk, TIF_SPEC_IB); 663 else 664 clear_tsk_thread_flag(tsk, TIF_SPEC_IB); 665 } 666 /* Return the updated threadinfo flags*/ 667 return read_task_thread_flags(tsk); 668 } 669 670 void speculation_ctrl_update(unsigned long tif) 671 { 672 unsigned long flags; 673 674 /* Forced update. Make sure all relevant TIF flags are different */ 675 local_irq_save(flags); 676 __speculation_ctrl_update(~tif, tif); 677 local_irq_restore(flags); 678 } 679 680 /* Called from seccomp/prctl update */ 681 void speculation_ctrl_update_current(void) 682 { 683 preempt_disable(); 684 speculation_ctrl_update(speculation_ctrl_update_tif(current)); 685 preempt_enable(); 686 } 687 688 static inline void cr4_toggle_bits_irqsoff(unsigned long mask) 689 { 690 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 691 692 newval = cr4 ^ mask; 693 if (newval != cr4) { 694 this_cpu_write(cpu_tlbstate.cr4, newval); 695 __write_cr4(newval); 696 } 697 } 698 699 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) 700 { 701 unsigned long tifp, tifn; 702 703 tifn = read_task_thread_flags(next_p); 704 tifp = read_task_thread_flags(prev_p); 705 706 switch_to_bitmap(tifp); 707 708 propagate_user_return_notify(prev_p, next_p); 709 710 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && 711 arch_has_block_step()) { 712 unsigned long debugctl, msk; 713 714 rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 715 debugctl &= ~DEBUGCTLMSR_BTF; 716 msk = tifn & _TIF_BLOCKSTEP; 717 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 718 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 719 } 720 721 if ((tifp ^ tifn) & _TIF_NOTSC) 722 cr4_toggle_bits_irqsoff(X86_CR4_TSD); 723 724 if ((tifp ^ tifn) & _TIF_NOCPUID) 725 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); 726 727 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { 728 __speculation_ctrl_update(tifp, tifn); 729 } else { 730 speculation_ctrl_update_tif(prev_p); 731 tifn = speculation_ctrl_update_tif(next_p); 732 733 /* Enforce MSR update to ensure consistent state */ 734 __speculation_ctrl_update(~tifn, tifn); 735 } 736 } 737 738 /* 739 * Idle related variables and functions 740 */ 741 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; 742 EXPORT_SYMBOL(boot_option_idle_override); 743 744 /* 745 * We use this if we don't have any better idle routine.. 746 */ 747 void __cpuidle default_idle(void) 748 { 749 raw_safe_halt(); 750 raw_local_irq_disable(); 751 } 752 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) 753 EXPORT_SYMBOL(default_idle); 754 #endif 755 756 DEFINE_STATIC_CALL_NULL(x86_idle, default_idle); 757 758 static bool x86_idle_set(void) 759 { 760 return !!static_call_query(x86_idle); 761 } 762 763 #ifndef CONFIG_SMP 764 static inline void __noreturn play_dead(void) 765 { 766 BUG(); 767 } 768 #endif 769 770 void arch_cpu_idle_enter(void) 771 { 772 tsc_verify_tsc_adjust(false); 773 local_touch_nmi(); 774 } 775 776 void __noreturn arch_cpu_idle_dead(void) 777 { 778 play_dead(); 779 } 780 781 /* 782 * Called from the generic idle code. 783 */ 784 void __cpuidle arch_cpu_idle(void) 785 { 786 static_call(x86_idle)(); 787 } 788 EXPORT_SYMBOL_GPL(arch_cpu_idle); 789 790 #ifdef CONFIG_XEN 791 bool xen_set_default_idle(void) 792 { 793 bool ret = x86_idle_set(); 794 795 static_call_update(x86_idle, default_idle); 796 797 return ret; 798 } 799 #endif 800 801 struct cpumask cpus_stop_mask; 802 803 void __noreturn stop_this_cpu(void *dummy) 804 { 805 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 806 unsigned int cpu = smp_processor_id(); 807 808 local_irq_disable(); 809 810 /* 811 * Remove this CPU from the online mask and disable it 812 * unconditionally. This might be redundant in case that the reboot 813 * vector was handled late and stop_other_cpus() sent an NMI. 814 * 815 * According to SDM and APM NMIs can be accepted even after soft 816 * disabling the local APIC. 817 */ 818 set_cpu_online(cpu, false); 819 disable_local_APIC(); 820 mcheck_cpu_clear(c); 821 822 /* 823 * Use wbinvd on processors that support SME. This provides support 824 * for performing a successful kexec when going from SME inactive 825 * to SME active (or vice-versa). The cache must be cleared so that 826 * if there are entries with the same physical address, both with and 827 * without the encryption bit, they don't race each other when flushed 828 * and potentially end up with the wrong entry being committed to 829 * memory. 830 * 831 * Test the CPUID bit directly because the machine might've cleared 832 * X86_FEATURE_SME due to cmdline options. 833 */ 834 if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0))) 835 wbinvd(); 836 837 /* 838 * This brings a cache line back and dirties it, but 839 * native_stop_other_cpus() will overwrite cpus_stop_mask after it 840 * observed that all CPUs reported stop. This write will invalidate 841 * the related cache line on this CPU. 842 */ 843 cpumask_clear_cpu(cpu, &cpus_stop_mask); 844 845 #ifdef CONFIG_SMP 846 if (smp_ops.stop_this_cpu) { 847 smp_ops.stop_this_cpu(); 848 BUG(); 849 } 850 #endif 851 852 for (;;) { 853 /* 854 * Use native_halt() so that memory contents don't change 855 * (stack usage and variables) after possibly issuing the 856 * wbinvd() above. 857 */ 858 native_halt(); 859 } 860 } 861 862 /* 863 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf 864 * exists and whenever MONITOR/MWAIT extensions are present there is at 865 * least one C1 substate. 866 * 867 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait 868 * is passed to kernel commandline parameter. 869 */ 870 static __init bool prefer_mwait_c1_over_halt(void) 871 { 872 const struct cpuinfo_x86 *c = &boot_cpu_data; 873 u32 eax, ebx, ecx, edx; 874 875 /* If override is enforced on the command line, fall back to HALT. */ 876 if (boot_option_idle_override != IDLE_NO_OVERRIDE) 877 return false; 878 879 /* MWAIT is not supported on this platform. Fallback to HALT */ 880 if (!cpu_has(c, X86_FEATURE_MWAIT)) 881 return false; 882 883 /* Monitor has a bug or APIC stops in C1E. Fallback to HALT */ 884 if (boot_cpu_has_bug(X86_BUG_MONITOR) || boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) 885 return false; 886 887 cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); 888 889 /* 890 * If MWAIT extensions are not available, it is safe to use MWAIT 891 * with EAX=0, ECX=0. 892 */ 893 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) 894 return true; 895 896 /* 897 * If MWAIT extensions are available, there should be at least one 898 * MWAIT C1 substate present. 899 */ 900 return !!(edx & MWAIT_C1_SUBSTATE_MASK); 901 } 902 903 /* 904 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT 905 * with interrupts enabled and no flags, which is backwards compatible with the 906 * original MWAIT implementation. 907 */ 908 static __cpuidle void mwait_idle(void) 909 { 910 if (!current_set_polling_and_test()) { 911 const void *addr = ¤t_thread_info()->flags; 912 913 alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr)); 914 __monitor(addr, 0, 0); 915 if (!need_resched()) { 916 __sti_mwait(0, 0); 917 raw_local_irq_disable(); 918 } 919 } 920 __current_clr_polling(); 921 } 922 923 void __init select_idle_routine(void) 924 { 925 if (boot_option_idle_override == IDLE_POLL) { 926 if (IS_ENABLED(CONFIG_SMP) && __max_threads_per_core > 1) 927 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); 928 return; 929 } 930 931 /* Required to guard against xen_set_default_idle() */ 932 if (x86_idle_set()) 933 return; 934 935 if (prefer_mwait_c1_over_halt()) { 936 pr_info("using mwait in idle threads\n"); 937 static_call_update(x86_idle, mwait_idle); 938 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { 939 pr_info("using TDX aware idle routine\n"); 940 static_call_update(x86_idle, tdx_halt); 941 } else { 942 static_call_update(x86_idle, default_idle); 943 } 944 } 945 946 void amd_e400_c1e_apic_setup(void) 947 { 948 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 949 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); 950 local_irq_disable(); 951 tick_broadcast_force(); 952 local_irq_enable(); 953 } 954 } 955 956 void __init arch_post_acpi_subsys_init(void) 957 { 958 u32 lo, hi; 959 960 if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) 961 return; 962 963 /* 964 * AMD E400 detection needs to happen after ACPI has been enabled. If 965 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in 966 * MSR_K8_INT_PENDING_MSG. 967 */ 968 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 969 if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) 970 return; 971 972 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); 973 974 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 975 mark_tsc_unstable("TSC halt in AMD C1E"); 976 977 if (IS_ENABLED(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE)) 978 static_branch_enable(&arch_needs_tick_broadcast); 979 pr_info("System has AMD C1E erratum E400. Workaround enabled.\n"); 980 } 981 982 static int __init idle_setup(char *str) 983 { 984 if (!str) 985 return -EINVAL; 986 987 if (!strcmp(str, "poll")) { 988 pr_info("using polling idle threads\n"); 989 boot_option_idle_override = IDLE_POLL; 990 cpu_idle_poll_ctrl(true); 991 } else if (!strcmp(str, "halt")) { 992 /* 'idle=halt' HALT for idle. C-states are disabled. */ 993 boot_option_idle_override = IDLE_HALT; 994 } else if (!strcmp(str, "nomwait")) { 995 /* 'idle=nomwait' disables MWAIT for idle */ 996 boot_option_idle_override = IDLE_NOMWAIT; 997 } else { 998 return -EINVAL; 999 } 1000 1001 return 0; 1002 } 1003 early_param("idle", idle_setup); 1004 1005 unsigned long arch_align_stack(unsigned long sp) 1006 { 1007 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1008 sp -= get_random_u32_below(8192); 1009 return sp & ~0xf; 1010 } 1011 1012 unsigned long arch_randomize_brk(struct mm_struct *mm) 1013 { 1014 if (mmap_is_ia32()) 1015 return randomize_page(mm->brk, SZ_32M); 1016 1017 return randomize_page(mm->brk, SZ_1G); 1018 } 1019 1020 /* 1021 * Called from fs/proc with a reference on @p to find the function 1022 * which called into schedule(). This needs to be done carefully 1023 * because the task might wake up and we might look at a stack 1024 * changing under us. 1025 */ 1026 unsigned long __get_wchan(struct task_struct *p) 1027 { 1028 struct unwind_state state; 1029 unsigned long addr = 0; 1030 1031 if (!try_get_task_stack(p)) 1032 return 0; 1033 1034 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); 1035 unwind_next_frame(&state)) { 1036 addr = unwind_get_return_address(&state); 1037 if (!addr) 1038 break; 1039 if (in_sched_functions(addr)) 1040 continue; 1041 break; 1042 } 1043 1044 put_task_stack(p); 1045 1046 return addr; 1047 } 1048 1049 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2) 1050 { 1051 switch (option) { 1052 case ARCH_GET_CPUID: 1053 return get_cpuid_mode(); 1054 case ARCH_SET_CPUID: 1055 return set_cpuid_mode(arg2); 1056 case ARCH_GET_XCOMP_SUPP: 1057 case ARCH_GET_XCOMP_PERM: 1058 case ARCH_REQ_XCOMP_PERM: 1059 case ARCH_GET_XCOMP_GUEST_PERM: 1060 case ARCH_REQ_XCOMP_GUEST_PERM: 1061 return fpu_xstate_prctl(option, arg2); 1062 } 1063 1064 if (!in_ia32_syscall()) 1065 return do_arch_prctl_64(current, option, arg2); 1066 1067 return -EINVAL; 1068 } 1069 1070 SYSCALL_DEFINE0(ni_syscall) 1071 { 1072 return -ENOSYS; 1073 } 1074