1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/errno.h> 5 #include <linux/kernel.h> 6 #include <linux/mm.h> 7 #include <linux/smp.h> 8 #include <linux/cpu.h> 9 #include <linux/prctl.h> 10 #include <linux/slab.h> 11 #include <linux/sched.h> 12 #include <linux/sched/idle.h> 13 #include <linux/sched/debug.h> 14 #include <linux/sched/task.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 #include <linux/pm.h> 19 #include <linux/tick.h> 20 #include <linux/random.h> 21 #include <linux/user-return-notifier.h> 22 #include <linux/dmi.h> 23 #include <linux/utsname.h> 24 #include <linux/stackprotector.h> 25 #include <linux/cpuidle.h> 26 #include <linux/acpi.h> 27 #include <linux/elf-randomize.h> 28 #include <linux/static_call.h> 29 #include <trace/events/power.h> 30 #include <linux/hw_breakpoint.h> 31 #include <linux/entry-common.h> 32 #include <asm/cpu.h> 33 #include <asm/cpuid/api.h> 34 #include <asm/apic.h> 35 #include <linux/uaccess.h> 36 #include <asm/mwait.h> 37 #include <asm/fpu/api.h> 38 #include <asm/fpu/sched.h> 39 #include <asm/fpu/xstate.h> 40 #include <asm/debugreg.h> 41 #include <asm/nmi.h> 42 #include <asm/tlbflush.h> 43 #include <asm/mce.h> 44 #include <asm/vm86.h> 45 #include <asm/switch_to.h> 46 #include <asm/desc.h> 47 #include <asm/prctl.h> 48 #include <asm/spec-ctrl.h> 49 #include <asm/io_bitmap.h> 50 #include <asm/proto.h> 51 #include <asm/frame.h> 52 #include <asm/unwind.h> 53 #include <asm/tdx.h> 54 #include <asm/mmu_context.h> 55 #include <asm/msr.h> 56 #include <asm/shstk.h> 57 58 #include "process.h" 59 60 /* 61 * per-CPU TSS segments. Threads are completely 'soft' on Linux, 62 * no more per-task TSS's. The TSS size is kept cacheline-aligned 63 * so they are allowed to end up in the .data..cacheline_aligned 64 * section. Since TSS's are completely CPU-local, we want them 65 * on exact cacheline boundaries, to eliminate cacheline ping-pong. 66 */ 67 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { 68 .x86_tss = { 69 /* 70 * .sp0 is only used when entering ring 0 from a lower 71 * privilege level. Since the init task never runs anything 72 * but ring 0 code, there is no need for a valid value here. 73 * Poison it. 74 */ 75 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, 76 77 #ifdef CONFIG_X86_32 78 .sp1 = TOP_OF_INIT_STACK, 79 80 .ss0 = __KERNEL_DS, 81 .ss1 = __KERNEL_CS, 82 #endif 83 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, 84 }, 85 }; 86 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); 87 88 DEFINE_PER_CPU(bool, __tss_limit_invalid); 89 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); 90 91 /* 92 * this gets called so that we can store lazy state into memory and copy the 93 * current task into the new thread. 94 */ 95 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 96 { 97 /* fpu_clone() will initialize the "dst_fpu" memory */ 98 memcpy_and_pad(dst, arch_task_struct_size, src, sizeof(*dst), 0); 99 100 #ifdef CONFIG_VM86 101 dst->thread.vm86 = NULL; 102 #endif 103 104 return 0; 105 } 106 107 #ifdef CONFIG_X86_64 108 void arch_release_task_struct(struct task_struct *tsk) 109 { 110 if (fpu_state_size_dynamic() && !(tsk->flags & (PF_KTHREAD | PF_USER_WORKER))) 111 fpstate_free(x86_task_fpu(tsk)); 112 } 113 #endif 114 115 /* 116 * Free thread data structures etc.. 117 */ 118 void exit_thread(struct task_struct *tsk) 119 { 120 struct thread_struct *t = &tsk->thread; 121 122 if (test_thread_flag(TIF_IO_BITMAP)) 123 io_bitmap_exit(tsk); 124 125 free_vm86(t); 126 127 shstk_free(tsk); 128 fpu__drop(tsk); 129 } 130 131 static int set_new_tls(struct task_struct *p, unsigned long tls) 132 { 133 struct user_desc __user *utls = (struct user_desc __user *)tls; 134 135 if (in_ia32_syscall()) 136 return do_set_thread_area(p, -1, utls, 0); 137 else 138 return do_set_thread_area_64(p, ARCH_SET_FS, tls); 139 } 140 141 __visible void ret_from_fork(struct task_struct *prev, struct pt_regs *regs, 142 int (*fn)(void *), void *fn_arg) 143 { 144 schedule_tail(prev); 145 146 /* Is this a kernel thread? */ 147 if (unlikely(fn)) { 148 fn(fn_arg); 149 /* 150 * A kernel thread is allowed to return here after successfully 151 * calling kernel_execve(). Exit to userspace to complete the 152 * execve() syscall. 153 */ 154 regs->ax = 0; 155 } 156 157 syscall_exit_to_user_mode(regs); 158 } 159 160 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) 161 { 162 unsigned long clone_flags = args->flags; 163 unsigned long sp = args->stack; 164 unsigned long tls = args->tls; 165 struct inactive_task_frame *frame; 166 struct fork_frame *fork_frame; 167 struct pt_regs *childregs; 168 unsigned long new_ssp; 169 int ret = 0; 170 171 childregs = task_pt_regs(p); 172 fork_frame = container_of(childregs, struct fork_frame, regs); 173 frame = &fork_frame->frame; 174 175 frame->bp = encode_frame_pointer(childregs); 176 frame->ret_addr = (unsigned long) ret_from_fork_asm; 177 p->thread.sp = (unsigned long) fork_frame; 178 p->thread.io_bitmap = NULL; 179 clear_tsk_thread_flag(p, TIF_IO_BITMAP); 180 p->thread.iopl_warn = 0; 181 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 182 183 #ifdef CONFIG_X86_64 184 current_save_fsgs(); 185 p->thread.fsindex = current->thread.fsindex; 186 p->thread.fsbase = current->thread.fsbase; 187 p->thread.gsindex = current->thread.gsindex; 188 p->thread.gsbase = current->thread.gsbase; 189 190 savesegment(es, p->thread.es); 191 savesegment(ds, p->thread.ds); 192 193 if (p->mm && (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM) 194 set_bit(MM_CONTEXT_LOCK_LAM, &p->mm->context.flags); 195 #else 196 p->thread.sp0 = (unsigned long) (childregs + 1); 197 savesegment(gs, p->thread.gs); 198 /* 199 * Clear all status flags including IF and set fixed bit. 64bit 200 * does not have this initialization as the frame does not contain 201 * flags. The flags consistency (especially vs. AC) is there 202 * ensured via objtool, which lacks 32bit support. 203 */ 204 frame->flags = X86_EFLAGS_FIXED; 205 #endif 206 207 /* 208 * Allocate a new shadow stack for thread if needed. If shadow stack, 209 * is disabled, new_ssp will remain 0, and fpu_clone() will know not to 210 * update it. 211 */ 212 new_ssp = shstk_alloc_thread_stack(p, clone_flags, args->stack_size); 213 if (IS_ERR_VALUE(new_ssp)) 214 return PTR_ERR((void *)new_ssp); 215 216 fpu_clone(p, clone_flags, args->fn, new_ssp); 217 218 /* Kernel thread ? */ 219 if (unlikely(p->flags & PF_KTHREAD)) { 220 p->thread.pkru = pkru_get_init_value(); 221 memset(childregs, 0, sizeof(struct pt_regs)); 222 kthread_frame_init(frame, args->fn, args->fn_arg); 223 return 0; 224 } 225 226 /* 227 * Clone current's PKRU value from hardware. tsk->thread.pkru 228 * is only valid when scheduled out. 229 */ 230 p->thread.pkru = read_pkru(); 231 232 frame->bx = 0; 233 *childregs = *current_pt_regs(); 234 childregs->ax = 0; 235 if (sp) 236 childregs->sp = sp; 237 238 if (unlikely(args->fn)) { 239 /* 240 * A user space thread, but it doesn't return to 241 * ret_after_fork(). 242 * 243 * In order to indicate that to tools like gdb, 244 * we reset the stack and instruction pointers. 245 * 246 * It does the same kernel frame setup to return to a kernel 247 * function that a kernel thread does. 248 */ 249 childregs->sp = 0; 250 childregs->ip = 0; 251 kthread_frame_init(frame, args->fn, args->fn_arg); 252 return 0; 253 } 254 255 /* Set a new TLS for the child thread? */ 256 if (clone_flags & CLONE_SETTLS) 257 ret = set_new_tls(p, tls); 258 259 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) 260 io_bitmap_share(p); 261 262 return ret; 263 } 264 265 static void pkru_flush_thread(void) 266 { 267 /* 268 * If PKRU is enabled the default PKRU value has to be loaded into 269 * the hardware right here (similar to context switch). 270 */ 271 pkru_write_default(); 272 } 273 274 void flush_thread(void) 275 { 276 struct task_struct *tsk = current; 277 278 flush_ptrace_hw_breakpoint(tsk); 279 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 280 281 fpu_flush_thread(); 282 pkru_flush_thread(); 283 } 284 285 void disable_TSC(void) 286 { 287 preempt_disable(); 288 if (!test_and_set_thread_flag(TIF_NOTSC)) 289 /* 290 * Must flip the CPU state synchronously with 291 * TIF_NOTSC in the current running context. 292 */ 293 cr4_set_bits(X86_CR4_TSD); 294 preempt_enable(); 295 } 296 297 static void enable_TSC(void) 298 { 299 preempt_disable(); 300 if (test_and_clear_thread_flag(TIF_NOTSC)) 301 /* 302 * Must flip the CPU state synchronously with 303 * TIF_NOTSC in the current running context. 304 */ 305 cr4_clear_bits(X86_CR4_TSD); 306 preempt_enable(); 307 } 308 309 int get_tsc_mode(unsigned long adr) 310 { 311 unsigned int val; 312 313 if (test_thread_flag(TIF_NOTSC)) 314 val = PR_TSC_SIGSEGV; 315 else 316 val = PR_TSC_ENABLE; 317 318 return put_user(val, (unsigned int __user *)adr); 319 } 320 321 int set_tsc_mode(unsigned int val) 322 { 323 if (val == PR_TSC_SIGSEGV) 324 disable_TSC(); 325 else if (val == PR_TSC_ENABLE) 326 enable_TSC(); 327 else 328 return -EINVAL; 329 330 return 0; 331 } 332 333 DEFINE_PER_CPU(u64, msr_misc_features_shadow); 334 335 static void set_cpuid_faulting(bool on) 336 { 337 338 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 339 u64 msrval; 340 341 msrval = this_cpu_read(msr_misc_features_shadow); 342 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 343 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 344 this_cpu_write(msr_misc_features_shadow, msrval); 345 wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval); 346 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { 347 if (on) 348 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT); 349 else 350 msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT); 351 } 352 } 353 354 static void disable_cpuid(void) 355 { 356 preempt_disable(); 357 if (!test_and_set_thread_flag(TIF_NOCPUID)) { 358 /* 359 * Must flip the CPU state synchronously with 360 * TIF_NOCPUID in the current running context. 361 */ 362 set_cpuid_faulting(true); 363 } 364 preempt_enable(); 365 } 366 367 static void enable_cpuid(void) 368 { 369 preempt_disable(); 370 if (test_and_clear_thread_flag(TIF_NOCPUID)) { 371 /* 372 * Must flip the CPU state synchronously with 373 * TIF_NOCPUID in the current running context. 374 */ 375 set_cpuid_faulting(false); 376 } 377 preempt_enable(); 378 } 379 380 static int get_cpuid_mode(void) 381 { 382 return !test_thread_flag(TIF_NOCPUID); 383 } 384 385 static int set_cpuid_mode(unsigned long cpuid_enabled) 386 { 387 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) 388 return -ENODEV; 389 390 if (cpuid_enabled) 391 enable_cpuid(); 392 else 393 disable_cpuid(); 394 395 return 0; 396 } 397 398 /* 399 * Called immediately after a successful exec. 400 */ 401 void arch_setup_new_exec(void) 402 { 403 /* If cpuid was previously disabled for this task, re-enable it. */ 404 if (test_thread_flag(TIF_NOCPUID)) 405 enable_cpuid(); 406 407 /* 408 * Don't inherit TIF_SSBD across exec boundary when 409 * PR_SPEC_DISABLE_NOEXEC is used. 410 */ 411 if (test_thread_flag(TIF_SSBD) && 412 task_spec_ssb_noexec(current)) { 413 clear_thread_flag(TIF_SSBD); 414 task_clear_spec_ssb_disable(current); 415 task_clear_spec_ssb_noexec(current); 416 speculation_ctrl_update(read_thread_flags()); 417 } 418 419 mm_reset_untag_mask(current->mm); 420 } 421 422 #ifdef CONFIG_X86_IOPL_IOPERM 423 static inline void switch_to_bitmap(unsigned long tifp) 424 { 425 /* 426 * Invalidate I/O bitmap if the previous task used it. This prevents 427 * any possible leakage of an active I/O bitmap. 428 * 429 * If the next task has an I/O bitmap it will handle it on exit to 430 * user mode. 431 */ 432 if (tifp & _TIF_IO_BITMAP) 433 tss_invalidate_io_bitmap(); 434 } 435 436 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) 437 { 438 /* 439 * Copy at least the byte range of the incoming tasks bitmap which 440 * covers the permitted I/O ports. 441 * 442 * If the previous task which used an I/O bitmap had more bits 443 * permitted, then the copy needs to cover those as well so they 444 * get turned off. 445 */ 446 memcpy(tss->io_bitmap.bitmap, iobm->bitmap, 447 max(tss->io_bitmap.prev_max, iobm->max)); 448 449 /* 450 * Store the new max and the sequence number of this bitmap 451 * and a pointer to the bitmap itself. 452 */ 453 tss->io_bitmap.prev_max = iobm->max; 454 tss->io_bitmap.prev_sequence = iobm->sequence; 455 } 456 457 /** 458 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode 459 */ 460 void native_tss_update_io_bitmap(void) 461 { 462 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 463 struct thread_struct *t = ¤t->thread; 464 u16 *base = &tss->x86_tss.io_bitmap_base; 465 466 if (!test_thread_flag(TIF_IO_BITMAP)) { 467 native_tss_invalidate_io_bitmap(); 468 return; 469 } 470 471 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { 472 *base = IO_BITMAP_OFFSET_VALID_ALL; 473 } else { 474 struct io_bitmap *iobm = t->io_bitmap; 475 476 if (WARN_ON_ONCE(!iobm)) { 477 clear_thread_flag(TIF_IO_BITMAP); 478 native_tss_invalidate_io_bitmap(); 479 } 480 481 /* 482 * Only copy bitmap data when the sequence number differs. The 483 * update time is accounted to the incoming task. 484 */ 485 if (tss->io_bitmap.prev_sequence != iobm->sequence) 486 tss_copy_io_bitmap(tss, iobm); 487 488 /* Enable the bitmap */ 489 *base = IO_BITMAP_OFFSET_VALID_MAP; 490 } 491 492 /* 493 * Make sure that the TSS limit is covering the IO bitmap. It might have 494 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 495 * access from user space to trigger a #GP because the bitmap is outside 496 * the TSS limit. 497 */ 498 refresh_tss_limit(); 499 } 500 #else /* CONFIG_X86_IOPL_IOPERM */ 501 static inline void switch_to_bitmap(unsigned long tifp) { } 502 #endif 503 504 #ifdef CONFIG_SMP 505 506 struct ssb_state { 507 struct ssb_state *shared_state; 508 raw_spinlock_t lock; 509 unsigned int disable_state; 510 unsigned long local_state; 511 }; 512 513 #define LSTATE_SSB 0 514 515 static DEFINE_PER_CPU(struct ssb_state, ssb_state); 516 517 void speculative_store_bypass_ht_init(void) 518 { 519 struct ssb_state *st = this_cpu_ptr(&ssb_state); 520 unsigned int this_cpu = smp_processor_id(); 521 unsigned int cpu; 522 523 st->local_state = 0; 524 525 /* 526 * Shared state setup happens once on the first bringup 527 * of the CPU. It's not destroyed on CPU hotunplug. 528 */ 529 if (st->shared_state) 530 return; 531 532 raw_spin_lock_init(&st->lock); 533 534 /* 535 * Go over HT siblings and check whether one of them has set up the 536 * shared state pointer already. 537 */ 538 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { 539 if (cpu == this_cpu) 540 continue; 541 542 if (!per_cpu(ssb_state, cpu).shared_state) 543 continue; 544 545 /* Link it to the state of the sibling: */ 546 st->shared_state = per_cpu(ssb_state, cpu).shared_state; 547 return; 548 } 549 550 /* 551 * First HT sibling to come up on the core. Link shared state of 552 * the first HT sibling to itself. The siblings on the same core 553 * which come up later will see the shared state pointer and link 554 * themselves to the state of this CPU. 555 */ 556 st->shared_state = st; 557 } 558 559 /* 560 * Logic is: First HT sibling enables SSBD for both siblings in the core 561 * and last sibling to disable it, disables it for the whole core. This how 562 * MSR_SPEC_CTRL works in "hardware": 563 * 564 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL 565 */ 566 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 567 { 568 struct ssb_state *st = this_cpu_ptr(&ssb_state); 569 u64 msr = x86_amd_ls_cfg_base; 570 571 if (!static_cpu_has(X86_FEATURE_ZEN)) { 572 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 573 wrmsrq(MSR_AMD64_LS_CFG, msr); 574 return; 575 } 576 577 if (tifn & _TIF_SSBD) { 578 /* 579 * Since this can race with prctl(), block reentry on the 580 * same CPU. 581 */ 582 if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) 583 return; 584 585 msr |= x86_amd_ls_cfg_ssbd_mask; 586 587 raw_spin_lock(&st->shared_state->lock); 588 /* First sibling enables SSBD: */ 589 if (!st->shared_state->disable_state) 590 wrmsrq(MSR_AMD64_LS_CFG, msr); 591 st->shared_state->disable_state++; 592 raw_spin_unlock(&st->shared_state->lock); 593 } else { 594 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) 595 return; 596 597 raw_spin_lock(&st->shared_state->lock); 598 st->shared_state->disable_state--; 599 if (!st->shared_state->disable_state) 600 wrmsrq(MSR_AMD64_LS_CFG, msr); 601 raw_spin_unlock(&st->shared_state->lock); 602 } 603 } 604 #else 605 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 606 { 607 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 608 609 wrmsrq(MSR_AMD64_LS_CFG, msr); 610 } 611 #endif 612 613 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) 614 { 615 /* 616 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 617 * so ssbd_tif_to_spec_ctrl() just works. 618 */ 619 wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 620 } 621 622 /* 623 * Update the MSRs managing speculation control, during context switch. 624 * 625 * tifp: Previous task's thread flags 626 * tifn: Next task's thread flags 627 */ 628 static __always_inline void __speculation_ctrl_update(unsigned long tifp, 629 unsigned long tifn) 630 { 631 unsigned long tif_diff = tifp ^ tifn; 632 u64 msr = x86_spec_ctrl_base; 633 bool updmsr = false; 634 635 lockdep_assert_irqs_disabled(); 636 637 /* Handle change of TIF_SSBD depending on the mitigation method. */ 638 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { 639 if (tif_diff & _TIF_SSBD) 640 amd_set_ssb_virt_state(tifn); 641 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { 642 if (tif_diff & _TIF_SSBD) 643 amd_set_core_ssb_state(tifn); 644 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 645 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 646 updmsr |= !!(tif_diff & _TIF_SSBD); 647 msr |= ssbd_tif_to_spec_ctrl(tifn); 648 } 649 650 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ 651 if (IS_ENABLED(CONFIG_SMP) && 652 static_branch_unlikely(&switch_to_cond_stibp)) { 653 updmsr |= !!(tif_diff & _TIF_SPEC_IB); 654 msr |= stibp_tif_to_spec_ctrl(tifn); 655 } 656 657 if (updmsr) 658 update_spec_ctrl_cond(msr); 659 } 660 661 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) 662 { 663 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { 664 if (task_spec_ssb_disable(tsk)) 665 set_tsk_thread_flag(tsk, TIF_SSBD); 666 else 667 clear_tsk_thread_flag(tsk, TIF_SSBD); 668 669 if (task_spec_ib_disable(tsk)) 670 set_tsk_thread_flag(tsk, TIF_SPEC_IB); 671 else 672 clear_tsk_thread_flag(tsk, TIF_SPEC_IB); 673 } 674 /* Return the updated threadinfo flags*/ 675 return read_task_thread_flags(tsk); 676 } 677 678 void speculation_ctrl_update(unsigned long tif) 679 { 680 unsigned long flags; 681 682 /* Forced update. Make sure all relevant TIF flags are different */ 683 local_irq_save(flags); 684 __speculation_ctrl_update(~tif, tif); 685 local_irq_restore(flags); 686 } 687 688 /* Called from seccomp/prctl update */ 689 void speculation_ctrl_update_current(void) 690 { 691 preempt_disable(); 692 speculation_ctrl_update(speculation_ctrl_update_tif(current)); 693 preempt_enable(); 694 } 695 696 static inline void cr4_toggle_bits_irqsoff(unsigned long mask) 697 { 698 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 699 700 newval = cr4 ^ mask; 701 if (newval != cr4) { 702 this_cpu_write(cpu_tlbstate.cr4, newval); 703 __write_cr4(newval); 704 } 705 } 706 707 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) 708 { 709 unsigned long tifp, tifn; 710 711 tifn = read_task_thread_flags(next_p); 712 tifp = read_task_thread_flags(prev_p); 713 714 switch_to_bitmap(tifp); 715 716 propagate_user_return_notify(prev_p, next_p); 717 718 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && 719 arch_has_block_step()) { 720 unsigned long debugctl, msk; 721 722 rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 723 debugctl &= ~DEBUGCTLMSR_BTF; 724 msk = tifn & _TIF_BLOCKSTEP; 725 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 726 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 727 } 728 729 if ((tifp ^ tifn) & _TIF_NOTSC) 730 cr4_toggle_bits_irqsoff(X86_CR4_TSD); 731 732 if ((tifp ^ tifn) & _TIF_NOCPUID) 733 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); 734 735 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { 736 __speculation_ctrl_update(tifp, tifn); 737 } else { 738 speculation_ctrl_update_tif(prev_p); 739 tifn = speculation_ctrl_update_tif(next_p); 740 741 /* Enforce MSR update to ensure consistent state */ 742 __speculation_ctrl_update(~tifn, tifn); 743 } 744 } 745 746 /* 747 * Idle related variables and functions 748 */ 749 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; 750 EXPORT_SYMBOL(boot_option_idle_override); 751 752 /* 753 * We use this if we don't have any better idle routine.. 754 */ 755 void __cpuidle default_idle(void) 756 { 757 raw_safe_halt(); 758 raw_local_irq_disable(); 759 } 760 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) 761 EXPORT_SYMBOL(default_idle); 762 #endif 763 764 DEFINE_STATIC_CALL_NULL(x86_idle, default_idle); 765 766 static bool x86_idle_set(void) 767 { 768 return !!static_call_query(x86_idle); 769 } 770 771 #ifndef CONFIG_SMP 772 static inline void __noreturn play_dead(void) 773 { 774 BUG(); 775 } 776 #endif 777 778 void arch_cpu_idle_enter(void) 779 { 780 tsc_verify_tsc_adjust(false); 781 local_touch_nmi(); 782 } 783 784 void __noreturn arch_cpu_idle_dead(void) 785 { 786 play_dead(); 787 } 788 789 /* 790 * Called from the generic idle code. 791 */ 792 void __cpuidle arch_cpu_idle(void) 793 { 794 static_call(x86_idle)(); 795 } 796 EXPORT_SYMBOL_GPL(arch_cpu_idle); 797 798 #ifdef CONFIG_XEN 799 bool xen_set_default_idle(void) 800 { 801 bool ret = x86_idle_set(); 802 803 static_call_update(x86_idle, default_idle); 804 805 return ret; 806 } 807 #endif 808 809 struct cpumask cpus_stop_mask; 810 811 void __noreturn stop_this_cpu(void *dummy) 812 { 813 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 814 unsigned int cpu = smp_processor_id(); 815 816 local_irq_disable(); 817 818 /* 819 * Remove this CPU from the online mask and disable it 820 * unconditionally. This might be redundant in case that the reboot 821 * vector was handled late and stop_other_cpus() sent an NMI. 822 * 823 * According to SDM and APM NMIs can be accepted even after soft 824 * disabling the local APIC. 825 */ 826 set_cpu_online(cpu, false); 827 disable_local_APIC(); 828 mcheck_cpu_clear(c); 829 830 /* 831 * Use wbinvd on processors that support SME. This provides support 832 * for performing a successful kexec when going from SME inactive 833 * to SME active (or vice-versa). The cache must be cleared so that 834 * if there are entries with the same physical address, both with and 835 * without the encryption bit, they don't race each other when flushed 836 * and potentially end up with the wrong entry being committed to 837 * memory. 838 * 839 * Test the CPUID bit directly because the machine might've cleared 840 * X86_FEATURE_SME due to cmdline options. 841 */ 842 if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0))) 843 wbinvd(); 844 845 /* 846 * This brings a cache line back and dirties it, but 847 * native_stop_other_cpus() will overwrite cpus_stop_mask after it 848 * observed that all CPUs reported stop. This write will invalidate 849 * the related cache line on this CPU. 850 */ 851 cpumask_clear_cpu(cpu, &cpus_stop_mask); 852 853 #ifdef CONFIG_SMP 854 if (smp_ops.stop_this_cpu) { 855 smp_ops.stop_this_cpu(); 856 BUG(); 857 } 858 #endif 859 860 for (;;) { 861 /* 862 * Use native_halt() so that memory contents don't change 863 * (stack usage and variables) after possibly issuing the 864 * wbinvd() above. 865 */ 866 native_halt(); 867 } 868 } 869 870 /* 871 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf 872 * exists and whenever MONITOR/MWAIT extensions are present there is at 873 * least one C1 substate. 874 * 875 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait 876 * is passed to kernel commandline parameter. 877 */ 878 static __init bool prefer_mwait_c1_over_halt(void) 879 { 880 const struct cpuinfo_x86 *c = &boot_cpu_data; 881 u32 eax, ebx, ecx, edx; 882 883 /* If override is enforced on the command line, fall back to HALT. */ 884 if (boot_option_idle_override != IDLE_NO_OVERRIDE) 885 return false; 886 887 /* MWAIT is not supported on this platform. Fallback to HALT */ 888 if (!cpu_has(c, X86_FEATURE_MWAIT)) 889 return false; 890 891 /* Monitor has a bug or APIC stops in C1E. Fallback to HALT */ 892 if (boot_cpu_has_bug(X86_BUG_MONITOR) || boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) 893 return false; 894 895 cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx); 896 897 /* 898 * If MWAIT extensions are not available, it is safe to use MWAIT 899 * with EAX=0, ECX=0. 900 */ 901 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) 902 return true; 903 904 /* 905 * If MWAIT extensions are available, there should be at least one 906 * MWAIT C1 substate present. 907 */ 908 return !!(edx & MWAIT_C1_SUBSTATE_MASK); 909 } 910 911 /* 912 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT 913 * with interrupts enabled and no flags, which is backwards compatible with the 914 * original MWAIT implementation. 915 */ 916 static __cpuidle void mwait_idle(void) 917 { 918 if (need_resched()) 919 return; 920 921 x86_idle_clear_cpu_buffers(); 922 923 if (!current_set_polling_and_test()) { 924 const void *addr = ¤t_thread_info()->flags; 925 926 alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr)); 927 __monitor(addr, 0, 0); 928 if (need_resched()) 929 goto out; 930 931 __sti_mwait(0, 0); 932 raw_local_irq_disable(); 933 } 934 935 out: 936 __current_clr_polling(); 937 } 938 939 void __init select_idle_routine(void) 940 { 941 if (boot_option_idle_override == IDLE_POLL) { 942 if (IS_ENABLED(CONFIG_SMP) && __max_threads_per_core > 1) 943 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); 944 return; 945 } 946 947 /* Required to guard against xen_set_default_idle() */ 948 if (x86_idle_set()) 949 return; 950 951 if (prefer_mwait_c1_over_halt()) { 952 pr_info("using mwait in idle threads\n"); 953 static_call_update(x86_idle, mwait_idle); 954 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { 955 pr_info("using TDX aware idle routine\n"); 956 static_call_update(x86_idle, tdx_halt); 957 } else { 958 static_call_update(x86_idle, default_idle); 959 } 960 } 961 962 void amd_e400_c1e_apic_setup(void) 963 { 964 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 965 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); 966 local_irq_disable(); 967 tick_broadcast_force(); 968 local_irq_enable(); 969 } 970 } 971 972 void __init arch_post_acpi_subsys_init(void) 973 { 974 u32 lo, hi; 975 976 if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) 977 return; 978 979 /* 980 * AMD E400 detection needs to happen after ACPI has been enabled. If 981 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in 982 * MSR_K8_INT_PENDING_MSG. 983 */ 984 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 985 if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) 986 return; 987 988 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); 989 990 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 991 mark_tsc_unstable("TSC halt in AMD C1E"); 992 993 if (IS_ENABLED(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE)) 994 static_branch_enable(&arch_needs_tick_broadcast); 995 pr_info("System has AMD C1E erratum E400. Workaround enabled.\n"); 996 } 997 998 static int __init idle_setup(char *str) 999 { 1000 if (!str) 1001 return -EINVAL; 1002 1003 if (!strcmp(str, "poll")) { 1004 pr_info("using polling idle threads\n"); 1005 boot_option_idle_override = IDLE_POLL; 1006 cpu_idle_poll_ctrl(true); 1007 } else if (!strcmp(str, "halt")) { 1008 /* 'idle=halt' HALT for idle. C-states are disabled. */ 1009 boot_option_idle_override = IDLE_HALT; 1010 } else if (!strcmp(str, "nomwait")) { 1011 /* 'idle=nomwait' disables MWAIT for idle */ 1012 boot_option_idle_override = IDLE_NOMWAIT; 1013 } else { 1014 return -EINVAL; 1015 } 1016 1017 return 0; 1018 } 1019 early_param("idle", idle_setup); 1020 1021 unsigned long arch_align_stack(unsigned long sp) 1022 { 1023 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 1024 sp -= get_random_u32_below(8192); 1025 return sp & ~0xf; 1026 } 1027 1028 unsigned long arch_randomize_brk(struct mm_struct *mm) 1029 { 1030 if (mmap_is_ia32()) 1031 return randomize_page(mm->brk, SZ_32M); 1032 1033 return randomize_page(mm->brk, SZ_1G); 1034 } 1035 1036 /* 1037 * Called from fs/proc with a reference on @p to find the function 1038 * which called into schedule(). This needs to be done carefully 1039 * because the task might wake up and we might look at a stack 1040 * changing under us. 1041 */ 1042 unsigned long __get_wchan(struct task_struct *p) 1043 { 1044 struct unwind_state state; 1045 unsigned long addr = 0; 1046 1047 if (!try_get_task_stack(p)) 1048 return 0; 1049 1050 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); 1051 unwind_next_frame(&state)) { 1052 addr = unwind_get_return_address(&state); 1053 if (!addr) 1054 break; 1055 if (in_sched_functions(addr)) 1056 continue; 1057 break; 1058 } 1059 1060 put_task_stack(p); 1061 1062 return addr; 1063 } 1064 1065 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2) 1066 { 1067 switch (option) { 1068 case ARCH_GET_CPUID: 1069 return get_cpuid_mode(); 1070 case ARCH_SET_CPUID: 1071 return set_cpuid_mode(arg2); 1072 case ARCH_GET_XCOMP_SUPP: 1073 case ARCH_GET_XCOMP_PERM: 1074 case ARCH_REQ_XCOMP_PERM: 1075 case ARCH_GET_XCOMP_GUEST_PERM: 1076 case ARCH_REQ_XCOMP_GUEST_PERM: 1077 return fpu_xstate_prctl(option, arg2); 1078 } 1079 1080 if (!in_ia32_syscall()) 1081 return do_arch_prctl_64(current, option, arg2); 1082 1083 return -EINVAL; 1084 } 1085 1086 SYSCALL_DEFINE0(ni_syscall) 1087 { 1088 return -ENOSYS; 1089 } 1090