1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/errno.h> 5 #include <linux/kernel.h> 6 #include <linux/mm.h> 7 #include <linux/smp.h> 8 #include <linux/prctl.h> 9 #include <linux/slab.h> 10 #include <linux/sched.h> 11 #include <linux/sched/idle.h> 12 #include <linux/sched/debug.h> 13 #include <linux/sched/task.h> 14 #include <linux/sched/task_stack.h> 15 #include <linux/init.h> 16 #include <linux/export.h> 17 #include <linux/pm.h> 18 #include <linux/tick.h> 19 #include <linux/random.h> 20 #include <linux/user-return-notifier.h> 21 #include <linux/dmi.h> 22 #include <linux/utsname.h> 23 #include <linux/stackprotector.h> 24 #include <linux/cpuidle.h> 25 #include <linux/acpi.h> 26 #include <linux/elf-randomize.h> 27 #include <trace/events/power.h> 28 #include <linux/hw_breakpoint.h> 29 #include <asm/cpu.h> 30 #include <asm/apic.h> 31 #include <linux/uaccess.h> 32 #include <asm/mwait.h> 33 #include <asm/fpu/api.h> 34 #include <asm/fpu/sched.h> 35 #include <asm/fpu/xstate.h> 36 #include <asm/debugreg.h> 37 #include <asm/nmi.h> 38 #include <asm/tlbflush.h> 39 #include <asm/mce.h> 40 #include <asm/vm86.h> 41 #include <asm/switch_to.h> 42 #include <asm/desc.h> 43 #include <asm/prctl.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/io_bitmap.h> 46 #include <asm/proto.h> 47 #include <asm/frame.h> 48 #include <asm/unwind.h> 49 #include <asm/tdx.h> 50 51 #include "process.h" 52 53 /* 54 * per-CPU TSS segments. Threads are completely 'soft' on Linux, 55 * no more per-task TSS's. The TSS size is kept cacheline-aligned 56 * so they are allowed to end up in the .data..cacheline_aligned 57 * section. Since TSS's are completely CPU-local, we want them 58 * on exact cacheline boundaries, to eliminate cacheline ping-pong. 59 */ 60 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { 61 .x86_tss = { 62 /* 63 * .sp0 is only used when entering ring 0 from a lower 64 * privilege level. Since the init task never runs anything 65 * but ring 0 code, there is no need for a valid value here. 66 * Poison it. 67 */ 68 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, 69 70 #ifdef CONFIG_X86_32 71 .sp1 = TOP_OF_INIT_STACK, 72 73 .ss0 = __KERNEL_DS, 74 .ss1 = __KERNEL_CS, 75 #endif 76 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, 77 }, 78 }; 79 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); 80 81 DEFINE_PER_CPU(bool, __tss_limit_invalid); 82 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); 83 84 /* 85 * this gets called so that we can store lazy state into memory and copy the 86 * current task into the new thread. 87 */ 88 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 89 { 90 memcpy(dst, src, arch_task_struct_size); 91 #ifdef CONFIG_VM86 92 dst->thread.vm86 = NULL; 93 #endif 94 /* Drop the copied pointer to current's fpstate */ 95 dst->thread.fpu.fpstate = NULL; 96 97 return 0; 98 } 99 100 #ifdef CONFIG_X86_64 101 void arch_release_task_struct(struct task_struct *tsk) 102 { 103 if (fpu_state_size_dynamic()) 104 fpstate_free(&tsk->thread.fpu); 105 } 106 #endif 107 108 /* 109 * Free thread data structures etc.. 110 */ 111 void exit_thread(struct task_struct *tsk) 112 { 113 struct thread_struct *t = &tsk->thread; 114 struct fpu *fpu = &t->fpu; 115 116 if (test_thread_flag(TIF_IO_BITMAP)) 117 io_bitmap_exit(tsk); 118 119 free_vm86(t); 120 121 fpu__drop(fpu); 122 } 123 124 static int set_new_tls(struct task_struct *p, unsigned long tls) 125 { 126 struct user_desc __user *utls = (struct user_desc __user *)tls; 127 128 if (in_ia32_syscall()) 129 return do_set_thread_area(p, -1, utls, 0); 130 else 131 return do_set_thread_area_64(p, ARCH_SET_FS, tls); 132 } 133 134 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) 135 { 136 unsigned long clone_flags = args->flags; 137 unsigned long sp = args->stack; 138 unsigned long tls = args->tls; 139 struct inactive_task_frame *frame; 140 struct fork_frame *fork_frame; 141 struct pt_regs *childregs; 142 int ret = 0; 143 144 childregs = task_pt_regs(p); 145 fork_frame = container_of(childregs, struct fork_frame, regs); 146 frame = &fork_frame->frame; 147 148 frame->bp = encode_frame_pointer(childregs); 149 frame->ret_addr = (unsigned long) ret_from_fork; 150 p->thread.sp = (unsigned long) fork_frame; 151 p->thread.io_bitmap = NULL; 152 p->thread.iopl_warn = 0; 153 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 154 155 #ifdef CONFIG_X86_64 156 current_save_fsgs(); 157 p->thread.fsindex = current->thread.fsindex; 158 p->thread.fsbase = current->thread.fsbase; 159 p->thread.gsindex = current->thread.gsindex; 160 p->thread.gsbase = current->thread.gsbase; 161 162 savesegment(es, p->thread.es); 163 savesegment(ds, p->thread.ds); 164 #else 165 p->thread.sp0 = (unsigned long) (childregs + 1); 166 savesegment(gs, p->thread.gs); 167 /* 168 * Clear all status flags including IF and set fixed bit. 64bit 169 * does not have this initialization as the frame does not contain 170 * flags. The flags consistency (especially vs. AC) is there 171 * ensured via objtool, which lacks 32bit support. 172 */ 173 frame->flags = X86_EFLAGS_FIXED; 174 #endif 175 176 fpu_clone(p, clone_flags, args->fn); 177 178 /* Kernel thread ? */ 179 if (unlikely(p->flags & PF_KTHREAD)) { 180 p->thread.pkru = pkru_get_init_value(); 181 memset(childregs, 0, sizeof(struct pt_regs)); 182 kthread_frame_init(frame, args->fn, args->fn_arg); 183 return 0; 184 } 185 186 /* 187 * Clone current's PKRU value from hardware. tsk->thread.pkru 188 * is only valid when scheduled out. 189 */ 190 p->thread.pkru = read_pkru(); 191 192 frame->bx = 0; 193 *childregs = *current_pt_regs(); 194 childregs->ax = 0; 195 if (sp) 196 childregs->sp = sp; 197 198 if (unlikely(args->fn)) { 199 /* 200 * A user space thread, but it doesn't return to 201 * ret_after_fork(). 202 * 203 * In order to indicate that to tools like gdb, 204 * we reset the stack and instruction pointers. 205 * 206 * It does the same kernel frame setup to return to a kernel 207 * function that a kernel thread does. 208 */ 209 childregs->sp = 0; 210 childregs->ip = 0; 211 kthread_frame_init(frame, args->fn, args->fn_arg); 212 return 0; 213 } 214 215 /* Set a new TLS for the child thread? */ 216 if (clone_flags & CLONE_SETTLS) 217 ret = set_new_tls(p, tls); 218 219 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) 220 io_bitmap_share(p); 221 222 return ret; 223 } 224 225 static void pkru_flush_thread(void) 226 { 227 /* 228 * If PKRU is enabled the default PKRU value has to be loaded into 229 * the hardware right here (similar to context switch). 230 */ 231 pkru_write_default(); 232 } 233 234 void flush_thread(void) 235 { 236 struct task_struct *tsk = current; 237 238 flush_ptrace_hw_breakpoint(tsk); 239 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 240 241 fpu_flush_thread(); 242 pkru_flush_thread(); 243 } 244 245 void disable_TSC(void) 246 { 247 preempt_disable(); 248 if (!test_and_set_thread_flag(TIF_NOTSC)) 249 /* 250 * Must flip the CPU state synchronously with 251 * TIF_NOTSC in the current running context. 252 */ 253 cr4_set_bits(X86_CR4_TSD); 254 preempt_enable(); 255 } 256 257 static void enable_TSC(void) 258 { 259 preempt_disable(); 260 if (test_and_clear_thread_flag(TIF_NOTSC)) 261 /* 262 * Must flip the CPU state synchronously with 263 * TIF_NOTSC in the current running context. 264 */ 265 cr4_clear_bits(X86_CR4_TSD); 266 preempt_enable(); 267 } 268 269 int get_tsc_mode(unsigned long adr) 270 { 271 unsigned int val; 272 273 if (test_thread_flag(TIF_NOTSC)) 274 val = PR_TSC_SIGSEGV; 275 else 276 val = PR_TSC_ENABLE; 277 278 return put_user(val, (unsigned int __user *)adr); 279 } 280 281 int set_tsc_mode(unsigned int val) 282 { 283 if (val == PR_TSC_SIGSEGV) 284 disable_TSC(); 285 else if (val == PR_TSC_ENABLE) 286 enable_TSC(); 287 else 288 return -EINVAL; 289 290 return 0; 291 } 292 293 DEFINE_PER_CPU(u64, msr_misc_features_shadow); 294 295 static void set_cpuid_faulting(bool on) 296 { 297 u64 msrval; 298 299 msrval = this_cpu_read(msr_misc_features_shadow); 300 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 301 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 302 this_cpu_write(msr_misc_features_shadow, msrval); 303 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); 304 } 305 306 static void disable_cpuid(void) 307 { 308 preempt_disable(); 309 if (!test_and_set_thread_flag(TIF_NOCPUID)) { 310 /* 311 * Must flip the CPU state synchronously with 312 * TIF_NOCPUID in the current running context. 313 */ 314 set_cpuid_faulting(true); 315 } 316 preempt_enable(); 317 } 318 319 static void enable_cpuid(void) 320 { 321 preempt_disable(); 322 if (test_and_clear_thread_flag(TIF_NOCPUID)) { 323 /* 324 * Must flip the CPU state synchronously with 325 * TIF_NOCPUID in the current running context. 326 */ 327 set_cpuid_faulting(false); 328 } 329 preempt_enable(); 330 } 331 332 static int get_cpuid_mode(void) 333 { 334 return !test_thread_flag(TIF_NOCPUID); 335 } 336 337 static int set_cpuid_mode(unsigned long cpuid_enabled) 338 { 339 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) 340 return -ENODEV; 341 342 if (cpuid_enabled) 343 enable_cpuid(); 344 else 345 disable_cpuid(); 346 347 return 0; 348 } 349 350 /* 351 * Called immediately after a successful exec. 352 */ 353 void arch_setup_new_exec(void) 354 { 355 /* If cpuid was previously disabled for this task, re-enable it. */ 356 if (test_thread_flag(TIF_NOCPUID)) 357 enable_cpuid(); 358 359 /* 360 * Don't inherit TIF_SSBD across exec boundary when 361 * PR_SPEC_DISABLE_NOEXEC is used. 362 */ 363 if (test_thread_flag(TIF_SSBD) && 364 task_spec_ssb_noexec(current)) { 365 clear_thread_flag(TIF_SSBD); 366 task_clear_spec_ssb_disable(current); 367 task_clear_spec_ssb_noexec(current); 368 speculation_ctrl_update(read_thread_flags()); 369 } 370 } 371 372 #ifdef CONFIG_X86_IOPL_IOPERM 373 static inline void switch_to_bitmap(unsigned long tifp) 374 { 375 /* 376 * Invalidate I/O bitmap if the previous task used it. This prevents 377 * any possible leakage of an active I/O bitmap. 378 * 379 * If the next task has an I/O bitmap it will handle it on exit to 380 * user mode. 381 */ 382 if (tifp & _TIF_IO_BITMAP) 383 tss_invalidate_io_bitmap(); 384 } 385 386 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) 387 { 388 /* 389 * Copy at least the byte range of the incoming tasks bitmap which 390 * covers the permitted I/O ports. 391 * 392 * If the previous task which used an I/O bitmap had more bits 393 * permitted, then the copy needs to cover those as well so they 394 * get turned off. 395 */ 396 memcpy(tss->io_bitmap.bitmap, iobm->bitmap, 397 max(tss->io_bitmap.prev_max, iobm->max)); 398 399 /* 400 * Store the new max and the sequence number of this bitmap 401 * and a pointer to the bitmap itself. 402 */ 403 tss->io_bitmap.prev_max = iobm->max; 404 tss->io_bitmap.prev_sequence = iobm->sequence; 405 } 406 407 /** 408 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode 409 */ 410 void native_tss_update_io_bitmap(void) 411 { 412 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 413 struct thread_struct *t = ¤t->thread; 414 u16 *base = &tss->x86_tss.io_bitmap_base; 415 416 if (!test_thread_flag(TIF_IO_BITMAP)) { 417 native_tss_invalidate_io_bitmap(); 418 return; 419 } 420 421 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { 422 *base = IO_BITMAP_OFFSET_VALID_ALL; 423 } else { 424 struct io_bitmap *iobm = t->io_bitmap; 425 426 /* 427 * Only copy bitmap data when the sequence number differs. The 428 * update time is accounted to the incoming task. 429 */ 430 if (tss->io_bitmap.prev_sequence != iobm->sequence) 431 tss_copy_io_bitmap(tss, iobm); 432 433 /* Enable the bitmap */ 434 *base = IO_BITMAP_OFFSET_VALID_MAP; 435 } 436 437 /* 438 * Make sure that the TSS limit is covering the IO bitmap. It might have 439 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O 440 * access from user space to trigger a #GP because tbe bitmap is outside 441 * the TSS limit. 442 */ 443 refresh_tss_limit(); 444 } 445 #else /* CONFIG_X86_IOPL_IOPERM */ 446 static inline void switch_to_bitmap(unsigned long tifp) { } 447 #endif 448 449 #ifdef CONFIG_SMP 450 451 struct ssb_state { 452 struct ssb_state *shared_state; 453 raw_spinlock_t lock; 454 unsigned int disable_state; 455 unsigned long local_state; 456 }; 457 458 #define LSTATE_SSB 0 459 460 static DEFINE_PER_CPU(struct ssb_state, ssb_state); 461 462 void speculative_store_bypass_ht_init(void) 463 { 464 struct ssb_state *st = this_cpu_ptr(&ssb_state); 465 unsigned int this_cpu = smp_processor_id(); 466 unsigned int cpu; 467 468 st->local_state = 0; 469 470 /* 471 * Shared state setup happens once on the first bringup 472 * of the CPU. It's not destroyed on CPU hotunplug. 473 */ 474 if (st->shared_state) 475 return; 476 477 raw_spin_lock_init(&st->lock); 478 479 /* 480 * Go over HT siblings and check whether one of them has set up the 481 * shared state pointer already. 482 */ 483 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { 484 if (cpu == this_cpu) 485 continue; 486 487 if (!per_cpu(ssb_state, cpu).shared_state) 488 continue; 489 490 /* Link it to the state of the sibling: */ 491 st->shared_state = per_cpu(ssb_state, cpu).shared_state; 492 return; 493 } 494 495 /* 496 * First HT sibling to come up on the core. Link shared state of 497 * the first HT sibling to itself. The siblings on the same core 498 * which come up later will see the shared state pointer and link 499 * themselves to the state of this CPU. 500 */ 501 st->shared_state = st; 502 } 503 504 /* 505 * Logic is: First HT sibling enables SSBD for both siblings in the core 506 * and last sibling to disable it, disables it for the whole core. This how 507 * MSR_SPEC_CTRL works in "hardware": 508 * 509 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL 510 */ 511 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 512 { 513 struct ssb_state *st = this_cpu_ptr(&ssb_state); 514 u64 msr = x86_amd_ls_cfg_base; 515 516 if (!static_cpu_has(X86_FEATURE_ZEN)) { 517 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 518 wrmsrl(MSR_AMD64_LS_CFG, msr); 519 return; 520 } 521 522 if (tifn & _TIF_SSBD) { 523 /* 524 * Since this can race with prctl(), block reentry on the 525 * same CPU. 526 */ 527 if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) 528 return; 529 530 msr |= x86_amd_ls_cfg_ssbd_mask; 531 532 raw_spin_lock(&st->shared_state->lock); 533 /* First sibling enables SSBD: */ 534 if (!st->shared_state->disable_state) 535 wrmsrl(MSR_AMD64_LS_CFG, msr); 536 st->shared_state->disable_state++; 537 raw_spin_unlock(&st->shared_state->lock); 538 } else { 539 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) 540 return; 541 542 raw_spin_lock(&st->shared_state->lock); 543 st->shared_state->disable_state--; 544 if (!st->shared_state->disable_state) 545 wrmsrl(MSR_AMD64_LS_CFG, msr); 546 raw_spin_unlock(&st->shared_state->lock); 547 } 548 } 549 #else 550 static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 551 { 552 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 553 554 wrmsrl(MSR_AMD64_LS_CFG, msr); 555 } 556 #endif 557 558 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) 559 { 560 /* 561 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 562 * so ssbd_tif_to_spec_ctrl() just works. 563 */ 564 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 565 } 566 567 /* 568 * Update the MSRs managing speculation control, during context switch. 569 * 570 * tifp: Previous task's thread flags 571 * tifn: Next task's thread flags 572 */ 573 static __always_inline void __speculation_ctrl_update(unsigned long tifp, 574 unsigned long tifn) 575 { 576 unsigned long tif_diff = tifp ^ tifn; 577 u64 msr = x86_spec_ctrl_base; 578 bool updmsr = false; 579 580 lockdep_assert_irqs_disabled(); 581 582 /* Handle change of TIF_SSBD depending on the mitigation method. */ 583 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { 584 if (tif_diff & _TIF_SSBD) 585 amd_set_ssb_virt_state(tifn); 586 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { 587 if (tif_diff & _TIF_SSBD) 588 amd_set_core_ssb_state(tifn); 589 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 590 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 591 updmsr |= !!(tif_diff & _TIF_SSBD); 592 msr |= ssbd_tif_to_spec_ctrl(tifn); 593 } 594 595 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ 596 if (IS_ENABLED(CONFIG_SMP) && 597 static_branch_unlikely(&switch_to_cond_stibp)) { 598 updmsr |= !!(tif_diff & _TIF_SPEC_IB); 599 msr |= stibp_tif_to_spec_ctrl(tifn); 600 } 601 602 if (updmsr) 603 write_spec_ctrl_current(msr, false); 604 } 605 606 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) 607 { 608 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { 609 if (task_spec_ssb_disable(tsk)) 610 set_tsk_thread_flag(tsk, TIF_SSBD); 611 else 612 clear_tsk_thread_flag(tsk, TIF_SSBD); 613 614 if (task_spec_ib_disable(tsk)) 615 set_tsk_thread_flag(tsk, TIF_SPEC_IB); 616 else 617 clear_tsk_thread_flag(tsk, TIF_SPEC_IB); 618 } 619 /* Return the updated threadinfo flags*/ 620 return read_task_thread_flags(tsk); 621 } 622 623 void speculation_ctrl_update(unsigned long tif) 624 { 625 unsigned long flags; 626 627 /* Forced update. Make sure all relevant TIF flags are different */ 628 local_irq_save(flags); 629 __speculation_ctrl_update(~tif, tif); 630 local_irq_restore(flags); 631 } 632 633 /* Called from seccomp/prctl update */ 634 void speculation_ctrl_update_current(void) 635 { 636 preempt_disable(); 637 speculation_ctrl_update(speculation_ctrl_update_tif(current)); 638 preempt_enable(); 639 } 640 641 static inline void cr4_toggle_bits_irqsoff(unsigned long mask) 642 { 643 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 644 645 newval = cr4 ^ mask; 646 if (newval != cr4) { 647 this_cpu_write(cpu_tlbstate.cr4, newval); 648 __write_cr4(newval); 649 } 650 } 651 652 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) 653 { 654 unsigned long tifp, tifn; 655 656 tifn = read_task_thread_flags(next_p); 657 tifp = read_task_thread_flags(prev_p); 658 659 switch_to_bitmap(tifp); 660 661 propagate_user_return_notify(prev_p, next_p); 662 663 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && 664 arch_has_block_step()) { 665 unsigned long debugctl, msk; 666 667 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 668 debugctl &= ~DEBUGCTLMSR_BTF; 669 msk = tifn & _TIF_BLOCKSTEP; 670 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 671 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 672 } 673 674 if ((tifp ^ tifn) & _TIF_NOTSC) 675 cr4_toggle_bits_irqsoff(X86_CR4_TSD); 676 677 if ((tifp ^ tifn) & _TIF_NOCPUID) 678 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); 679 680 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { 681 __speculation_ctrl_update(tifp, tifn); 682 } else { 683 speculation_ctrl_update_tif(prev_p); 684 tifn = speculation_ctrl_update_tif(next_p); 685 686 /* Enforce MSR update to ensure consistent state */ 687 __speculation_ctrl_update(~tifn, tifn); 688 } 689 } 690 691 /* 692 * Idle related variables and functions 693 */ 694 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; 695 EXPORT_SYMBOL(boot_option_idle_override); 696 697 static void (*x86_idle)(void); 698 699 #ifndef CONFIG_SMP 700 static inline void play_dead(void) 701 { 702 BUG(); 703 } 704 #endif 705 706 void arch_cpu_idle_enter(void) 707 { 708 tsc_verify_tsc_adjust(false); 709 local_touch_nmi(); 710 } 711 712 void arch_cpu_idle_dead(void) 713 { 714 play_dead(); 715 } 716 717 /* 718 * Called from the generic idle code. 719 */ 720 void arch_cpu_idle(void) 721 { 722 x86_idle(); 723 } 724 725 /* 726 * We use this if we don't have any better idle routine.. 727 */ 728 void __cpuidle default_idle(void) 729 { 730 raw_safe_halt(); 731 } 732 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) 733 EXPORT_SYMBOL(default_idle); 734 #endif 735 736 #ifdef CONFIG_XEN 737 bool xen_set_default_idle(void) 738 { 739 bool ret = !!x86_idle; 740 741 x86_idle = default_idle; 742 743 return ret; 744 } 745 #endif 746 747 void __noreturn stop_this_cpu(void *dummy) 748 { 749 local_irq_disable(); 750 /* 751 * Remove this CPU: 752 */ 753 set_cpu_online(smp_processor_id(), false); 754 disable_local_APIC(); 755 mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); 756 757 /* 758 * Use wbinvd on processors that support SME. This provides support 759 * for performing a successful kexec when going from SME inactive 760 * to SME active (or vice-versa). The cache must be cleared so that 761 * if there are entries with the same physical address, both with and 762 * without the encryption bit, they don't race each other when flushed 763 * and potentially end up with the wrong entry being committed to 764 * memory. 765 * 766 * Test the CPUID bit directly because the machine might've cleared 767 * X86_FEATURE_SME due to cmdline options. 768 */ 769 if (cpuid_eax(0x8000001f) & BIT(0)) 770 native_wbinvd(); 771 for (;;) { 772 /* 773 * Use native_halt() so that memory contents don't change 774 * (stack usage and variables) after possibly issuing the 775 * native_wbinvd() above. 776 */ 777 native_halt(); 778 } 779 } 780 781 /* 782 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power 783 * states (local apic timer and TSC stop). 784 * 785 * XXX this function is completely buggered vs RCU and tracing. 786 */ 787 static void amd_e400_idle(void) 788 { 789 /* 790 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E 791 * gets set after static_cpu_has() places have been converted via 792 * alternatives. 793 */ 794 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 795 default_idle(); 796 return; 797 } 798 799 tick_broadcast_enter(); 800 801 default_idle(); 802 803 /* 804 * The switch back from broadcast mode needs to be called with 805 * interrupts disabled. 806 */ 807 raw_local_irq_disable(); 808 tick_broadcast_exit(); 809 raw_local_irq_enable(); 810 } 811 812 /* 813 * Intel Core2 and older machines prefer MWAIT over HALT for C1. 814 * We can't rely on cpuidle installing MWAIT, because it will not load 815 * on systems that support only C1 -- so the boot default must be MWAIT. 816 * 817 * Some AMD machines are the opposite, they depend on using HALT. 818 * 819 * So for default C1, which is used during boot until cpuidle loads, 820 * use MWAIT-C1 on Intel HW that has it, else use HALT. 821 */ 822 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) 823 { 824 if (c->x86_vendor != X86_VENDOR_INTEL) 825 return 0; 826 827 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) 828 return 0; 829 830 return 1; 831 } 832 833 /* 834 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT 835 * with interrupts enabled and no flags, which is backwards compatible with the 836 * original MWAIT implementation. 837 */ 838 static __cpuidle void mwait_idle(void) 839 { 840 if (!current_set_polling_and_test()) { 841 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { 842 mb(); /* quirk */ 843 clflush((void *)¤t_thread_info()->flags); 844 mb(); /* quirk */ 845 } 846 847 __monitor((void *)¤t_thread_info()->flags, 0, 0); 848 if (!need_resched()) 849 __sti_mwait(0, 0); 850 else 851 raw_local_irq_enable(); 852 } else { 853 raw_local_irq_enable(); 854 } 855 __current_clr_polling(); 856 } 857 858 void select_idle_routine(const struct cpuinfo_x86 *c) 859 { 860 #ifdef CONFIG_SMP 861 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) 862 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); 863 #endif 864 if (x86_idle || boot_option_idle_override == IDLE_POLL) 865 return; 866 867 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { 868 pr_info("using AMD E400 aware idle routine\n"); 869 x86_idle = amd_e400_idle; 870 } else if (prefer_mwait_c1_over_halt(c)) { 871 pr_info("using mwait in idle threads\n"); 872 x86_idle = mwait_idle; 873 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { 874 pr_info("using TDX aware idle routine\n"); 875 x86_idle = tdx_safe_halt; 876 } else 877 x86_idle = default_idle; 878 } 879 880 void amd_e400_c1e_apic_setup(void) 881 { 882 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { 883 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); 884 local_irq_disable(); 885 tick_broadcast_force(); 886 local_irq_enable(); 887 } 888 } 889 890 void __init arch_post_acpi_subsys_init(void) 891 { 892 u32 lo, hi; 893 894 if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) 895 return; 896 897 /* 898 * AMD E400 detection needs to happen after ACPI has been enabled. If 899 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in 900 * MSR_K8_INT_PENDING_MSG. 901 */ 902 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 903 if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) 904 return; 905 906 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); 907 908 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) 909 mark_tsc_unstable("TSC halt in AMD C1E"); 910 pr_info("System has AMD C1E enabled\n"); 911 } 912 913 static int __init idle_setup(char *str) 914 { 915 if (!str) 916 return -EINVAL; 917 918 if (!strcmp(str, "poll")) { 919 pr_info("using polling idle threads\n"); 920 boot_option_idle_override = IDLE_POLL; 921 cpu_idle_poll_ctrl(true); 922 } else if (!strcmp(str, "halt")) { 923 /* 924 * When the boot option of idle=halt is added, halt is 925 * forced to be used for CPU idle. In such case CPU C2/C3 926 * won't be used again. 927 * To continue to load the CPU idle driver, don't touch 928 * the boot_option_idle_override. 929 */ 930 x86_idle = default_idle; 931 boot_option_idle_override = IDLE_HALT; 932 } else if (!strcmp(str, "nomwait")) { 933 /* 934 * If the boot option of "idle=nomwait" is added, 935 * it means that mwait will be disabled for CPU C2/C3 936 * states. In such case it won't touch the variable 937 * of boot_option_idle_override. 938 */ 939 boot_option_idle_override = IDLE_NOMWAIT; 940 } else 941 return -1; 942 943 return 0; 944 } 945 early_param("idle", idle_setup); 946 947 unsigned long arch_align_stack(unsigned long sp) 948 { 949 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 950 sp -= get_random_int() % 8192; 951 return sp & ~0xf; 952 } 953 954 unsigned long arch_randomize_brk(struct mm_struct *mm) 955 { 956 return randomize_page(mm->brk, 0x02000000); 957 } 958 959 /* 960 * Called from fs/proc with a reference on @p to find the function 961 * which called into schedule(). This needs to be done carefully 962 * because the task might wake up and we might look at a stack 963 * changing under us. 964 */ 965 unsigned long __get_wchan(struct task_struct *p) 966 { 967 struct unwind_state state; 968 unsigned long addr = 0; 969 970 if (!try_get_task_stack(p)) 971 return 0; 972 973 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); 974 unwind_next_frame(&state)) { 975 addr = unwind_get_return_address(&state); 976 if (!addr) 977 break; 978 if (in_sched_functions(addr)) 979 continue; 980 break; 981 } 982 983 put_task_stack(p); 984 985 return addr; 986 } 987 988 long do_arch_prctl_common(int option, unsigned long arg2) 989 { 990 switch (option) { 991 case ARCH_GET_CPUID: 992 return get_cpuid_mode(); 993 case ARCH_SET_CPUID: 994 return set_cpuid_mode(arg2); 995 case ARCH_GET_XCOMP_SUPP: 996 case ARCH_GET_XCOMP_PERM: 997 case ARCH_REQ_XCOMP_PERM: 998 case ARCH_GET_XCOMP_GUEST_PERM: 999 case ARCH_REQ_XCOMP_GUEST_PERM: 1000 return fpu_xstate_prctl(option, arg2); 1001 } 1002 1003 return -EINVAL; 1004 } 1005