1 /* 2 * Common interrupt code for 32 and 64 bit 3 */ 4 #include <linux/cpu.h> 5 #include <linux/interrupt.h> 6 #include <linux/kernel_stat.h> 7 #include <linux/of.h> 8 #include <linux/seq_file.h> 9 #include <linux/smp.h> 10 #include <linux/ftrace.h> 11 #include <linux/delay.h> 12 13 #include <asm/apic.h> 14 #include <asm/io_apic.h> 15 #include <asm/irq.h> 16 #include <asm/idle.h> 17 #include <asm/mce.h> 18 #include <asm/hw_irq.h> 19 20 atomic_t irq_err_count; 21 22 /* Function pointer for generic interrupt vector handling */ 23 void (*x86_platform_ipi_callback)(void) = NULL; 24 25 /* 26 * 'what should we do if we get a hw irq event on an illegal vector'. 27 * each architecture has to answer this themselves. 28 */ 29 void ack_bad_irq(unsigned int irq) 30 { 31 if (printk_ratelimit()) 32 pr_err("unexpected IRQ trap at vector %02x\n", irq); 33 34 /* 35 * Currently unexpected vectors happen only on SMP and APIC. 36 * We _must_ ack these because every local APIC has only N 37 * irq slots per priority level, and a 'hanging, unacked' IRQ 38 * holds up an irq slot - in excessive cases (when multiple 39 * unexpected vectors occur) that might lock up the APIC 40 * completely. 41 * But only ack when the APIC is enabled -AK 42 */ 43 ack_APIC_irq(); 44 } 45 46 #define irq_stats(x) (&per_cpu(irq_stat, x)) 47 /* 48 * /proc/interrupts printing for arch specific interrupts 49 */ 50 int arch_show_interrupts(struct seq_file *p, int prec) 51 { 52 int j; 53 54 seq_printf(p, "%*s: ", prec, "NMI"); 55 for_each_online_cpu(j) 56 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); 57 seq_printf(p, " Non-maskable interrupts\n"); 58 #ifdef CONFIG_X86_LOCAL_APIC 59 seq_printf(p, "%*s: ", prec, "LOC"); 60 for_each_online_cpu(j) 61 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); 62 seq_printf(p, " Local timer interrupts\n"); 63 64 seq_printf(p, "%*s: ", prec, "SPU"); 65 for_each_online_cpu(j) 66 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); 67 seq_printf(p, " Spurious interrupts\n"); 68 seq_printf(p, "%*s: ", prec, "PMI"); 69 for_each_online_cpu(j) 70 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); 71 seq_printf(p, " Performance monitoring interrupts\n"); 72 seq_printf(p, "%*s: ", prec, "IWI"); 73 for_each_online_cpu(j) 74 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs); 75 seq_printf(p, " IRQ work interrupts\n"); 76 #endif 77 if (x86_platform_ipi_callback) { 78 seq_printf(p, "%*s: ", prec, "PLT"); 79 for_each_online_cpu(j) 80 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis); 81 seq_printf(p, " Platform interrupts\n"); 82 } 83 #ifdef CONFIG_SMP 84 seq_printf(p, "%*s: ", prec, "RES"); 85 for_each_online_cpu(j) 86 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); 87 seq_printf(p, " Rescheduling interrupts\n"); 88 seq_printf(p, "%*s: ", prec, "CAL"); 89 for_each_online_cpu(j) 90 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); 91 seq_printf(p, " Function call interrupts\n"); 92 seq_printf(p, "%*s: ", prec, "TLB"); 93 for_each_online_cpu(j) 94 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); 95 seq_printf(p, " TLB shootdowns\n"); 96 #endif 97 #ifdef CONFIG_X86_THERMAL_VECTOR 98 seq_printf(p, "%*s: ", prec, "TRM"); 99 for_each_online_cpu(j) 100 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); 101 seq_printf(p, " Thermal event interrupts\n"); 102 #endif 103 #ifdef CONFIG_X86_MCE_THRESHOLD 104 seq_printf(p, "%*s: ", prec, "THR"); 105 for_each_online_cpu(j) 106 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); 107 seq_printf(p, " Threshold APIC interrupts\n"); 108 #endif 109 #ifdef CONFIG_X86_MCE 110 seq_printf(p, "%*s: ", prec, "MCE"); 111 for_each_online_cpu(j) 112 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); 113 seq_printf(p, " Machine check exceptions\n"); 114 seq_printf(p, "%*s: ", prec, "MCP"); 115 for_each_online_cpu(j) 116 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j)); 117 seq_printf(p, " Machine check polls\n"); 118 #endif 119 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); 120 #if defined(CONFIG_X86_IO_APIC) 121 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); 122 #endif 123 return 0; 124 } 125 126 /* 127 * /proc/stat helpers 128 */ 129 u64 arch_irq_stat_cpu(unsigned int cpu) 130 { 131 u64 sum = irq_stats(cpu)->__nmi_count; 132 133 #ifdef CONFIG_X86_LOCAL_APIC 134 sum += irq_stats(cpu)->apic_timer_irqs; 135 sum += irq_stats(cpu)->irq_spurious_count; 136 sum += irq_stats(cpu)->apic_perf_irqs; 137 sum += irq_stats(cpu)->apic_irq_work_irqs; 138 #endif 139 if (x86_platform_ipi_callback) 140 sum += irq_stats(cpu)->x86_platform_ipis; 141 #ifdef CONFIG_SMP 142 sum += irq_stats(cpu)->irq_resched_count; 143 sum += irq_stats(cpu)->irq_call_count; 144 sum += irq_stats(cpu)->irq_tlb_count; 145 #endif 146 #ifdef CONFIG_X86_THERMAL_VECTOR 147 sum += irq_stats(cpu)->irq_thermal_count; 148 #endif 149 #ifdef CONFIG_X86_MCE_THRESHOLD 150 sum += irq_stats(cpu)->irq_threshold_count; 151 #endif 152 #ifdef CONFIG_X86_MCE 153 sum += per_cpu(mce_exception_count, cpu); 154 sum += per_cpu(mce_poll_count, cpu); 155 #endif 156 return sum; 157 } 158 159 u64 arch_irq_stat(void) 160 { 161 u64 sum = atomic_read(&irq_err_count); 162 163 #ifdef CONFIG_X86_IO_APIC 164 sum += atomic_read(&irq_mis_count); 165 #endif 166 return sum; 167 } 168 169 170 /* 171 * do_IRQ handles all normal device IRQ's (the special 172 * SMP cross-CPU interrupts have their own specific 173 * handlers). 174 */ 175 unsigned int __irq_entry do_IRQ(struct pt_regs *regs) 176 { 177 struct pt_regs *old_regs = set_irq_regs(regs); 178 179 /* high bit used in ret_from_ code */ 180 unsigned vector = ~regs->orig_ax; 181 unsigned irq; 182 183 exit_idle(); 184 irq_enter(); 185 186 irq = __this_cpu_read(vector_irq[vector]); 187 188 if (!handle_irq(irq, regs)) { 189 ack_APIC_irq(); 190 191 if (printk_ratelimit()) 192 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n", 193 __func__, smp_processor_id(), vector, irq); 194 } 195 196 irq_exit(); 197 198 set_irq_regs(old_regs); 199 return 1; 200 } 201 202 /* 203 * Handler for X86_PLATFORM_IPI_VECTOR. 204 */ 205 void smp_x86_platform_ipi(struct pt_regs *regs) 206 { 207 struct pt_regs *old_regs = set_irq_regs(regs); 208 209 ack_APIC_irq(); 210 211 exit_idle(); 212 213 irq_enter(); 214 215 inc_irq_stat(x86_platform_ipis); 216 217 if (x86_platform_ipi_callback) 218 x86_platform_ipi_callback(); 219 220 irq_exit(); 221 222 set_irq_regs(old_regs); 223 } 224 225 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); 226 227 #ifdef CONFIG_HOTPLUG_CPU 228 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ 229 void fixup_irqs(void) 230 { 231 unsigned int irq, vector; 232 static int warned; 233 struct irq_desc *desc; 234 struct irq_data *data; 235 struct irq_chip *chip; 236 237 for_each_irq_desc(irq, desc) { 238 int break_affinity = 0; 239 int set_affinity = 1; 240 const struct cpumask *affinity; 241 242 if (!desc) 243 continue; 244 if (irq == 2) 245 continue; 246 247 /* interrupt's are disabled at this point */ 248 raw_spin_lock(&desc->lock); 249 250 data = irq_desc_get_irq_data(desc); 251 affinity = data->affinity; 252 if (!irq_has_action(irq) || irqd_is_per_cpu(data) || 253 cpumask_subset(affinity, cpu_online_mask)) { 254 raw_spin_unlock(&desc->lock); 255 continue; 256 } 257 258 /* 259 * Complete the irq move. This cpu is going down and for 260 * non intr-remapping case, we can't wait till this interrupt 261 * arrives at this cpu before completing the irq move. 262 */ 263 irq_force_complete_move(irq); 264 265 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { 266 break_affinity = 1; 267 affinity = cpu_all_mask; 268 } 269 270 chip = irq_data_get_irq_chip(data); 271 if (!irqd_can_move_in_process_context(data) && chip->irq_mask) 272 chip->irq_mask(data); 273 274 if (chip->irq_set_affinity) 275 chip->irq_set_affinity(data, affinity, true); 276 else if (!(warned++)) 277 set_affinity = 0; 278 279 if (!irqd_can_move_in_process_context(data) && 280 !irqd_irq_disabled(data) && chip->irq_unmask) 281 chip->irq_unmask(data); 282 283 raw_spin_unlock(&desc->lock); 284 285 if (break_affinity && set_affinity) 286 printk("Broke affinity for irq %i\n", irq); 287 else if (!set_affinity) 288 printk("Cannot set affinity for irq %i\n", irq); 289 } 290 291 /* 292 * We can remove mdelay() and then send spuriuous interrupts to 293 * new cpu targets for all the irqs that were handled previously by 294 * this cpu. While it works, I have seen spurious interrupt messages 295 * (nothing wrong but still...). 296 * 297 * So for now, retain mdelay(1) and check the IRR and then send those 298 * interrupts to new targets as this cpu is already offlined... 299 */ 300 mdelay(1); 301 302 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 303 unsigned int irr; 304 305 if (__this_cpu_read(vector_irq[vector]) < 0) 306 continue; 307 308 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 309 if (irr & (1 << (vector % 32))) { 310 irq = __this_cpu_read(vector_irq[vector]); 311 312 desc = irq_to_desc(irq); 313 data = irq_desc_get_irq_data(desc); 314 chip = irq_data_get_irq_chip(data); 315 raw_spin_lock(&desc->lock); 316 if (chip->irq_retrigger) 317 chip->irq_retrigger(data); 318 raw_spin_unlock(&desc->lock); 319 } 320 } 321 } 322 #endif 323