1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/linkage.h> 3 #include <linux/errno.h> 4 #include <linux/signal.h> 5 #include <linux/sched.h> 6 #include <linux/ioport.h> 7 #include <linux/interrupt.h> 8 #include <linux/irq.h> 9 #include <linux/timex.h> 10 #include <linux/random.h> 11 #include <linux/init.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/syscore_ops.h> 14 #include <linux/bitops.h> 15 #include <linux/acpi.h> 16 #include <linux/io.h> 17 #include <linux/delay.h> 18 #include <linux/pgtable.h> 19 20 #include <linux/atomic.h> 21 #include <asm/timer.h> 22 #include <asm/hw_irq.h> 23 #include <asm/desc.h> 24 #include <asm/apic.h> 25 #include <asm/i8259.h> 26 #include <asm/io_apic.h> 27 28 /* 29 * This is the 'legacy' 8259A Programmable Interrupt Controller, 30 * present in the majority of PC/AT boxes. 31 * plus some generic x86 specific things if generic specifics makes 32 * any sense at all. 33 */ 34 static void init_8259A(int auto_eoi); 35 36 static bool pcat_compat __ro_after_init; 37 static int i8259A_auto_eoi; 38 DEFINE_RAW_SPINLOCK(i8259A_lock); 39 40 /* 41 * 8259A PIC functions to handle ISA devices: 42 */ 43 44 /* 45 * This contains the irq mask for both 8259A irq controllers, 46 */ 47 unsigned int cached_irq_mask = 0xffff; 48 49 /* 50 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older) 51 * boards the timer interrupt is not really connected to any IO-APIC pin, 52 * it's fed to the master 8259A's IR0 line only. 53 * 54 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC. 55 * this 'mixed mode' IRQ handling costs nothing because it's only used 56 * at IRQ setup time. 57 */ 58 unsigned long io_apic_irqs; 59 60 static void mask_8259A_irq(unsigned int irq) 61 { 62 unsigned int mask = 1 << irq; 63 unsigned long flags; 64 65 raw_spin_lock_irqsave(&i8259A_lock, flags); 66 cached_irq_mask |= mask; 67 if (irq & 8) 68 outb(cached_slave_mask, PIC_SLAVE_IMR); 69 else 70 outb(cached_master_mask, PIC_MASTER_IMR); 71 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 72 } 73 74 static void disable_8259A_irq(struct irq_data *data) 75 { 76 mask_8259A_irq(data->irq); 77 } 78 79 static void unmask_8259A_irq(unsigned int irq) 80 { 81 unsigned int mask = ~(1 << irq); 82 unsigned long flags; 83 84 raw_spin_lock_irqsave(&i8259A_lock, flags); 85 cached_irq_mask &= mask; 86 if (irq & 8) 87 outb(cached_slave_mask, PIC_SLAVE_IMR); 88 else 89 outb(cached_master_mask, PIC_MASTER_IMR); 90 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 91 } 92 93 static void enable_8259A_irq(struct irq_data *data) 94 { 95 unmask_8259A_irq(data->irq); 96 } 97 98 static int i8259A_irq_pending(unsigned int irq) 99 { 100 unsigned int mask = 1<<irq; 101 unsigned long flags; 102 int ret; 103 104 raw_spin_lock_irqsave(&i8259A_lock, flags); 105 if (irq < 8) 106 ret = inb(PIC_MASTER_CMD) & mask; 107 else 108 ret = inb(PIC_SLAVE_CMD) & (mask >> 8); 109 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 110 111 return ret; 112 } 113 114 static void make_8259A_irq(unsigned int irq) 115 { 116 disable_irq_nosync(irq); 117 io_apic_irqs &= ~(1<<irq); 118 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); 119 irq_set_status_flags(irq, IRQ_LEVEL); 120 enable_irq(irq); 121 lapic_assign_legacy_vector(irq, true); 122 } 123 124 /* 125 * This function assumes to be called rarely. Switching between 126 * 8259A registers is slow. 127 * This has to be protected by the irq controller spinlock 128 * before being called. 129 */ 130 static inline int i8259A_irq_real(unsigned int irq) 131 { 132 int value; 133 int irqmask = 1<<irq; 134 135 if (irq < 8) { 136 outb(0x0B, PIC_MASTER_CMD); /* ISR register */ 137 value = inb(PIC_MASTER_CMD) & irqmask; 138 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ 139 return value; 140 } 141 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ 142 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); 143 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ 144 return value; 145 } 146 147 /* 148 * Careful! The 8259A is a fragile beast, it pretty 149 * much _has_ to be done exactly like this (mask it 150 * first, _then_ send the EOI, and the order of EOI 151 * to the two 8259s is important! 152 */ 153 static void mask_and_ack_8259A(struct irq_data *data) 154 { 155 unsigned int irq = data->irq; 156 unsigned int irqmask = 1 << irq; 157 unsigned long flags; 158 159 raw_spin_lock_irqsave(&i8259A_lock, flags); 160 /* 161 * Lightweight spurious IRQ detection. We do not want 162 * to overdo spurious IRQ handling - it's usually a sign 163 * of hardware problems, so we only do the checks we can 164 * do without slowing down good hardware unnecessarily. 165 * 166 * Note that IRQ7 and IRQ15 (the two spurious IRQs 167 * usually resulting from the 8259A-1|2 PICs) occur 168 * even if the IRQ is masked in the 8259A. Thus we 169 * can check spurious 8259A IRQs without doing the 170 * quite slow i8259A_irq_real() call for every IRQ. 171 * This does not cover 100% of spurious interrupts, 172 * but should be enough to warn the user that there 173 * is something bad going on ... 174 */ 175 if (cached_irq_mask & irqmask) 176 goto spurious_8259A_irq; 177 cached_irq_mask |= irqmask; 178 179 handle_real_irq: 180 if (irq & 8) { 181 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ 182 outb(cached_slave_mask, PIC_SLAVE_IMR); 183 /* 'Specific EOI' to slave */ 184 outb(0x60+(irq&7), PIC_SLAVE_CMD); 185 /* 'Specific EOI' to master-IRQ2 */ 186 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); 187 } else { 188 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 189 outb(cached_master_mask, PIC_MASTER_IMR); 190 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ 191 } 192 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 193 return; 194 195 spurious_8259A_irq: 196 /* 197 * this is the slow path - should happen rarely. 198 */ 199 if (i8259A_irq_real(irq)) 200 /* 201 * oops, the IRQ _is_ in service according to the 202 * 8259A - not spurious, go handle it. 203 */ 204 goto handle_real_irq; 205 206 { 207 static int spurious_irq_mask; 208 /* 209 * At this point we can be sure the IRQ is spurious, 210 * lets ACK and report it. [once per IRQ] 211 */ 212 if (!(spurious_irq_mask & irqmask)) { 213 printk_deferred(KERN_DEBUG 214 "spurious 8259A interrupt: IRQ%d.\n", irq); 215 spurious_irq_mask |= irqmask; 216 } 217 atomic_inc(&irq_err_count); 218 /* 219 * Theoretically we do not have to handle this IRQ, 220 * but in Linux this does not cause problems and is 221 * simpler for us. 222 */ 223 goto handle_real_irq; 224 } 225 } 226 227 struct irq_chip i8259A_chip = { 228 .name = "XT-PIC", 229 .irq_mask = disable_8259A_irq, 230 .irq_disable = disable_8259A_irq, 231 .irq_unmask = enable_8259A_irq, 232 .irq_mask_ack = mask_and_ack_8259A, 233 }; 234 235 static char irq_trigger[2]; 236 /* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ */ 237 static void restore_ELCR(char *trigger) 238 { 239 outb(trigger[0], PIC_ELCR1); 240 outb(trigger[1], PIC_ELCR2); 241 } 242 243 static void save_ELCR(char *trigger) 244 { 245 /* IRQ 0,1,2,8,13 are marked as reserved */ 246 trigger[0] = inb(PIC_ELCR1) & 0xF8; 247 trigger[1] = inb(PIC_ELCR2) & 0xDE; 248 } 249 250 static void i8259A_resume(void *data) 251 { 252 init_8259A(i8259A_auto_eoi); 253 restore_ELCR(irq_trigger); 254 } 255 256 static int i8259A_suspend(void *data) 257 { 258 save_ELCR(irq_trigger); 259 return 0; 260 } 261 262 static void i8259A_shutdown(void *data) 263 { 264 /* Put the i8259A into a quiescent state that 265 * the kernel initialization code can get it 266 * out of. 267 */ 268 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 269 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 270 } 271 272 static const struct syscore_ops i8259_syscore_ops = { 273 .suspend = i8259A_suspend, 274 .resume = i8259A_resume, 275 .shutdown = i8259A_shutdown, 276 }; 277 278 static struct syscore i8259_syscore = { 279 .ops = &i8259_syscore_ops, 280 }; 281 282 static void mask_8259A(void) 283 { 284 unsigned long flags; 285 286 raw_spin_lock_irqsave(&i8259A_lock, flags); 287 288 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 289 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 290 291 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 292 } 293 294 static void unmask_8259A(void) 295 { 296 unsigned long flags; 297 298 raw_spin_lock_irqsave(&i8259A_lock, flags); 299 300 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ 301 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ 302 303 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 304 } 305 306 static int probe_8259A(void) 307 { 308 unsigned char new_val, probe_val = ~(1 << PIC_CASCADE_IR); 309 unsigned long flags; 310 311 /* 312 * If MADT has the PCAT_COMPAT flag set, then do not bother probing 313 * for the PIC. Some BIOSes leave the PIC uninitialized and probing 314 * fails. 315 * 316 * Right now this causes problems as quite some code depends on 317 * nr_legacy_irqs() > 0 or has_legacy_pic() == true. This is silly 318 * when the system has an IO/APIC because then PIC is not required 319 * at all, except for really old machines where the timer interrupt 320 * must be routed through the PIC. So just pretend that the PIC is 321 * there and let legacy_pic->init() initialize it for nothing. 322 * 323 * Alternatively this could just try to initialize the PIC and 324 * repeat the probe, but for cases where there is no PIC that's 325 * just pointless. 326 */ 327 if (pcat_compat) 328 return nr_legacy_irqs(); 329 330 /* 331 * Check to see if we have a PIC. Mask all except the cascade and 332 * read back the value we just wrote. If we don't have a PIC, we 333 * will read 0xff as opposed to the value we wrote. 334 */ 335 raw_spin_lock_irqsave(&i8259A_lock, flags); 336 337 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 338 outb(probe_val, PIC_MASTER_IMR); 339 new_val = inb(PIC_MASTER_IMR); 340 if (new_val != probe_val) { 341 printk(KERN_INFO "Using NULL legacy PIC\n"); 342 legacy_pic = &null_legacy_pic; 343 } 344 345 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 346 return nr_legacy_irqs(); 347 } 348 349 static void init_8259A(int auto_eoi) 350 { 351 unsigned long flags; 352 353 i8259A_auto_eoi = auto_eoi; 354 355 raw_spin_lock_irqsave(&i8259A_lock, flags); 356 357 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 358 359 /* 360 * outb_pic - this has to work on a wide range of PC hardware. 361 */ 362 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ 363 364 /* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */ 365 outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR); 366 367 /* 8259A-1 (the master) has a slave on IR2 */ 368 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); 369 370 if (auto_eoi) /* master does Auto EOI */ 371 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); 372 else /* master expects normal EOI */ 373 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); 374 375 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ 376 377 /* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */ 378 outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR); 379 /* 8259A-2 is a slave on master's IR2 */ 380 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); 381 /* (slave's support for AEOI in flat mode is to be investigated) */ 382 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); 383 384 if (auto_eoi) 385 /* 386 * In AEOI mode we just have to mask the interrupt 387 * when acking. 388 */ 389 i8259A_chip.irq_mask_ack = disable_8259A_irq; 390 else 391 i8259A_chip.irq_mask_ack = mask_and_ack_8259A; 392 393 udelay(100); /* wait for 8259A to initialize */ 394 395 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ 396 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ 397 398 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 399 } 400 401 /* 402 * make i8259 a driver so that we can select pic functions at run time. the goal 403 * is to make x86 binary compatible among pc compatible and non-pc compatible 404 * platforms, such as x86 MID. 405 */ 406 407 static void legacy_pic_noop(void) { }; 408 static void legacy_pic_uint_noop(unsigned int unused) { }; 409 static void legacy_pic_int_noop(int unused) { }; 410 static int legacy_pic_irq_pending_noop(unsigned int irq) 411 { 412 return 0; 413 } 414 static int legacy_pic_probe(void) 415 { 416 return 0; 417 } 418 419 struct legacy_pic null_legacy_pic = { 420 .nr_legacy_irqs = 0, 421 .chip = &dummy_irq_chip, 422 .mask = legacy_pic_uint_noop, 423 .unmask = legacy_pic_uint_noop, 424 .mask_all = legacy_pic_noop, 425 .restore_mask = legacy_pic_noop, 426 .init = legacy_pic_int_noop, 427 .probe = legacy_pic_probe, 428 .irq_pending = legacy_pic_irq_pending_noop, 429 .make_irq = legacy_pic_uint_noop, 430 }; 431 432 static struct legacy_pic default_legacy_pic = { 433 .nr_legacy_irqs = NR_IRQS_LEGACY, 434 .chip = &i8259A_chip, 435 .mask = mask_8259A_irq, 436 .unmask = unmask_8259A_irq, 437 .mask_all = mask_8259A, 438 .restore_mask = unmask_8259A, 439 .init = init_8259A, 440 .probe = probe_8259A, 441 .irq_pending = i8259A_irq_pending, 442 .make_irq = make_8259A_irq, 443 }; 444 445 struct legacy_pic *legacy_pic = &default_legacy_pic; 446 EXPORT_SYMBOL(legacy_pic); 447 448 static int __init i8259A_init_ops(void) 449 { 450 if (legacy_pic == &default_legacy_pic) 451 register_syscore(&i8259_syscore); 452 453 return 0; 454 } 455 device_initcall(i8259A_init_ops); 456 457 void __init legacy_pic_pcat_compat(void) 458 { 459 pcat_compat = true; 460 } 461