1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/sysdev.h> 5 #include <linux/delay.h> 6 #include <linux/errno.h> 7 #include <linux/slab.h> 8 #include <linux/hpet.h> 9 #include <linux/init.h> 10 #include <linux/cpu.h> 11 #include <linux/pm.h> 12 #include <linux/io.h> 13 14 #include <asm/fixmap.h> 15 #include <asm/i8253.h> 16 #include <asm/hpet.h> 17 18 #define HPET_MASK CLOCKSOURCE_MASK(32) 19 20 /* FSEC = 10^-15 21 NSEC = 10^-9 */ 22 #define FSEC_PER_NSEC 1000000L 23 24 #define HPET_DEV_USED_BIT 2 25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 26 #define HPET_DEV_VALID 0x8 27 #define HPET_DEV_FSB_CAP 0x1000 28 #define HPET_DEV_PERI_CAP 0x2000 29 30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) 31 32 /* 33 * HPET address is set in acpi/boot.c, when an ACPI entry exists 34 */ 35 unsigned long hpet_address; 36 u8 hpet_blockid; /* OS timer block num */ 37 u8 hpet_msi_disable; 38 39 #ifdef CONFIG_PCI_MSI 40 static unsigned long hpet_num_timers; 41 #endif 42 static void __iomem *hpet_virt_address; 43 44 struct hpet_dev { 45 struct clock_event_device evt; 46 unsigned int num; 47 int cpu; 48 unsigned int irq; 49 unsigned int flags; 50 char name[10]; 51 }; 52 53 inline unsigned int hpet_readl(unsigned int a) 54 { 55 return readl(hpet_virt_address + a); 56 } 57 58 static inline void hpet_writel(unsigned int d, unsigned int a) 59 { 60 writel(d, hpet_virt_address + a); 61 } 62 63 #ifdef CONFIG_X86_64 64 #include <asm/pgtable.h> 65 #endif 66 67 static inline void hpet_set_mapping(void) 68 { 69 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 70 #ifdef CONFIG_X86_64 71 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); 72 #endif 73 } 74 75 static inline void hpet_clear_mapping(void) 76 { 77 iounmap(hpet_virt_address); 78 hpet_virt_address = NULL; 79 } 80 81 /* 82 * HPET command line enable / disable 83 */ 84 static int boot_hpet_disable; 85 int hpet_force_user; 86 static int hpet_verbose; 87 88 static int __init hpet_setup(char *str) 89 { 90 if (str) { 91 if (!strncmp("disable", str, 7)) 92 boot_hpet_disable = 1; 93 if (!strncmp("force", str, 5)) 94 hpet_force_user = 1; 95 if (!strncmp("verbose", str, 7)) 96 hpet_verbose = 1; 97 } 98 return 1; 99 } 100 __setup("hpet=", hpet_setup); 101 102 static int __init disable_hpet(char *str) 103 { 104 boot_hpet_disable = 1; 105 return 1; 106 } 107 __setup("nohpet", disable_hpet); 108 109 static inline int is_hpet_capable(void) 110 { 111 return !boot_hpet_disable && hpet_address; 112 } 113 114 /* 115 * HPET timer interrupt enable / disable 116 */ 117 static int hpet_legacy_int_enabled; 118 119 /** 120 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 121 */ 122 int is_hpet_enabled(void) 123 { 124 return is_hpet_capable() && hpet_legacy_int_enabled; 125 } 126 EXPORT_SYMBOL_GPL(is_hpet_enabled); 127 128 static void _hpet_print_config(const char *function, int line) 129 { 130 u32 i, timers, l, h; 131 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 132 l = hpet_readl(HPET_ID); 133 h = hpet_readl(HPET_PERIOD); 134 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 135 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 136 l = hpet_readl(HPET_CFG); 137 h = hpet_readl(HPET_STATUS); 138 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 139 l = hpet_readl(HPET_COUNTER); 140 h = hpet_readl(HPET_COUNTER+4); 141 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 142 143 for (i = 0; i < timers; i++) { 144 l = hpet_readl(HPET_Tn_CFG(i)); 145 h = hpet_readl(HPET_Tn_CFG(i)+4); 146 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 147 i, l, h); 148 l = hpet_readl(HPET_Tn_CMP(i)); 149 h = hpet_readl(HPET_Tn_CMP(i)+4); 150 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 151 i, l, h); 152 l = hpet_readl(HPET_Tn_ROUTE(i)); 153 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 154 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 155 i, l, h); 156 } 157 } 158 159 #define hpet_print_config() \ 160 do { \ 161 if (hpet_verbose) \ 162 _hpet_print_config(__FUNCTION__, __LINE__); \ 163 } while (0) 164 165 /* 166 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 167 * timer 0 and timer 1 in case of RTC emulation. 168 */ 169 #ifdef CONFIG_HPET 170 171 static void hpet_reserve_msi_timers(struct hpet_data *hd); 172 173 static void hpet_reserve_platform_timers(unsigned int id) 174 { 175 struct hpet __iomem *hpet = hpet_virt_address; 176 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 177 unsigned int nrtimers, i; 178 struct hpet_data hd; 179 180 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 181 182 memset(&hd, 0, sizeof(hd)); 183 hd.hd_phys_address = hpet_address; 184 hd.hd_address = hpet; 185 hd.hd_nirqs = nrtimers; 186 hpet_reserve_timer(&hd, 0); 187 188 #ifdef CONFIG_HPET_EMULATE_RTC 189 hpet_reserve_timer(&hd, 1); 190 #endif 191 192 /* 193 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 194 * is wrong for i8259!) not the output IRQ. Many BIOS writers 195 * don't bother configuring *any* comparator interrupts. 196 */ 197 hd.hd_irq[0] = HPET_LEGACY_8254; 198 hd.hd_irq[1] = HPET_LEGACY_RTC; 199 200 for (i = 2; i < nrtimers; timer++, i++) { 201 hd.hd_irq[i] = (readl(&timer->hpet_config) & 202 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 203 } 204 205 hpet_reserve_msi_timers(&hd); 206 207 hpet_alloc(&hd); 208 209 } 210 #else 211 static void hpet_reserve_platform_timers(unsigned int id) { } 212 #endif 213 214 /* 215 * Common hpet info 216 */ 217 static unsigned long hpet_period; 218 219 static void hpet_legacy_set_mode(enum clock_event_mode mode, 220 struct clock_event_device *evt); 221 static int hpet_legacy_next_event(unsigned long delta, 222 struct clock_event_device *evt); 223 224 /* 225 * The hpet clock event device 226 */ 227 static struct clock_event_device hpet_clockevent = { 228 .name = "hpet", 229 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 230 .set_mode = hpet_legacy_set_mode, 231 .set_next_event = hpet_legacy_next_event, 232 .shift = 32, 233 .irq = 0, 234 .rating = 50, 235 }; 236 237 static void hpet_stop_counter(void) 238 { 239 unsigned long cfg = hpet_readl(HPET_CFG); 240 cfg &= ~HPET_CFG_ENABLE; 241 hpet_writel(cfg, HPET_CFG); 242 } 243 244 static void hpet_reset_counter(void) 245 { 246 hpet_writel(0, HPET_COUNTER); 247 hpet_writel(0, HPET_COUNTER + 4); 248 } 249 250 static void hpet_start_counter(void) 251 { 252 unsigned int cfg = hpet_readl(HPET_CFG); 253 cfg |= HPET_CFG_ENABLE; 254 hpet_writel(cfg, HPET_CFG); 255 } 256 257 static void hpet_restart_counter(void) 258 { 259 hpet_stop_counter(); 260 hpet_reset_counter(); 261 hpet_start_counter(); 262 } 263 264 static void hpet_resume_device(void) 265 { 266 force_hpet_resume(); 267 } 268 269 static void hpet_resume_counter(struct clocksource *cs) 270 { 271 hpet_resume_device(); 272 hpet_restart_counter(); 273 } 274 275 static void hpet_enable_legacy_int(void) 276 { 277 unsigned int cfg = hpet_readl(HPET_CFG); 278 279 cfg |= HPET_CFG_LEGACY; 280 hpet_writel(cfg, HPET_CFG); 281 hpet_legacy_int_enabled = 1; 282 } 283 284 static void hpet_legacy_clockevent_register(void) 285 { 286 /* Start HPET legacy interrupts */ 287 hpet_enable_legacy_int(); 288 289 /* 290 * The mult factor is defined as (include/linux/clockchips.h) 291 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) 292 * hpet_period is in units of femtoseconds (per cycle), so 293 * mult/2^shift = cyc/ns = 10^6/hpet_period 294 * mult = (10^6 * 2^shift)/hpet_period 295 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period 296 */ 297 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, 298 hpet_period, hpet_clockevent.shift); 299 /* Calculate the min / max delta */ 300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 301 &hpet_clockevent); 302 /* 5 usec minimum reprogramming delta. */ 303 hpet_clockevent.min_delta_ns = 5000; 304 305 /* 306 * Start hpet with the boot cpu mask and make it 307 * global after the IO_APIC has been initialized. 308 */ 309 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 310 clockevents_register_device(&hpet_clockevent); 311 global_clock_event = &hpet_clockevent; 312 printk(KERN_DEBUG "hpet clockevent registered\n"); 313 } 314 315 static int hpet_setup_msi_irq(unsigned int irq); 316 317 static void hpet_set_mode(enum clock_event_mode mode, 318 struct clock_event_device *evt, int timer) 319 { 320 unsigned int cfg, cmp, now; 321 uint64_t delta; 322 323 switch (mode) { 324 case CLOCK_EVT_MODE_PERIODIC: 325 hpet_stop_counter(); 326 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; 327 delta >>= evt->shift; 328 now = hpet_readl(HPET_COUNTER); 329 cmp = now + (unsigned int) delta; 330 cfg = hpet_readl(HPET_Tn_CFG(timer)); 331 /* Make sure we use edge triggered interrupts */ 332 cfg &= ~HPET_TN_LEVEL; 333 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 334 HPET_TN_SETVAL | HPET_TN_32BIT; 335 hpet_writel(cfg, HPET_Tn_CFG(timer)); 336 hpet_writel(cmp, HPET_Tn_CMP(timer)); 337 udelay(1); 338 /* 339 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 340 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 341 * bit is automatically cleared after the first write. 342 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 343 * Publication # 24674) 344 */ 345 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); 346 hpet_start_counter(); 347 hpet_print_config(); 348 break; 349 350 case CLOCK_EVT_MODE_ONESHOT: 351 cfg = hpet_readl(HPET_Tn_CFG(timer)); 352 cfg &= ~HPET_TN_PERIODIC; 353 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 354 hpet_writel(cfg, HPET_Tn_CFG(timer)); 355 break; 356 357 case CLOCK_EVT_MODE_UNUSED: 358 case CLOCK_EVT_MODE_SHUTDOWN: 359 cfg = hpet_readl(HPET_Tn_CFG(timer)); 360 cfg &= ~HPET_TN_ENABLE; 361 hpet_writel(cfg, HPET_Tn_CFG(timer)); 362 break; 363 364 case CLOCK_EVT_MODE_RESUME: 365 if (timer == 0) { 366 hpet_enable_legacy_int(); 367 } else { 368 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 369 hpet_setup_msi_irq(hdev->irq); 370 disable_irq(hdev->irq); 371 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 372 enable_irq(hdev->irq); 373 } 374 hpet_print_config(); 375 break; 376 } 377 } 378 379 static int hpet_next_event(unsigned long delta, 380 struct clock_event_device *evt, int timer) 381 { 382 u32 cnt; 383 384 cnt = hpet_readl(HPET_COUNTER); 385 cnt += (u32) delta; 386 hpet_writel(cnt, HPET_Tn_CMP(timer)); 387 388 /* 389 * We need to read back the CMP register on certain HPET 390 * implementations (ATI chipsets) which seem to delay the 391 * transfer of the compare register into the internal compare 392 * logic. With small deltas this might actually be too late as 393 * the counter could already be higher than the compare value 394 * at that point and we would wait for the next hpet interrupt 395 * forever. We found out that reading the CMP register back 396 * forces the transfer so we can rely on the comparison with 397 * the counter register below. If the read back from the 398 * compare register does not match the value we programmed 399 * then we might have a real hardware problem. We can not do 400 * much about it here, but at least alert the user/admin with 401 * a prominent warning. 402 * 403 * An erratum on some chipsets (ICH9,..), results in 404 * comparator read immediately following a write returning old 405 * value. Workaround for this is to read this value second 406 * time, when first read returns old value. 407 * 408 * In fact the write to the comparator register is delayed up 409 * to two HPET cycles so the workaround we tried to restrict 410 * the readback to those known to be borked ATI chipsets 411 * failed miserably. So we give up on optimizations forever 412 * and penalize all HPET incarnations unconditionally. 413 */ 414 if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) { 415 if (hpet_readl(HPET_Tn_CMP(timer)) != cnt) 416 printk_once(KERN_WARNING 417 "hpet: compare register read back failed.\n"); 418 } 419 420 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; 421 } 422 423 static void hpet_legacy_set_mode(enum clock_event_mode mode, 424 struct clock_event_device *evt) 425 { 426 hpet_set_mode(mode, evt, 0); 427 } 428 429 static int hpet_legacy_next_event(unsigned long delta, 430 struct clock_event_device *evt) 431 { 432 return hpet_next_event(delta, evt, 0); 433 } 434 435 /* 436 * HPET MSI Support 437 */ 438 #ifdef CONFIG_PCI_MSI 439 440 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 441 static struct hpet_dev *hpet_devs; 442 443 void hpet_msi_unmask(struct irq_data *data) 444 { 445 struct hpet_dev *hdev = data->handler_data; 446 unsigned int cfg; 447 448 /* unmask it */ 449 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 450 cfg |= HPET_TN_FSB; 451 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 452 } 453 454 void hpet_msi_mask(struct irq_data *data) 455 { 456 struct hpet_dev *hdev = data->handler_data; 457 unsigned int cfg; 458 459 /* mask it */ 460 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 461 cfg &= ~HPET_TN_FSB; 462 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 463 } 464 465 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) 466 { 467 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 468 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 469 } 470 471 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) 472 { 473 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 474 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 475 msg->address_hi = 0; 476 } 477 478 static void hpet_msi_set_mode(enum clock_event_mode mode, 479 struct clock_event_device *evt) 480 { 481 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 482 hpet_set_mode(mode, evt, hdev->num); 483 } 484 485 static int hpet_msi_next_event(unsigned long delta, 486 struct clock_event_device *evt) 487 { 488 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 489 return hpet_next_event(delta, evt, hdev->num); 490 } 491 492 static int hpet_setup_msi_irq(unsigned int irq) 493 { 494 if (arch_setup_hpet_msi(irq, hpet_blockid)) { 495 destroy_irq(irq); 496 return -EINVAL; 497 } 498 return 0; 499 } 500 501 static int hpet_assign_irq(struct hpet_dev *dev) 502 { 503 unsigned int irq; 504 505 irq = create_irq_nr(0, -1); 506 if (!irq) 507 return -EINVAL; 508 509 set_irq_data(irq, dev); 510 511 if (hpet_setup_msi_irq(irq)) 512 return -EINVAL; 513 514 dev->irq = irq; 515 return 0; 516 } 517 518 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 519 { 520 struct hpet_dev *dev = (struct hpet_dev *)data; 521 struct clock_event_device *hevt = &dev->evt; 522 523 if (!hevt->event_handler) { 524 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 525 dev->num); 526 return IRQ_HANDLED; 527 } 528 529 hevt->event_handler(hevt); 530 return IRQ_HANDLED; 531 } 532 533 static int hpet_setup_irq(struct hpet_dev *dev) 534 { 535 536 if (request_irq(dev->irq, hpet_interrupt_handler, 537 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, 538 dev->name, dev)) 539 return -1; 540 541 disable_irq(dev->irq); 542 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 543 enable_irq(dev->irq); 544 545 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 546 dev->name, dev->irq); 547 548 return 0; 549 } 550 551 /* This should be called in specific @cpu */ 552 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 553 { 554 struct clock_event_device *evt = &hdev->evt; 555 uint64_t hpet_freq; 556 557 WARN_ON(cpu != smp_processor_id()); 558 if (!(hdev->flags & HPET_DEV_VALID)) 559 return; 560 561 if (hpet_setup_msi_irq(hdev->irq)) 562 return; 563 564 hdev->cpu = cpu; 565 per_cpu(cpu_hpet_dev, cpu) = hdev; 566 evt->name = hdev->name; 567 hpet_setup_irq(hdev); 568 evt->irq = hdev->irq; 569 570 evt->rating = 110; 571 evt->features = CLOCK_EVT_FEAT_ONESHOT; 572 if (hdev->flags & HPET_DEV_PERI_CAP) 573 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 574 575 evt->set_mode = hpet_msi_set_mode; 576 evt->set_next_event = hpet_msi_next_event; 577 evt->shift = 32; 578 579 /* 580 * The period is a femto seconds value. We need to calculate the 581 * scaled math multiplication factor for nanosecond to hpet tick 582 * conversion. 583 */ 584 hpet_freq = FSEC_PER_SEC; 585 do_div(hpet_freq, hpet_period); 586 evt->mult = div_sc((unsigned long) hpet_freq, 587 NSEC_PER_SEC, evt->shift); 588 /* Calculate the max delta */ 589 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); 590 /* 5 usec minimum reprogramming delta. */ 591 evt->min_delta_ns = 5000; 592 593 evt->cpumask = cpumask_of(hdev->cpu); 594 clockevents_register_device(evt); 595 } 596 597 #ifdef CONFIG_HPET 598 /* Reserve at least one timer for userspace (/dev/hpet) */ 599 #define RESERVE_TIMERS 1 600 #else 601 #define RESERVE_TIMERS 0 602 #endif 603 604 static void hpet_msi_capability_lookup(unsigned int start_timer) 605 { 606 unsigned int id; 607 unsigned int num_timers; 608 unsigned int num_timers_used = 0; 609 int i; 610 611 if (hpet_msi_disable) 612 return; 613 614 if (boot_cpu_has(X86_FEATURE_ARAT)) 615 return; 616 id = hpet_readl(HPET_ID); 617 618 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 619 num_timers++; /* Value read out starts from 0 */ 620 hpet_print_config(); 621 622 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 623 if (!hpet_devs) 624 return; 625 626 hpet_num_timers = num_timers; 627 628 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 629 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 630 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 631 632 /* Only consider HPET timer with MSI support */ 633 if (!(cfg & HPET_TN_FSB_CAP)) 634 continue; 635 636 hdev->flags = 0; 637 if (cfg & HPET_TN_PERIODIC_CAP) 638 hdev->flags |= HPET_DEV_PERI_CAP; 639 hdev->num = i; 640 641 sprintf(hdev->name, "hpet%d", i); 642 if (hpet_assign_irq(hdev)) 643 continue; 644 645 hdev->flags |= HPET_DEV_FSB_CAP; 646 hdev->flags |= HPET_DEV_VALID; 647 num_timers_used++; 648 if (num_timers_used == num_possible_cpus()) 649 break; 650 } 651 652 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 653 num_timers, num_timers_used); 654 } 655 656 #ifdef CONFIG_HPET 657 static void hpet_reserve_msi_timers(struct hpet_data *hd) 658 { 659 int i; 660 661 if (!hpet_devs) 662 return; 663 664 for (i = 0; i < hpet_num_timers; i++) { 665 struct hpet_dev *hdev = &hpet_devs[i]; 666 667 if (!(hdev->flags & HPET_DEV_VALID)) 668 continue; 669 670 hd->hd_irq[hdev->num] = hdev->irq; 671 hpet_reserve_timer(hd, hdev->num); 672 } 673 } 674 #endif 675 676 static struct hpet_dev *hpet_get_unused_timer(void) 677 { 678 int i; 679 680 if (!hpet_devs) 681 return NULL; 682 683 for (i = 0; i < hpet_num_timers; i++) { 684 struct hpet_dev *hdev = &hpet_devs[i]; 685 686 if (!(hdev->flags & HPET_DEV_VALID)) 687 continue; 688 if (test_and_set_bit(HPET_DEV_USED_BIT, 689 (unsigned long *)&hdev->flags)) 690 continue; 691 return hdev; 692 } 693 return NULL; 694 } 695 696 struct hpet_work_struct { 697 struct delayed_work work; 698 struct completion complete; 699 }; 700 701 static void hpet_work(struct work_struct *w) 702 { 703 struct hpet_dev *hdev; 704 int cpu = smp_processor_id(); 705 struct hpet_work_struct *hpet_work; 706 707 hpet_work = container_of(w, struct hpet_work_struct, work.work); 708 709 hdev = hpet_get_unused_timer(); 710 if (hdev) 711 init_one_hpet_msi_clockevent(hdev, cpu); 712 713 complete(&hpet_work->complete); 714 } 715 716 static int hpet_cpuhp_notify(struct notifier_block *n, 717 unsigned long action, void *hcpu) 718 { 719 unsigned long cpu = (unsigned long)hcpu; 720 struct hpet_work_struct work; 721 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 722 723 switch (action & 0xf) { 724 case CPU_ONLINE: 725 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); 726 init_completion(&work.complete); 727 /* FIXME: add schedule_work_on() */ 728 schedule_delayed_work_on(cpu, &work.work, 0); 729 wait_for_completion(&work.complete); 730 destroy_timer_on_stack(&work.work.timer); 731 break; 732 case CPU_DEAD: 733 if (hdev) { 734 free_irq(hdev->irq, hdev); 735 hdev->flags &= ~HPET_DEV_USED; 736 per_cpu(cpu_hpet_dev, cpu) = NULL; 737 } 738 break; 739 } 740 return NOTIFY_OK; 741 } 742 #else 743 744 static int hpet_setup_msi_irq(unsigned int irq) 745 { 746 return 0; 747 } 748 static void hpet_msi_capability_lookup(unsigned int start_timer) 749 { 750 return; 751 } 752 753 #ifdef CONFIG_HPET 754 static void hpet_reserve_msi_timers(struct hpet_data *hd) 755 { 756 return; 757 } 758 #endif 759 760 static int hpet_cpuhp_notify(struct notifier_block *n, 761 unsigned long action, void *hcpu) 762 { 763 return NOTIFY_OK; 764 } 765 766 #endif 767 768 /* 769 * Clock source related code 770 */ 771 static cycle_t read_hpet(struct clocksource *cs) 772 { 773 return (cycle_t)hpet_readl(HPET_COUNTER); 774 } 775 776 #ifdef CONFIG_X86_64 777 static cycle_t __vsyscall_fn vread_hpet(void) 778 { 779 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); 780 } 781 #endif 782 783 static struct clocksource clocksource_hpet = { 784 .name = "hpet", 785 .rating = 250, 786 .read = read_hpet, 787 .mask = HPET_MASK, 788 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 789 .resume = hpet_resume_counter, 790 #ifdef CONFIG_X86_64 791 .vread = vread_hpet, 792 #endif 793 }; 794 795 static int hpet_clocksource_register(void) 796 { 797 u64 start, now; 798 u64 hpet_freq; 799 cycle_t t1; 800 801 /* Start the counter */ 802 hpet_restart_counter(); 803 804 /* Verify whether hpet counter works */ 805 t1 = hpet_readl(HPET_COUNTER); 806 rdtscll(start); 807 808 /* 809 * We don't know the TSC frequency yet, but waiting for 810 * 200000 TSC cycles is safe: 811 * 4 GHz == 50us 812 * 1 GHz == 200us 813 */ 814 do { 815 rep_nop(); 816 rdtscll(now); 817 } while ((now - start) < 200000UL); 818 819 if (t1 == hpet_readl(HPET_COUNTER)) { 820 printk(KERN_WARNING 821 "HPET counter not counting. HPET disabled\n"); 822 return -ENODEV; 823 } 824 825 /* 826 * The definition of mult is (include/linux/clocksource.h) 827 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc 828 * so we first need to convert hpet_period to ns/cyc units: 829 * mult/2^shift = ns/cyc = hpet_period/10^6 830 * mult = (hpet_period * 2^shift)/10^6 831 * mult = (hpet_period << shift)/FSEC_PER_NSEC 832 */ 833 834 /* Need to convert hpet_period (fsec/cyc) to cyc/sec: 835 * 836 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc) 837 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period 838 */ 839 hpet_freq = FSEC_PER_SEC; 840 do_div(hpet_freq, hpet_period); 841 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 842 843 return 0; 844 } 845 846 /** 847 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 848 */ 849 int __init hpet_enable(void) 850 { 851 unsigned int id; 852 int i; 853 854 if (!is_hpet_capable()) 855 return 0; 856 857 hpet_set_mapping(); 858 859 /* 860 * Read the period and check for a sane value: 861 */ 862 hpet_period = hpet_readl(HPET_PERIOD); 863 864 /* 865 * AMD SB700 based systems with spread spectrum enabled use a 866 * SMM based HPET emulation to provide proper frequency 867 * setting. The SMM code is initialized with the first HPET 868 * register access and takes some time to complete. During 869 * this time the config register reads 0xffffffff. We check 870 * for max. 1000 loops whether the config register reads a non 871 * 0xffffffff value to make sure that HPET is up and running 872 * before we go further. A counting loop is safe, as the HPET 873 * access takes thousands of CPU cycles. On non SB700 based 874 * machines this check is only done once and has no side 875 * effects. 876 */ 877 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 878 if (i == 1000) { 879 printk(KERN_WARNING 880 "HPET config register value = 0xFFFFFFFF. " 881 "Disabling HPET\n"); 882 goto out_nohpet; 883 } 884 } 885 886 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 887 goto out_nohpet; 888 889 /* 890 * Read the HPET ID register to retrieve the IRQ routing 891 * information and the number of channels 892 */ 893 id = hpet_readl(HPET_ID); 894 hpet_print_config(); 895 896 #ifdef CONFIG_HPET_EMULATE_RTC 897 /* 898 * The legacy routing mode needs at least two channels, tick timer 899 * and the rtc emulation channel. 900 */ 901 if (!(id & HPET_ID_NUMBER)) 902 goto out_nohpet; 903 #endif 904 905 if (hpet_clocksource_register()) 906 goto out_nohpet; 907 908 if (id & HPET_ID_LEGSUP) { 909 hpet_legacy_clockevent_register(); 910 return 1; 911 } 912 return 0; 913 914 out_nohpet: 915 hpet_clear_mapping(); 916 hpet_address = 0; 917 return 0; 918 } 919 920 /* 921 * Needs to be late, as the reserve_timer code calls kalloc ! 922 * 923 * Not a problem on i386 as hpet_enable is called from late_time_init, 924 * but on x86_64 it is necessary ! 925 */ 926 static __init int hpet_late_init(void) 927 { 928 int cpu; 929 930 if (boot_hpet_disable) 931 return -ENODEV; 932 933 if (!hpet_address) { 934 if (!force_hpet_address) 935 return -ENODEV; 936 937 hpet_address = force_hpet_address; 938 hpet_enable(); 939 } 940 941 if (!hpet_virt_address) 942 return -ENODEV; 943 944 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 945 hpet_msi_capability_lookup(2); 946 else 947 hpet_msi_capability_lookup(0); 948 949 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 950 hpet_print_config(); 951 952 if (hpet_msi_disable) 953 return 0; 954 955 if (boot_cpu_has(X86_FEATURE_ARAT)) 956 return 0; 957 958 for_each_online_cpu(cpu) { 959 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); 960 } 961 962 /* This notifier should be called after workqueue is ready */ 963 hotcpu_notifier(hpet_cpuhp_notify, -20); 964 965 return 0; 966 } 967 fs_initcall(hpet_late_init); 968 969 void hpet_disable(void) 970 { 971 if (is_hpet_capable() && hpet_virt_address) { 972 unsigned int cfg = hpet_readl(HPET_CFG); 973 974 if (hpet_legacy_int_enabled) { 975 cfg &= ~HPET_CFG_LEGACY; 976 hpet_legacy_int_enabled = 0; 977 } 978 cfg &= ~HPET_CFG_ENABLE; 979 hpet_writel(cfg, HPET_CFG); 980 } 981 } 982 983 #ifdef CONFIG_HPET_EMULATE_RTC 984 985 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 986 * is enabled, we support RTC interrupt functionality in software. 987 * RTC has 3 kinds of interrupts: 988 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 989 * is updated 990 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 991 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 992 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 993 * (1) and (2) above are implemented using polling at a frequency of 994 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 995 * overhead. (DEFAULT_RTC_INT_FREQ) 996 * For (3), we use interrupts at 64Hz or user specified periodic 997 * frequency, whichever is higher. 998 */ 999 #include <linux/mc146818rtc.h> 1000 #include <linux/rtc.h> 1001 #include <asm/rtc.h> 1002 1003 #define DEFAULT_RTC_INT_FREQ 64 1004 #define DEFAULT_RTC_SHIFT 6 1005 #define RTC_NUM_INTS 1 1006 1007 static unsigned long hpet_rtc_flags; 1008 static int hpet_prev_update_sec; 1009 static struct rtc_time hpet_alarm_time; 1010 static unsigned long hpet_pie_count; 1011 static u32 hpet_t1_cmp; 1012 static u32 hpet_default_delta; 1013 static u32 hpet_pie_delta; 1014 static unsigned long hpet_pie_limit; 1015 1016 static rtc_irq_handler irq_handler; 1017 1018 /* 1019 * Check that the hpet counter c1 is ahead of the c2 1020 */ 1021 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1022 { 1023 return (s32)(c2 - c1) < 0; 1024 } 1025 1026 /* 1027 * Registers a IRQ handler. 1028 */ 1029 int hpet_register_irq_handler(rtc_irq_handler handler) 1030 { 1031 if (!is_hpet_enabled()) 1032 return -ENODEV; 1033 if (irq_handler) 1034 return -EBUSY; 1035 1036 irq_handler = handler; 1037 1038 return 0; 1039 } 1040 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1041 1042 /* 1043 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1044 * and does cleanup. 1045 */ 1046 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1047 { 1048 if (!is_hpet_enabled()) 1049 return; 1050 1051 irq_handler = NULL; 1052 hpet_rtc_flags = 0; 1053 } 1054 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1055 1056 /* 1057 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1058 * is not supported by all HPET implementations for timer 1. 1059 * 1060 * hpet_rtc_timer_init() is called when the rtc is initialized. 1061 */ 1062 int hpet_rtc_timer_init(void) 1063 { 1064 unsigned int cfg, cnt, delta; 1065 unsigned long flags; 1066 1067 if (!is_hpet_enabled()) 1068 return 0; 1069 1070 if (!hpet_default_delta) { 1071 uint64_t clc; 1072 1073 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1074 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1075 hpet_default_delta = clc; 1076 } 1077 1078 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1079 delta = hpet_default_delta; 1080 else 1081 delta = hpet_pie_delta; 1082 1083 local_irq_save(flags); 1084 1085 cnt = delta + hpet_readl(HPET_COUNTER); 1086 hpet_writel(cnt, HPET_T1_CMP); 1087 hpet_t1_cmp = cnt; 1088 1089 cfg = hpet_readl(HPET_T1_CFG); 1090 cfg &= ~HPET_TN_PERIODIC; 1091 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1092 hpet_writel(cfg, HPET_T1_CFG); 1093 1094 local_irq_restore(flags); 1095 1096 return 1; 1097 } 1098 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1099 1100 /* 1101 * The functions below are called from rtc driver. 1102 * Return 0 if HPET is not being used. 1103 * Otherwise do the necessary changes and return 1. 1104 */ 1105 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1106 { 1107 if (!is_hpet_enabled()) 1108 return 0; 1109 1110 hpet_rtc_flags &= ~bit_mask; 1111 return 1; 1112 } 1113 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1114 1115 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1116 { 1117 unsigned long oldbits = hpet_rtc_flags; 1118 1119 if (!is_hpet_enabled()) 1120 return 0; 1121 1122 hpet_rtc_flags |= bit_mask; 1123 1124 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1125 hpet_prev_update_sec = -1; 1126 1127 if (!oldbits) 1128 hpet_rtc_timer_init(); 1129 1130 return 1; 1131 } 1132 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1133 1134 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1135 unsigned char sec) 1136 { 1137 if (!is_hpet_enabled()) 1138 return 0; 1139 1140 hpet_alarm_time.tm_hour = hrs; 1141 hpet_alarm_time.tm_min = min; 1142 hpet_alarm_time.tm_sec = sec; 1143 1144 return 1; 1145 } 1146 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1147 1148 int hpet_set_periodic_freq(unsigned long freq) 1149 { 1150 uint64_t clc; 1151 1152 if (!is_hpet_enabled()) 1153 return 0; 1154 1155 if (freq <= DEFAULT_RTC_INT_FREQ) 1156 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1157 else { 1158 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1159 do_div(clc, freq); 1160 clc >>= hpet_clockevent.shift; 1161 hpet_pie_delta = clc; 1162 hpet_pie_limit = 0; 1163 } 1164 return 1; 1165 } 1166 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1167 1168 int hpet_rtc_dropped_irq(void) 1169 { 1170 return is_hpet_enabled(); 1171 } 1172 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1173 1174 static void hpet_rtc_timer_reinit(void) 1175 { 1176 unsigned int cfg, delta; 1177 int lost_ints = -1; 1178 1179 if (unlikely(!hpet_rtc_flags)) { 1180 cfg = hpet_readl(HPET_T1_CFG); 1181 cfg &= ~HPET_TN_ENABLE; 1182 hpet_writel(cfg, HPET_T1_CFG); 1183 return; 1184 } 1185 1186 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1187 delta = hpet_default_delta; 1188 else 1189 delta = hpet_pie_delta; 1190 1191 /* 1192 * Increment the comparator value until we are ahead of the 1193 * current count. 1194 */ 1195 do { 1196 hpet_t1_cmp += delta; 1197 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1198 lost_ints++; 1199 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1200 1201 if (lost_ints) { 1202 if (hpet_rtc_flags & RTC_PIE) 1203 hpet_pie_count += lost_ints; 1204 if (printk_ratelimit()) 1205 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1206 lost_ints); 1207 } 1208 } 1209 1210 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1211 { 1212 struct rtc_time curr_time; 1213 unsigned long rtc_int_flag = 0; 1214 1215 hpet_rtc_timer_reinit(); 1216 memset(&curr_time, 0, sizeof(struct rtc_time)); 1217 1218 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1219 get_rtc_time(&curr_time); 1220 1221 if (hpet_rtc_flags & RTC_UIE && 1222 curr_time.tm_sec != hpet_prev_update_sec) { 1223 if (hpet_prev_update_sec >= 0) 1224 rtc_int_flag = RTC_UF; 1225 hpet_prev_update_sec = curr_time.tm_sec; 1226 } 1227 1228 if (hpet_rtc_flags & RTC_PIE && 1229 ++hpet_pie_count >= hpet_pie_limit) { 1230 rtc_int_flag |= RTC_PF; 1231 hpet_pie_count = 0; 1232 } 1233 1234 if (hpet_rtc_flags & RTC_AIE && 1235 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1236 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1237 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1238 rtc_int_flag |= RTC_AF; 1239 1240 if (rtc_int_flag) { 1241 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1242 if (irq_handler) 1243 irq_handler(rtc_int_flag, dev_id); 1244 } 1245 return IRQ_HANDLED; 1246 } 1247 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1248 #endif 1249