1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/delay.h> 4 #include <linux/errno.h> 5 #include <linux/hpet.h> 6 #include <linux/init.h> 7 #include <linux/sysdev.h> 8 #include <linux/pm.h> 9 10 #include <asm/fixmap.h> 11 #include <asm/hpet.h> 12 #include <asm/i8253.h> 13 #include <asm/io.h> 14 15 #define HPET_MASK CLOCKSOURCE_MASK(32) 16 #define HPET_SHIFT 22 17 18 /* FSEC = 10^-15 19 NSEC = 10^-9 */ 20 #define FSEC_PER_NSEC 1000000 21 22 /* 23 * HPET address is set in acpi/boot.c, when an ACPI entry exists 24 */ 25 unsigned long hpet_address; 26 static void __iomem *hpet_virt_address; 27 28 unsigned long hpet_readl(unsigned long a) 29 { 30 return readl(hpet_virt_address + a); 31 } 32 33 static inline void hpet_writel(unsigned long d, unsigned long a) 34 { 35 writel(d, hpet_virt_address + a); 36 } 37 38 #ifdef CONFIG_X86_64 39 40 #include <asm/pgtable.h> 41 42 static inline void hpet_set_mapping(void) 43 { 44 set_fixmap_nocache(FIX_HPET_BASE, hpet_address); 45 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); 46 hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE); 47 } 48 49 static inline void hpet_clear_mapping(void) 50 { 51 hpet_virt_address = NULL; 52 } 53 54 #else 55 56 static inline void hpet_set_mapping(void) 57 { 58 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 59 } 60 61 static inline void hpet_clear_mapping(void) 62 { 63 iounmap(hpet_virt_address); 64 hpet_virt_address = NULL; 65 } 66 #endif 67 68 /* 69 * HPET command line enable / disable 70 */ 71 static int boot_hpet_disable; 72 int hpet_force_user; 73 74 static int __init hpet_setup(char* str) 75 { 76 if (str) { 77 if (!strncmp("disable", str, 7)) 78 boot_hpet_disable = 1; 79 if (!strncmp("force", str, 5)) 80 hpet_force_user = 1; 81 } 82 return 1; 83 } 84 __setup("hpet=", hpet_setup); 85 86 static int __init disable_hpet(char *str) 87 { 88 boot_hpet_disable = 1; 89 return 1; 90 } 91 __setup("nohpet", disable_hpet); 92 93 static inline int is_hpet_capable(void) 94 { 95 return (!boot_hpet_disable && hpet_address); 96 } 97 98 /* 99 * HPET timer interrupt enable / disable 100 */ 101 static int hpet_legacy_int_enabled; 102 103 /** 104 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 105 */ 106 int is_hpet_enabled(void) 107 { 108 return is_hpet_capable() && hpet_legacy_int_enabled; 109 } 110 EXPORT_SYMBOL_GPL(is_hpet_enabled); 111 112 /* 113 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 114 * timer 0 and timer 1 in case of RTC emulation. 115 */ 116 #ifdef CONFIG_HPET 117 static void hpet_reserve_platform_timers(unsigned long id) 118 { 119 struct hpet __iomem *hpet = hpet_virt_address; 120 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 121 unsigned int nrtimers, i; 122 struct hpet_data hd; 123 124 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 125 126 memset(&hd, 0, sizeof (hd)); 127 hd.hd_phys_address = hpet_address; 128 hd.hd_address = hpet; 129 hd.hd_nirqs = nrtimers; 130 hd.hd_flags = HPET_DATA_PLATFORM; 131 hpet_reserve_timer(&hd, 0); 132 133 #ifdef CONFIG_HPET_EMULATE_RTC 134 hpet_reserve_timer(&hd, 1); 135 #endif 136 hd.hd_irq[0] = HPET_LEGACY_8254; 137 hd.hd_irq[1] = HPET_LEGACY_RTC; 138 139 for (i = 2; i < nrtimers; timer++, i++) 140 hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> 141 Tn_INT_ROUTE_CNF_SHIFT; 142 hpet_alloc(&hd); 143 } 144 #else 145 static void hpet_reserve_platform_timers(unsigned long id) { } 146 #endif 147 148 /* 149 * Common hpet info 150 */ 151 static unsigned long hpet_period; 152 153 static void hpet_legacy_set_mode(enum clock_event_mode mode, 154 struct clock_event_device *evt); 155 static int hpet_legacy_next_event(unsigned long delta, 156 struct clock_event_device *evt); 157 158 /* 159 * The hpet clock event device 160 */ 161 static struct clock_event_device hpet_clockevent = { 162 .name = "hpet", 163 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 164 .set_mode = hpet_legacy_set_mode, 165 .set_next_event = hpet_legacy_next_event, 166 .shift = 32, 167 .irq = 0, 168 .rating = 50, 169 }; 170 171 static void hpet_start_counter(void) 172 { 173 unsigned long cfg = hpet_readl(HPET_CFG); 174 175 cfg &= ~HPET_CFG_ENABLE; 176 hpet_writel(cfg, HPET_CFG); 177 hpet_writel(0, HPET_COUNTER); 178 hpet_writel(0, HPET_COUNTER + 4); 179 cfg |= HPET_CFG_ENABLE; 180 hpet_writel(cfg, HPET_CFG); 181 } 182 183 static void hpet_resume_device(void) 184 { 185 force_hpet_resume(); 186 } 187 188 static void hpet_restart_counter(void) 189 { 190 hpet_resume_device(); 191 hpet_start_counter(); 192 } 193 194 static void hpet_enable_legacy_int(void) 195 { 196 unsigned long cfg = hpet_readl(HPET_CFG); 197 198 cfg |= HPET_CFG_LEGACY; 199 hpet_writel(cfg, HPET_CFG); 200 hpet_legacy_int_enabled = 1; 201 } 202 203 static void hpet_legacy_clockevent_register(void) 204 { 205 uint64_t hpet_freq; 206 207 /* Start HPET legacy interrupts */ 208 hpet_enable_legacy_int(); 209 210 /* 211 * The period is a femto seconds value. We need to calculate the 212 * scaled math multiplication factor for nanosecond to hpet tick 213 * conversion. 214 */ 215 hpet_freq = 1000000000000000ULL; 216 do_div(hpet_freq, hpet_period); 217 hpet_clockevent.mult = div_sc((unsigned long) hpet_freq, 218 NSEC_PER_SEC, 32); 219 /* Calculate the min / max delta */ 220 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 221 &hpet_clockevent); 222 hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30, 223 &hpet_clockevent); 224 225 /* 226 * Start hpet with the boot cpu mask and make it 227 * global after the IO_APIC has been initialized. 228 */ 229 hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); 230 clockevents_register_device(&hpet_clockevent); 231 global_clock_event = &hpet_clockevent; 232 printk(KERN_DEBUG "hpet clockevent registered\n"); 233 } 234 235 static void hpet_legacy_set_mode(enum clock_event_mode mode, 236 struct clock_event_device *evt) 237 { 238 unsigned long cfg, cmp, now; 239 uint64_t delta; 240 241 switch(mode) { 242 case CLOCK_EVT_MODE_PERIODIC: 243 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; 244 delta >>= hpet_clockevent.shift; 245 now = hpet_readl(HPET_COUNTER); 246 cmp = now + (unsigned long) delta; 247 cfg = hpet_readl(HPET_T0_CFG); 248 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 249 HPET_TN_SETVAL | HPET_TN_32BIT; 250 hpet_writel(cfg, HPET_T0_CFG); 251 /* 252 * The first write after writing TN_SETVAL to the 253 * config register sets the counter value, the second 254 * write sets the period. 255 */ 256 hpet_writel(cmp, HPET_T0_CMP); 257 udelay(1); 258 hpet_writel((unsigned long) delta, HPET_T0_CMP); 259 break; 260 261 case CLOCK_EVT_MODE_ONESHOT: 262 cfg = hpet_readl(HPET_T0_CFG); 263 cfg &= ~HPET_TN_PERIODIC; 264 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 265 hpet_writel(cfg, HPET_T0_CFG); 266 break; 267 268 case CLOCK_EVT_MODE_UNUSED: 269 case CLOCK_EVT_MODE_SHUTDOWN: 270 cfg = hpet_readl(HPET_T0_CFG); 271 cfg &= ~HPET_TN_ENABLE; 272 hpet_writel(cfg, HPET_T0_CFG); 273 break; 274 275 case CLOCK_EVT_MODE_RESUME: 276 hpet_enable_legacy_int(); 277 break; 278 } 279 } 280 281 static int hpet_legacy_next_event(unsigned long delta, 282 struct clock_event_device *evt) 283 { 284 unsigned long cnt; 285 286 cnt = hpet_readl(HPET_COUNTER); 287 cnt += delta; 288 hpet_writel(cnt, HPET_T0_CMP); 289 290 return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0; 291 } 292 293 /* 294 * Clock source related code 295 */ 296 static cycle_t read_hpet(void) 297 { 298 return (cycle_t)hpet_readl(HPET_COUNTER); 299 } 300 301 #ifdef CONFIG_X86_64 302 static cycle_t __vsyscall_fn vread_hpet(void) 303 { 304 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); 305 } 306 #endif 307 308 static struct clocksource clocksource_hpet = { 309 .name = "hpet", 310 .rating = 250, 311 .read = read_hpet, 312 .mask = HPET_MASK, 313 .shift = HPET_SHIFT, 314 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 315 .resume = hpet_restart_counter, 316 #ifdef CONFIG_X86_64 317 .vread = vread_hpet, 318 #endif 319 }; 320 321 static int hpet_clocksource_register(void) 322 { 323 u64 tmp, start, now; 324 cycle_t t1; 325 326 /* Start the counter */ 327 hpet_start_counter(); 328 329 /* Verify whether hpet counter works */ 330 t1 = read_hpet(); 331 rdtscll(start); 332 333 /* 334 * We don't know the TSC frequency yet, but waiting for 335 * 200000 TSC cycles is safe: 336 * 4 GHz == 50us 337 * 1 GHz == 200us 338 */ 339 do { 340 rep_nop(); 341 rdtscll(now); 342 } while ((now - start) < 200000UL); 343 344 if (t1 == read_hpet()) { 345 printk(KERN_WARNING 346 "HPET counter not counting. HPET disabled\n"); 347 return -ENODEV; 348 } 349 350 /* Initialize and register HPET clocksource 351 * 352 * hpet period is in femto seconds per cycle 353 * so we need to convert this to ns/cyc units 354 * approximated by mult/2^shift 355 * 356 * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift 357 * fsec/cyc * 1ns/1000000fsec * 2^shift = mult 358 * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult 359 * (fsec/cyc << shift)/1000000 = mult 360 * (hpet_period << shift)/FSEC_PER_NSEC = mult 361 */ 362 tmp = (u64)hpet_period << HPET_SHIFT; 363 do_div(tmp, FSEC_PER_NSEC); 364 clocksource_hpet.mult = (u32)tmp; 365 366 clocksource_register(&clocksource_hpet); 367 368 return 0; 369 } 370 371 /* 372 * Try to setup the HPET timer 373 */ 374 int __init hpet_enable(void) 375 { 376 unsigned long id; 377 378 if (!is_hpet_capable()) 379 return 0; 380 381 hpet_set_mapping(); 382 383 /* 384 * Read the period and check for a sane value: 385 */ 386 hpet_period = hpet_readl(HPET_PERIOD); 387 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 388 goto out_nohpet; 389 390 /* 391 * Read the HPET ID register to retrieve the IRQ routing 392 * information and the number of channels 393 */ 394 id = hpet_readl(HPET_ID); 395 396 #ifdef CONFIG_HPET_EMULATE_RTC 397 /* 398 * The legacy routing mode needs at least two channels, tick timer 399 * and the rtc emulation channel. 400 */ 401 if (!(id & HPET_ID_NUMBER)) 402 goto out_nohpet; 403 #endif 404 405 if (hpet_clocksource_register()) 406 goto out_nohpet; 407 408 if (id & HPET_ID_LEGSUP) { 409 hpet_legacy_clockevent_register(); 410 return 1; 411 } 412 return 0; 413 414 out_nohpet: 415 hpet_clear_mapping(); 416 boot_hpet_disable = 1; 417 return 0; 418 } 419 420 /* 421 * Needs to be late, as the reserve_timer code calls kalloc ! 422 * 423 * Not a problem on i386 as hpet_enable is called from late_time_init, 424 * but on x86_64 it is necessary ! 425 */ 426 static __init int hpet_late_init(void) 427 { 428 if (boot_hpet_disable) 429 return -ENODEV; 430 431 if (!hpet_address) { 432 if (!force_hpet_address) 433 return -ENODEV; 434 435 hpet_address = force_hpet_address; 436 hpet_enable(); 437 if (!hpet_virt_address) 438 return -ENODEV; 439 } 440 441 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 442 443 return 0; 444 } 445 fs_initcall(hpet_late_init); 446 447 void hpet_disable(void) 448 { 449 if (is_hpet_capable()) { 450 unsigned long cfg = hpet_readl(HPET_CFG); 451 452 if (hpet_legacy_int_enabled) { 453 cfg &= ~HPET_CFG_LEGACY; 454 hpet_legacy_int_enabled = 0; 455 } 456 cfg &= ~HPET_CFG_ENABLE; 457 hpet_writel(cfg, HPET_CFG); 458 } 459 } 460 461 #ifdef CONFIG_HPET_EMULATE_RTC 462 463 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 464 * is enabled, we support RTC interrupt functionality in software. 465 * RTC has 3 kinds of interrupts: 466 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 467 * is updated 468 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 469 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 470 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 471 * (1) and (2) above are implemented using polling at a frequency of 472 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 473 * overhead. (DEFAULT_RTC_INT_FREQ) 474 * For (3), we use interrupts at 64Hz or user specified periodic 475 * frequency, whichever is higher. 476 */ 477 #include <linux/mc146818rtc.h> 478 #include <linux/rtc.h> 479 #include <asm/rtc.h> 480 481 #define DEFAULT_RTC_INT_FREQ 64 482 #define DEFAULT_RTC_SHIFT 6 483 #define RTC_NUM_INTS 1 484 485 static unsigned long hpet_rtc_flags; 486 static unsigned long hpet_prev_update_sec; 487 static struct rtc_time hpet_alarm_time; 488 static unsigned long hpet_pie_count; 489 static unsigned long hpet_t1_cmp; 490 static unsigned long hpet_default_delta; 491 static unsigned long hpet_pie_delta; 492 static unsigned long hpet_pie_limit; 493 494 static rtc_irq_handler irq_handler; 495 496 /* 497 * Registers a IRQ handler. 498 */ 499 int hpet_register_irq_handler(rtc_irq_handler handler) 500 { 501 if (!is_hpet_enabled()) 502 return -ENODEV; 503 if (irq_handler) 504 return -EBUSY; 505 506 irq_handler = handler; 507 508 return 0; 509 } 510 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 511 512 /* 513 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 514 * and does cleanup. 515 */ 516 void hpet_unregister_irq_handler(rtc_irq_handler handler) 517 { 518 if (!is_hpet_enabled()) 519 return; 520 521 irq_handler = NULL; 522 hpet_rtc_flags = 0; 523 } 524 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 525 526 /* 527 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 528 * is not supported by all HPET implementations for timer 1. 529 * 530 * hpet_rtc_timer_init() is called when the rtc is initialized. 531 */ 532 int hpet_rtc_timer_init(void) 533 { 534 unsigned long cfg, cnt, delta, flags; 535 536 if (!is_hpet_enabled()) 537 return 0; 538 539 if (!hpet_default_delta) { 540 uint64_t clc; 541 542 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 543 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 544 hpet_default_delta = (unsigned long) clc; 545 } 546 547 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 548 delta = hpet_default_delta; 549 else 550 delta = hpet_pie_delta; 551 552 local_irq_save(flags); 553 554 cnt = delta + hpet_readl(HPET_COUNTER); 555 hpet_writel(cnt, HPET_T1_CMP); 556 hpet_t1_cmp = cnt; 557 558 cfg = hpet_readl(HPET_T1_CFG); 559 cfg &= ~HPET_TN_PERIODIC; 560 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 561 hpet_writel(cfg, HPET_T1_CFG); 562 563 local_irq_restore(flags); 564 565 return 1; 566 } 567 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 568 569 /* 570 * The functions below are called from rtc driver. 571 * Return 0 if HPET is not being used. 572 * Otherwise do the necessary changes and return 1. 573 */ 574 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 575 { 576 if (!is_hpet_enabled()) 577 return 0; 578 579 hpet_rtc_flags &= ~bit_mask; 580 return 1; 581 } 582 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 583 584 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 585 { 586 unsigned long oldbits = hpet_rtc_flags; 587 588 if (!is_hpet_enabled()) 589 return 0; 590 591 hpet_rtc_flags |= bit_mask; 592 593 if (!oldbits) 594 hpet_rtc_timer_init(); 595 596 return 1; 597 } 598 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 599 600 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 601 unsigned char sec) 602 { 603 if (!is_hpet_enabled()) 604 return 0; 605 606 hpet_alarm_time.tm_hour = hrs; 607 hpet_alarm_time.tm_min = min; 608 hpet_alarm_time.tm_sec = sec; 609 610 return 1; 611 } 612 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 613 614 int hpet_set_periodic_freq(unsigned long freq) 615 { 616 uint64_t clc; 617 618 if (!is_hpet_enabled()) 619 return 0; 620 621 if (freq <= DEFAULT_RTC_INT_FREQ) 622 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 623 else { 624 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 625 do_div(clc, freq); 626 clc >>= hpet_clockevent.shift; 627 hpet_pie_delta = (unsigned long) clc; 628 } 629 return 1; 630 } 631 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 632 633 int hpet_rtc_dropped_irq(void) 634 { 635 return is_hpet_enabled(); 636 } 637 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 638 639 static void hpet_rtc_timer_reinit(void) 640 { 641 unsigned long cfg, delta; 642 int lost_ints = -1; 643 644 if (unlikely(!hpet_rtc_flags)) { 645 cfg = hpet_readl(HPET_T1_CFG); 646 cfg &= ~HPET_TN_ENABLE; 647 hpet_writel(cfg, HPET_T1_CFG); 648 return; 649 } 650 651 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 652 delta = hpet_default_delta; 653 else 654 delta = hpet_pie_delta; 655 656 /* 657 * Increment the comparator value until we are ahead of the 658 * current count. 659 */ 660 do { 661 hpet_t1_cmp += delta; 662 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 663 lost_ints++; 664 } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); 665 666 if (lost_ints) { 667 if (hpet_rtc_flags & RTC_PIE) 668 hpet_pie_count += lost_ints; 669 if (printk_ratelimit()) 670 printk(KERN_WARNING "rtc: lost %d interrupts\n", 671 lost_ints); 672 } 673 } 674 675 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 676 { 677 struct rtc_time curr_time; 678 unsigned long rtc_int_flag = 0; 679 680 hpet_rtc_timer_reinit(); 681 memset(&curr_time, 0, sizeof(struct rtc_time)); 682 683 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 684 get_rtc_time(&curr_time); 685 686 if (hpet_rtc_flags & RTC_UIE && 687 curr_time.tm_sec != hpet_prev_update_sec) { 688 rtc_int_flag = RTC_UF; 689 hpet_prev_update_sec = curr_time.tm_sec; 690 } 691 692 if (hpet_rtc_flags & RTC_PIE && 693 ++hpet_pie_count >= hpet_pie_limit) { 694 rtc_int_flag |= RTC_PF; 695 hpet_pie_count = 0; 696 } 697 698 if (hpet_rtc_flags & RTC_AIE && 699 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 700 (curr_time.tm_min == hpet_alarm_time.tm_min) && 701 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 702 rtc_int_flag |= RTC_AF; 703 704 if (rtc_int_flag) { 705 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 706 if (irq_handler) 707 irq_handler(rtc_int_flag, dev_id); 708 } 709 return IRQ_HANDLED; 710 } 711 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 712 #endif 713