1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/sysdev.h> 5 #include <linux/delay.h> 6 #include <linux/errno.h> 7 #include <linux/slab.h> 8 #include <linux/hpet.h> 9 #include <linux/init.h> 10 #include <linux/cpu.h> 11 #include <linux/pm.h> 12 #include <linux/io.h> 13 14 #include <asm/fixmap.h> 15 #include <asm/i8253.h> 16 #include <asm/hpet.h> 17 18 #define HPET_MASK CLOCKSOURCE_MASK(32) 19 20 /* FSEC = 10^-15 21 NSEC = 10^-9 */ 22 #define FSEC_PER_NSEC 1000000L 23 24 #define HPET_DEV_USED_BIT 2 25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 26 #define HPET_DEV_VALID 0x8 27 #define HPET_DEV_FSB_CAP 0x1000 28 #define HPET_DEV_PERI_CAP 0x2000 29 30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) 31 32 /* 33 * HPET address is set in acpi/boot.c, when an ACPI entry exists 34 */ 35 unsigned long hpet_address; 36 u8 hpet_blockid; /* OS timer block num */ 37 u8 hpet_msi_disable; 38 u8 hpet_readback_cmp; 39 40 #ifdef CONFIG_PCI_MSI 41 static unsigned long hpet_num_timers; 42 #endif 43 static void __iomem *hpet_virt_address; 44 45 struct hpet_dev { 46 struct clock_event_device evt; 47 unsigned int num; 48 int cpu; 49 unsigned int irq; 50 unsigned int flags; 51 char name[10]; 52 }; 53 54 inline unsigned int hpet_readl(unsigned int a) 55 { 56 return readl(hpet_virt_address + a); 57 } 58 59 static inline void hpet_writel(unsigned int d, unsigned int a) 60 { 61 writel(d, hpet_virt_address + a); 62 } 63 64 #ifdef CONFIG_X86_64 65 #include <asm/pgtable.h> 66 #endif 67 68 static inline void hpet_set_mapping(void) 69 { 70 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 71 #ifdef CONFIG_X86_64 72 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); 73 #endif 74 } 75 76 static inline void hpet_clear_mapping(void) 77 { 78 iounmap(hpet_virt_address); 79 hpet_virt_address = NULL; 80 } 81 82 /* 83 * HPET command line enable / disable 84 */ 85 static int boot_hpet_disable; 86 int hpet_force_user; 87 static int hpet_verbose; 88 89 static int __init hpet_setup(char *str) 90 { 91 if (str) { 92 if (!strncmp("disable", str, 7)) 93 boot_hpet_disable = 1; 94 if (!strncmp("force", str, 5)) 95 hpet_force_user = 1; 96 if (!strncmp("verbose", str, 7)) 97 hpet_verbose = 1; 98 } 99 return 1; 100 } 101 __setup("hpet=", hpet_setup); 102 103 static int __init disable_hpet(char *str) 104 { 105 boot_hpet_disable = 1; 106 return 1; 107 } 108 __setup("nohpet", disable_hpet); 109 110 static inline int is_hpet_capable(void) 111 { 112 return !boot_hpet_disable && hpet_address; 113 } 114 115 /* 116 * HPET timer interrupt enable / disable 117 */ 118 static int hpet_legacy_int_enabled; 119 120 /** 121 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 122 */ 123 int is_hpet_enabled(void) 124 { 125 return is_hpet_capable() && hpet_legacy_int_enabled; 126 } 127 EXPORT_SYMBOL_GPL(is_hpet_enabled); 128 129 static void _hpet_print_config(const char *function, int line) 130 { 131 u32 i, timers, l, h; 132 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 133 l = hpet_readl(HPET_ID); 134 h = hpet_readl(HPET_PERIOD); 135 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 136 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 137 l = hpet_readl(HPET_CFG); 138 h = hpet_readl(HPET_STATUS); 139 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 140 l = hpet_readl(HPET_COUNTER); 141 h = hpet_readl(HPET_COUNTER+4); 142 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 143 144 for (i = 0; i < timers; i++) { 145 l = hpet_readl(HPET_Tn_CFG(i)); 146 h = hpet_readl(HPET_Tn_CFG(i)+4); 147 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 148 i, l, h); 149 l = hpet_readl(HPET_Tn_CMP(i)); 150 h = hpet_readl(HPET_Tn_CMP(i)+4); 151 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 152 i, l, h); 153 l = hpet_readl(HPET_Tn_ROUTE(i)); 154 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 155 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 156 i, l, h); 157 } 158 } 159 160 #define hpet_print_config() \ 161 do { \ 162 if (hpet_verbose) \ 163 _hpet_print_config(__FUNCTION__, __LINE__); \ 164 } while (0) 165 166 /* 167 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 168 * timer 0 and timer 1 in case of RTC emulation. 169 */ 170 #ifdef CONFIG_HPET 171 172 static void hpet_reserve_msi_timers(struct hpet_data *hd); 173 174 static void hpet_reserve_platform_timers(unsigned int id) 175 { 176 struct hpet __iomem *hpet = hpet_virt_address; 177 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 178 unsigned int nrtimers, i; 179 struct hpet_data hd; 180 181 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 182 183 memset(&hd, 0, sizeof(hd)); 184 hd.hd_phys_address = hpet_address; 185 hd.hd_address = hpet; 186 hd.hd_nirqs = nrtimers; 187 hpet_reserve_timer(&hd, 0); 188 189 #ifdef CONFIG_HPET_EMULATE_RTC 190 hpet_reserve_timer(&hd, 1); 191 #endif 192 193 /* 194 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 195 * is wrong for i8259!) not the output IRQ. Many BIOS writers 196 * don't bother configuring *any* comparator interrupts. 197 */ 198 hd.hd_irq[0] = HPET_LEGACY_8254; 199 hd.hd_irq[1] = HPET_LEGACY_RTC; 200 201 for (i = 2; i < nrtimers; timer++, i++) { 202 hd.hd_irq[i] = (readl(&timer->hpet_config) & 203 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 204 } 205 206 hpet_reserve_msi_timers(&hd); 207 208 hpet_alloc(&hd); 209 210 } 211 #else 212 static void hpet_reserve_platform_timers(unsigned int id) { } 213 #endif 214 215 /* 216 * Common hpet info 217 */ 218 static unsigned long hpet_period; 219 220 static void hpet_legacy_set_mode(enum clock_event_mode mode, 221 struct clock_event_device *evt); 222 static int hpet_legacy_next_event(unsigned long delta, 223 struct clock_event_device *evt); 224 225 /* 226 * The hpet clock event device 227 */ 228 static struct clock_event_device hpet_clockevent = { 229 .name = "hpet", 230 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 231 .set_mode = hpet_legacy_set_mode, 232 .set_next_event = hpet_legacy_next_event, 233 .shift = 32, 234 .irq = 0, 235 .rating = 50, 236 }; 237 238 static void hpet_stop_counter(void) 239 { 240 unsigned long cfg = hpet_readl(HPET_CFG); 241 cfg &= ~HPET_CFG_ENABLE; 242 hpet_writel(cfg, HPET_CFG); 243 } 244 245 static void hpet_reset_counter(void) 246 { 247 hpet_writel(0, HPET_COUNTER); 248 hpet_writel(0, HPET_COUNTER + 4); 249 } 250 251 static void hpet_start_counter(void) 252 { 253 unsigned int cfg = hpet_readl(HPET_CFG); 254 cfg |= HPET_CFG_ENABLE; 255 hpet_writel(cfg, HPET_CFG); 256 } 257 258 static void hpet_restart_counter(void) 259 { 260 hpet_stop_counter(); 261 hpet_reset_counter(); 262 hpet_start_counter(); 263 } 264 265 static void hpet_resume_device(void) 266 { 267 force_hpet_resume(); 268 } 269 270 static void hpet_resume_counter(struct clocksource *cs) 271 { 272 hpet_resume_device(); 273 hpet_restart_counter(); 274 } 275 276 static void hpet_enable_legacy_int(void) 277 { 278 unsigned int cfg = hpet_readl(HPET_CFG); 279 280 cfg |= HPET_CFG_LEGACY; 281 hpet_writel(cfg, HPET_CFG); 282 hpet_legacy_int_enabled = 1; 283 } 284 285 static void hpet_legacy_clockevent_register(void) 286 { 287 /* Start HPET legacy interrupts */ 288 hpet_enable_legacy_int(); 289 290 /* 291 * The mult factor is defined as (include/linux/clockchips.h) 292 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) 293 * hpet_period is in units of femtoseconds (per cycle), so 294 * mult/2^shift = cyc/ns = 10^6/hpet_period 295 * mult = (10^6 * 2^shift)/hpet_period 296 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period 297 */ 298 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, 299 hpet_period, hpet_clockevent.shift); 300 /* Calculate the min / max delta */ 301 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 302 &hpet_clockevent); 303 /* 5 usec minimum reprogramming delta. */ 304 hpet_clockevent.min_delta_ns = 5000; 305 306 /* 307 * Start hpet with the boot cpu mask and make it 308 * global after the IO_APIC has been initialized. 309 */ 310 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 311 clockevents_register_device(&hpet_clockevent); 312 global_clock_event = &hpet_clockevent; 313 printk(KERN_DEBUG "hpet clockevent registered\n"); 314 } 315 316 static int hpet_setup_msi_irq(unsigned int irq); 317 318 static void hpet_set_mode(enum clock_event_mode mode, 319 struct clock_event_device *evt, int timer) 320 { 321 unsigned int cfg, cmp, now; 322 uint64_t delta; 323 324 switch (mode) { 325 case CLOCK_EVT_MODE_PERIODIC: 326 hpet_stop_counter(); 327 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; 328 delta >>= evt->shift; 329 now = hpet_readl(HPET_COUNTER); 330 cmp = now + (unsigned int) delta; 331 cfg = hpet_readl(HPET_Tn_CFG(timer)); 332 /* Make sure we use edge triggered interrupts */ 333 cfg &= ~HPET_TN_LEVEL; 334 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 335 HPET_TN_SETVAL | HPET_TN_32BIT; 336 hpet_writel(cfg, HPET_Tn_CFG(timer)); 337 hpet_writel(cmp, HPET_Tn_CMP(timer)); 338 udelay(1); 339 /* 340 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 341 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 342 * bit is automatically cleared after the first write. 343 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 344 * Publication # 24674) 345 */ 346 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); 347 hpet_start_counter(); 348 hpet_print_config(); 349 break; 350 351 case CLOCK_EVT_MODE_ONESHOT: 352 cfg = hpet_readl(HPET_Tn_CFG(timer)); 353 cfg &= ~HPET_TN_PERIODIC; 354 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 355 hpet_writel(cfg, HPET_Tn_CFG(timer)); 356 break; 357 358 case CLOCK_EVT_MODE_UNUSED: 359 case CLOCK_EVT_MODE_SHUTDOWN: 360 cfg = hpet_readl(HPET_Tn_CFG(timer)); 361 cfg &= ~HPET_TN_ENABLE; 362 hpet_writel(cfg, HPET_Tn_CFG(timer)); 363 break; 364 365 case CLOCK_EVT_MODE_RESUME: 366 if (timer == 0) { 367 hpet_enable_legacy_int(); 368 } else { 369 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 370 hpet_setup_msi_irq(hdev->irq); 371 disable_irq(hdev->irq); 372 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 373 enable_irq(hdev->irq); 374 } 375 hpet_print_config(); 376 break; 377 } 378 } 379 380 static int hpet_next_event(unsigned long delta, 381 struct clock_event_device *evt, int timer) 382 { 383 u32 cnt; 384 385 cnt = hpet_readl(HPET_COUNTER); 386 cnt += (u32) delta; 387 hpet_writel(cnt, HPET_Tn_CMP(timer)); 388 389 /* 390 * We need to read back the CMP register on certain HPET 391 * implementations (ATI chipsets) which seem to delay the 392 * transfer of the compare register into the internal compare 393 * logic. With small deltas this might actually be too late as 394 * the counter could already be higher than the compare value 395 * at that point and we would wait for the next hpet interrupt 396 * forever. We found out that reading the CMP register back 397 * forces the transfer so we can rely on the comparison with 398 * the counter register below. 399 * 400 * That works fine on those ATI chipsets, but on newer Intel 401 * chipsets (ICH9...) this triggers due to an erratum: Reading 402 * the comparator immediately following a write is returning 403 * the old value. 404 * 405 * We restrict the read back to the affected ATI chipsets (set 406 * by quirks) and also run it with hpet=verbose for debugging 407 * purposes. 408 */ 409 if (hpet_readback_cmp || hpet_verbose) { 410 u32 cmp = hpet_readl(HPET_Tn_CMP(timer)); 411 412 if (cmp != cnt) 413 printk_once(KERN_WARNING 414 "hpet: compare register read back failed.\n"); 415 } 416 417 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; 418 } 419 420 static void hpet_legacy_set_mode(enum clock_event_mode mode, 421 struct clock_event_device *evt) 422 { 423 hpet_set_mode(mode, evt, 0); 424 } 425 426 static int hpet_legacy_next_event(unsigned long delta, 427 struct clock_event_device *evt) 428 { 429 return hpet_next_event(delta, evt, 0); 430 } 431 432 /* 433 * HPET MSI Support 434 */ 435 #ifdef CONFIG_PCI_MSI 436 437 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 438 static struct hpet_dev *hpet_devs; 439 440 void hpet_msi_unmask(unsigned int irq) 441 { 442 struct hpet_dev *hdev = get_irq_data(irq); 443 unsigned int cfg; 444 445 /* unmask it */ 446 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 447 cfg |= HPET_TN_FSB; 448 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 449 } 450 451 void hpet_msi_mask(unsigned int irq) 452 { 453 unsigned int cfg; 454 struct hpet_dev *hdev = get_irq_data(irq); 455 456 /* mask it */ 457 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 458 cfg &= ~HPET_TN_FSB; 459 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 460 } 461 462 void hpet_msi_write(unsigned int irq, struct msi_msg *msg) 463 { 464 struct hpet_dev *hdev = get_irq_data(irq); 465 466 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 467 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 468 } 469 470 void hpet_msi_read(unsigned int irq, struct msi_msg *msg) 471 { 472 struct hpet_dev *hdev = get_irq_data(irq); 473 474 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 475 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 476 msg->address_hi = 0; 477 } 478 479 static void hpet_msi_set_mode(enum clock_event_mode mode, 480 struct clock_event_device *evt) 481 { 482 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 483 hpet_set_mode(mode, evt, hdev->num); 484 } 485 486 static int hpet_msi_next_event(unsigned long delta, 487 struct clock_event_device *evt) 488 { 489 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 490 return hpet_next_event(delta, evt, hdev->num); 491 } 492 493 static int hpet_setup_msi_irq(unsigned int irq) 494 { 495 if (arch_setup_hpet_msi(irq, hpet_blockid)) { 496 destroy_irq(irq); 497 return -EINVAL; 498 } 499 return 0; 500 } 501 502 static int hpet_assign_irq(struct hpet_dev *dev) 503 { 504 unsigned int irq; 505 506 irq = create_irq(); 507 if (!irq) 508 return -EINVAL; 509 510 set_irq_data(irq, dev); 511 512 if (hpet_setup_msi_irq(irq)) 513 return -EINVAL; 514 515 dev->irq = irq; 516 return 0; 517 } 518 519 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 520 { 521 struct hpet_dev *dev = (struct hpet_dev *)data; 522 struct clock_event_device *hevt = &dev->evt; 523 524 if (!hevt->event_handler) { 525 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 526 dev->num); 527 return IRQ_HANDLED; 528 } 529 530 hevt->event_handler(hevt); 531 return IRQ_HANDLED; 532 } 533 534 static int hpet_setup_irq(struct hpet_dev *dev) 535 { 536 537 if (request_irq(dev->irq, hpet_interrupt_handler, 538 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, 539 dev->name, dev)) 540 return -1; 541 542 disable_irq(dev->irq); 543 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 544 enable_irq(dev->irq); 545 546 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 547 dev->name, dev->irq); 548 549 return 0; 550 } 551 552 /* This should be called in specific @cpu */ 553 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 554 { 555 struct clock_event_device *evt = &hdev->evt; 556 uint64_t hpet_freq; 557 558 WARN_ON(cpu != smp_processor_id()); 559 if (!(hdev->flags & HPET_DEV_VALID)) 560 return; 561 562 if (hpet_setup_msi_irq(hdev->irq)) 563 return; 564 565 hdev->cpu = cpu; 566 per_cpu(cpu_hpet_dev, cpu) = hdev; 567 evt->name = hdev->name; 568 hpet_setup_irq(hdev); 569 evt->irq = hdev->irq; 570 571 evt->rating = 110; 572 evt->features = CLOCK_EVT_FEAT_ONESHOT; 573 if (hdev->flags & HPET_DEV_PERI_CAP) 574 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 575 576 evt->set_mode = hpet_msi_set_mode; 577 evt->set_next_event = hpet_msi_next_event; 578 evt->shift = 32; 579 580 /* 581 * The period is a femto seconds value. We need to calculate the 582 * scaled math multiplication factor for nanosecond to hpet tick 583 * conversion. 584 */ 585 hpet_freq = FSEC_PER_SEC; 586 do_div(hpet_freq, hpet_period); 587 evt->mult = div_sc((unsigned long) hpet_freq, 588 NSEC_PER_SEC, evt->shift); 589 /* Calculate the max delta */ 590 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); 591 /* 5 usec minimum reprogramming delta. */ 592 evt->min_delta_ns = 5000; 593 594 evt->cpumask = cpumask_of(hdev->cpu); 595 clockevents_register_device(evt); 596 } 597 598 #ifdef CONFIG_HPET 599 /* Reserve at least one timer for userspace (/dev/hpet) */ 600 #define RESERVE_TIMERS 1 601 #else 602 #define RESERVE_TIMERS 0 603 #endif 604 605 static void hpet_msi_capability_lookup(unsigned int start_timer) 606 { 607 unsigned int id; 608 unsigned int num_timers; 609 unsigned int num_timers_used = 0; 610 int i; 611 612 if (hpet_msi_disable) 613 return; 614 615 if (boot_cpu_has(X86_FEATURE_ARAT)) 616 return; 617 id = hpet_readl(HPET_ID); 618 619 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 620 num_timers++; /* Value read out starts from 0 */ 621 hpet_print_config(); 622 623 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 624 if (!hpet_devs) 625 return; 626 627 hpet_num_timers = num_timers; 628 629 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 630 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 631 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 632 633 /* Only consider HPET timer with MSI support */ 634 if (!(cfg & HPET_TN_FSB_CAP)) 635 continue; 636 637 hdev->flags = 0; 638 if (cfg & HPET_TN_PERIODIC_CAP) 639 hdev->flags |= HPET_DEV_PERI_CAP; 640 hdev->num = i; 641 642 sprintf(hdev->name, "hpet%d", i); 643 if (hpet_assign_irq(hdev)) 644 continue; 645 646 hdev->flags |= HPET_DEV_FSB_CAP; 647 hdev->flags |= HPET_DEV_VALID; 648 num_timers_used++; 649 if (num_timers_used == num_possible_cpus()) 650 break; 651 } 652 653 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 654 num_timers, num_timers_used); 655 } 656 657 #ifdef CONFIG_HPET 658 static void hpet_reserve_msi_timers(struct hpet_data *hd) 659 { 660 int i; 661 662 if (!hpet_devs) 663 return; 664 665 for (i = 0; i < hpet_num_timers; i++) { 666 struct hpet_dev *hdev = &hpet_devs[i]; 667 668 if (!(hdev->flags & HPET_DEV_VALID)) 669 continue; 670 671 hd->hd_irq[hdev->num] = hdev->irq; 672 hpet_reserve_timer(hd, hdev->num); 673 } 674 } 675 #endif 676 677 static struct hpet_dev *hpet_get_unused_timer(void) 678 { 679 int i; 680 681 if (!hpet_devs) 682 return NULL; 683 684 for (i = 0; i < hpet_num_timers; i++) { 685 struct hpet_dev *hdev = &hpet_devs[i]; 686 687 if (!(hdev->flags & HPET_DEV_VALID)) 688 continue; 689 if (test_and_set_bit(HPET_DEV_USED_BIT, 690 (unsigned long *)&hdev->flags)) 691 continue; 692 return hdev; 693 } 694 return NULL; 695 } 696 697 struct hpet_work_struct { 698 struct delayed_work work; 699 struct completion complete; 700 }; 701 702 static void hpet_work(struct work_struct *w) 703 { 704 struct hpet_dev *hdev; 705 int cpu = smp_processor_id(); 706 struct hpet_work_struct *hpet_work; 707 708 hpet_work = container_of(w, struct hpet_work_struct, work.work); 709 710 hdev = hpet_get_unused_timer(); 711 if (hdev) 712 init_one_hpet_msi_clockevent(hdev, cpu); 713 714 complete(&hpet_work->complete); 715 } 716 717 static int hpet_cpuhp_notify(struct notifier_block *n, 718 unsigned long action, void *hcpu) 719 { 720 unsigned long cpu = (unsigned long)hcpu; 721 struct hpet_work_struct work; 722 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 723 724 switch (action & 0xf) { 725 case CPU_ONLINE: 726 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); 727 init_completion(&work.complete); 728 /* FIXME: add schedule_work_on() */ 729 schedule_delayed_work_on(cpu, &work.work, 0); 730 wait_for_completion(&work.complete); 731 destroy_timer_on_stack(&work.work.timer); 732 break; 733 case CPU_DEAD: 734 if (hdev) { 735 free_irq(hdev->irq, hdev); 736 hdev->flags &= ~HPET_DEV_USED; 737 per_cpu(cpu_hpet_dev, cpu) = NULL; 738 } 739 break; 740 } 741 return NOTIFY_OK; 742 } 743 #else 744 745 static int hpet_setup_msi_irq(unsigned int irq) 746 { 747 return 0; 748 } 749 static void hpet_msi_capability_lookup(unsigned int start_timer) 750 { 751 return; 752 } 753 754 #ifdef CONFIG_HPET 755 static void hpet_reserve_msi_timers(struct hpet_data *hd) 756 { 757 return; 758 } 759 #endif 760 761 static int hpet_cpuhp_notify(struct notifier_block *n, 762 unsigned long action, void *hcpu) 763 { 764 return NOTIFY_OK; 765 } 766 767 #endif 768 769 /* 770 * Clock source related code 771 */ 772 static cycle_t read_hpet(struct clocksource *cs) 773 { 774 return (cycle_t)hpet_readl(HPET_COUNTER); 775 } 776 777 #ifdef CONFIG_X86_64 778 static cycle_t __vsyscall_fn vread_hpet(void) 779 { 780 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); 781 } 782 #endif 783 784 static struct clocksource clocksource_hpet = { 785 .name = "hpet", 786 .rating = 250, 787 .read = read_hpet, 788 .mask = HPET_MASK, 789 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 790 .resume = hpet_resume_counter, 791 #ifdef CONFIG_X86_64 792 .vread = vread_hpet, 793 #endif 794 }; 795 796 static int hpet_clocksource_register(void) 797 { 798 u64 start, now; 799 u64 hpet_freq; 800 cycle_t t1; 801 802 /* Start the counter */ 803 hpet_restart_counter(); 804 805 /* Verify whether hpet counter works */ 806 t1 = hpet_readl(HPET_COUNTER); 807 rdtscll(start); 808 809 /* 810 * We don't know the TSC frequency yet, but waiting for 811 * 200000 TSC cycles is safe: 812 * 4 GHz == 50us 813 * 1 GHz == 200us 814 */ 815 do { 816 rep_nop(); 817 rdtscll(now); 818 } while ((now - start) < 200000UL); 819 820 if (t1 == hpet_readl(HPET_COUNTER)) { 821 printk(KERN_WARNING 822 "HPET counter not counting. HPET disabled\n"); 823 return -ENODEV; 824 } 825 826 /* 827 * The definition of mult is (include/linux/clocksource.h) 828 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc 829 * so we first need to convert hpet_period to ns/cyc units: 830 * mult/2^shift = ns/cyc = hpet_period/10^6 831 * mult = (hpet_period * 2^shift)/10^6 832 * mult = (hpet_period << shift)/FSEC_PER_NSEC 833 */ 834 835 /* Need to convert hpet_period (fsec/cyc) to cyc/sec: 836 * 837 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc) 838 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period 839 */ 840 hpet_freq = FSEC_PER_SEC; 841 do_div(hpet_freq, hpet_period); 842 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 843 844 return 0; 845 } 846 847 /** 848 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 849 */ 850 int __init hpet_enable(void) 851 { 852 unsigned int id; 853 int i; 854 855 if (!is_hpet_capable()) 856 return 0; 857 858 hpet_set_mapping(); 859 860 /* 861 * Read the period and check for a sane value: 862 */ 863 hpet_period = hpet_readl(HPET_PERIOD); 864 865 /* 866 * AMD SB700 based systems with spread spectrum enabled use a 867 * SMM based HPET emulation to provide proper frequency 868 * setting. The SMM code is initialized with the first HPET 869 * register access and takes some time to complete. During 870 * this time the config register reads 0xffffffff. We check 871 * for max. 1000 loops whether the config register reads a non 872 * 0xffffffff value to make sure that HPET is up and running 873 * before we go further. A counting loop is safe, as the HPET 874 * access takes thousands of CPU cycles. On non SB700 based 875 * machines this check is only done once and has no side 876 * effects. 877 */ 878 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 879 if (i == 1000) { 880 printk(KERN_WARNING 881 "HPET config register value = 0xFFFFFFFF. " 882 "Disabling HPET\n"); 883 goto out_nohpet; 884 } 885 } 886 887 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 888 goto out_nohpet; 889 890 /* 891 * Read the HPET ID register to retrieve the IRQ routing 892 * information and the number of channels 893 */ 894 id = hpet_readl(HPET_ID); 895 hpet_print_config(); 896 897 #ifdef CONFIG_HPET_EMULATE_RTC 898 /* 899 * The legacy routing mode needs at least two channels, tick timer 900 * and the rtc emulation channel. 901 */ 902 if (!(id & HPET_ID_NUMBER)) 903 goto out_nohpet; 904 #endif 905 906 if (hpet_clocksource_register()) 907 goto out_nohpet; 908 909 if (id & HPET_ID_LEGSUP) { 910 hpet_legacy_clockevent_register(); 911 return 1; 912 } 913 return 0; 914 915 out_nohpet: 916 hpet_clear_mapping(); 917 hpet_address = 0; 918 return 0; 919 } 920 921 /* 922 * Needs to be late, as the reserve_timer code calls kalloc ! 923 * 924 * Not a problem on i386 as hpet_enable is called from late_time_init, 925 * but on x86_64 it is necessary ! 926 */ 927 static __init int hpet_late_init(void) 928 { 929 int cpu; 930 931 if (boot_hpet_disable) 932 return -ENODEV; 933 934 if (!hpet_address) { 935 if (!force_hpet_address) 936 return -ENODEV; 937 938 hpet_address = force_hpet_address; 939 hpet_enable(); 940 } 941 942 if (!hpet_virt_address) 943 return -ENODEV; 944 945 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 946 hpet_msi_capability_lookup(2); 947 else 948 hpet_msi_capability_lookup(0); 949 950 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 951 hpet_print_config(); 952 953 if (hpet_msi_disable) 954 return 0; 955 956 if (boot_cpu_has(X86_FEATURE_ARAT)) 957 return 0; 958 959 for_each_online_cpu(cpu) { 960 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); 961 } 962 963 /* This notifier should be called after workqueue is ready */ 964 hotcpu_notifier(hpet_cpuhp_notify, -20); 965 966 return 0; 967 } 968 fs_initcall(hpet_late_init); 969 970 void hpet_disable(void) 971 { 972 if (is_hpet_capable() && hpet_virt_address) { 973 unsigned int cfg = hpet_readl(HPET_CFG); 974 975 if (hpet_legacy_int_enabled) { 976 cfg &= ~HPET_CFG_LEGACY; 977 hpet_legacy_int_enabled = 0; 978 } 979 cfg &= ~HPET_CFG_ENABLE; 980 hpet_writel(cfg, HPET_CFG); 981 } 982 } 983 984 #ifdef CONFIG_HPET_EMULATE_RTC 985 986 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 987 * is enabled, we support RTC interrupt functionality in software. 988 * RTC has 3 kinds of interrupts: 989 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 990 * is updated 991 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 992 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 993 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 994 * (1) and (2) above are implemented using polling at a frequency of 995 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 996 * overhead. (DEFAULT_RTC_INT_FREQ) 997 * For (3), we use interrupts at 64Hz or user specified periodic 998 * frequency, whichever is higher. 999 */ 1000 #include <linux/mc146818rtc.h> 1001 #include <linux/rtc.h> 1002 #include <asm/rtc.h> 1003 1004 #define DEFAULT_RTC_INT_FREQ 64 1005 #define DEFAULT_RTC_SHIFT 6 1006 #define RTC_NUM_INTS 1 1007 1008 static unsigned long hpet_rtc_flags; 1009 static int hpet_prev_update_sec; 1010 static struct rtc_time hpet_alarm_time; 1011 static unsigned long hpet_pie_count; 1012 static u32 hpet_t1_cmp; 1013 static u32 hpet_default_delta; 1014 static u32 hpet_pie_delta; 1015 static unsigned long hpet_pie_limit; 1016 1017 static rtc_irq_handler irq_handler; 1018 1019 /* 1020 * Check that the hpet counter c1 is ahead of the c2 1021 */ 1022 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1023 { 1024 return (s32)(c2 - c1) < 0; 1025 } 1026 1027 /* 1028 * Registers a IRQ handler. 1029 */ 1030 int hpet_register_irq_handler(rtc_irq_handler handler) 1031 { 1032 if (!is_hpet_enabled()) 1033 return -ENODEV; 1034 if (irq_handler) 1035 return -EBUSY; 1036 1037 irq_handler = handler; 1038 1039 return 0; 1040 } 1041 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1042 1043 /* 1044 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1045 * and does cleanup. 1046 */ 1047 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1048 { 1049 if (!is_hpet_enabled()) 1050 return; 1051 1052 irq_handler = NULL; 1053 hpet_rtc_flags = 0; 1054 } 1055 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1056 1057 /* 1058 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1059 * is not supported by all HPET implementations for timer 1. 1060 * 1061 * hpet_rtc_timer_init() is called when the rtc is initialized. 1062 */ 1063 int hpet_rtc_timer_init(void) 1064 { 1065 unsigned int cfg, cnt, delta; 1066 unsigned long flags; 1067 1068 if (!is_hpet_enabled()) 1069 return 0; 1070 1071 if (!hpet_default_delta) { 1072 uint64_t clc; 1073 1074 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1075 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1076 hpet_default_delta = clc; 1077 } 1078 1079 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1080 delta = hpet_default_delta; 1081 else 1082 delta = hpet_pie_delta; 1083 1084 local_irq_save(flags); 1085 1086 cnt = delta + hpet_readl(HPET_COUNTER); 1087 hpet_writel(cnt, HPET_T1_CMP); 1088 hpet_t1_cmp = cnt; 1089 1090 cfg = hpet_readl(HPET_T1_CFG); 1091 cfg &= ~HPET_TN_PERIODIC; 1092 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1093 hpet_writel(cfg, HPET_T1_CFG); 1094 1095 local_irq_restore(flags); 1096 1097 return 1; 1098 } 1099 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1100 1101 /* 1102 * The functions below are called from rtc driver. 1103 * Return 0 if HPET is not being used. 1104 * Otherwise do the necessary changes and return 1. 1105 */ 1106 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1107 { 1108 if (!is_hpet_enabled()) 1109 return 0; 1110 1111 hpet_rtc_flags &= ~bit_mask; 1112 return 1; 1113 } 1114 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1115 1116 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1117 { 1118 unsigned long oldbits = hpet_rtc_flags; 1119 1120 if (!is_hpet_enabled()) 1121 return 0; 1122 1123 hpet_rtc_flags |= bit_mask; 1124 1125 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1126 hpet_prev_update_sec = -1; 1127 1128 if (!oldbits) 1129 hpet_rtc_timer_init(); 1130 1131 return 1; 1132 } 1133 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1134 1135 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1136 unsigned char sec) 1137 { 1138 if (!is_hpet_enabled()) 1139 return 0; 1140 1141 hpet_alarm_time.tm_hour = hrs; 1142 hpet_alarm_time.tm_min = min; 1143 hpet_alarm_time.tm_sec = sec; 1144 1145 return 1; 1146 } 1147 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1148 1149 int hpet_set_periodic_freq(unsigned long freq) 1150 { 1151 uint64_t clc; 1152 1153 if (!is_hpet_enabled()) 1154 return 0; 1155 1156 if (freq <= DEFAULT_RTC_INT_FREQ) 1157 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1158 else { 1159 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1160 do_div(clc, freq); 1161 clc >>= hpet_clockevent.shift; 1162 hpet_pie_delta = clc; 1163 hpet_pie_limit = 0; 1164 } 1165 return 1; 1166 } 1167 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1168 1169 int hpet_rtc_dropped_irq(void) 1170 { 1171 return is_hpet_enabled(); 1172 } 1173 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1174 1175 static void hpet_rtc_timer_reinit(void) 1176 { 1177 unsigned int cfg, delta; 1178 int lost_ints = -1; 1179 1180 if (unlikely(!hpet_rtc_flags)) { 1181 cfg = hpet_readl(HPET_T1_CFG); 1182 cfg &= ~HPET_TN_ENABLE; 1183 hpet_writel(cfg, HPET_T1_CFG); 1184 return; 1185 } 1186 1187 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1188 delta = hpet_default_delta; 1189 else 1190 delta = hpet_pie_delta; 1191 1192 /* 1193 * Increment the comparator value until we are ahead of the 1194 * current count. 1195 */ 1196 do { 1197 hpet_t1_cmp += delta; 1198 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1199 lost_ints++; 1200 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1201 1202 if (lost_ints) { 1203 if (hpet_rtc_flags & RTC_PIE) 1204 hpet_pie_count += lost_ints; 1205 if (printk_ratelimit()) 1206 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1207 lost_ints); 1208 } 1209 } 1210 1211 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1212 { 1213 struct rtc_time curr_time; 1214 unsigned long rtc_int_flag = 0; 1215 1216 hpet_rtc_timer_reinit(); 1217 memset(&curr_time, 0, sizeof(struct rtc_time)); 1218 1219 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1220 get_rtc_time(&curr_time); 1221 1222 if (hpet_rtc_flags & RTC_UIE && 1223 curr_time.tm_sec != hpet_prev_update_sec) { 1224 if (hpet_prev_update_sec >= 0) 1225 rtc_int_flag = RTC_UF; 1226 hpet_prev_update_sec = curr_time.tm_sec; 1227 } 1228 1229 if (hpet_rtc_flags & RTC_PIE && 1230 ++hpet_pie_count >= hpet_pie_limit) { 1231 rtc_int_flag |= RTC_PF; 1232 hpet_pie_count = 0; 1233 } 1234 1235 if (hpet_rtc_flags & RTC_AIE && 1236 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1237 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1238 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1239 rtc_int_flag |= RTC_AF; 1240 1241 if (rtc_int_flag) { 1242 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1243 if (irq_handler) 1244 irq_handler(rtc_int_flag, dev_id); 1245 } 1246 return IRQ_HANDLED; 1247 } 1248 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1249 #endif 1250