1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/export.h> 5 #include <linux/delay.h> 6 #include <linux/hpet.h> 7 #include <linux/cpu.h> 8 #include <linux/irq.h> 9 10 #include <asm/cpuid.h> 11 #include <asm/irq_remapping.h> 12 #include <asm/hpet.h> 13 #include <asm/time.h> 14 #include <asm/mwait.h> 15 16 #undef pr_fmt 17 #define pr_fmt(fmt) "hpet: " fmt 18 19 enum hpet_mode { 20 HPET_MODE_UNUSED, 21 HPET_MODE_LEGACY, 22 HPET_MODE_CLOCKEVT, 23 HPET_MODE_DEVICE, 24 }; 25 26 struct hpet_channel { 27 struct clock_event_device evt; 28 unsigned int num; 29 unsigned int cpu; 30 unsigned int irq; 31 unsigned int in_use; 32 enum hpet_mode mode; 33 unsigned int boot_cfg; 34 char name[10]; 35 }; 36 37 struct hpet_base { 38 unsigned int nr_channels; 39 unsigned int nr_clockevents; 40 unsigned int boot_cfg; 41 struct hpet_channel *channels; 42 }; 43 44 #define HPET_MASK CLOCKSOURCE_MASK(32) 45 46 #define HPET_MIN_CYCLES 128 47 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) 48 49 /* 50 * HPET address is set in acpi/boot.c, when an ACPI entry exists 51 */ 52 unsigned long hpet_address; 53 u8 hpet_blockid; /* OS timer block num */ 54 bool hpet_msi_disable; 55 56 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_GENERIC_MSI_IRQ) 57 static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel); 58 static struct irq_domain *hpet_domain; 59 #endif 60 61 static void __iomem *hpet_virt_address; 62 63 static struct hpet_base hpet_base; 64 65 static bool hpet_legacy_int_enabled; 66 static unsigned long hpet_freq; 67 68 bool boot_hpet_disable; 69 bool hpet_force_user; 70 static bool hpet_verbose; 71 72 static inline 73 struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt) 74 { 75 return container_of(evt, struct hpet_channel, evt); 76 } 77 78 inline unsigned int hpet_readl(unsigned int a) 79 { 80 return readl(hpet_virt_address + a); 81 } 82 83 static inline void hpet_writel(unsigned int d, unsigned int a) 84 { 85 writel(d, hpet_virt_address + a); 86 } 87 88 static inline void hpet_set_mapping(void) 89 { 90 hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE); 91 } 92 93 static inline void hpet_clear_mapping(void) 94 { 95 iounmap(hpet_virt_address); 96 hpet_virt_address = NULL; 97 } 98 99 /* 100 * HPET command line enable / disable 101 */ 102 static int __init hpet_setup(char *str) 103 { 104 while (str) { 105 char *next = strchr(str, ','); 106 107 if (next) 108 *next++ = 0; 109 if (!strncmp("disable", str, 7)) 110 boot_hpet_disable = true; 111 if (!strncmp("force", str, 5)) 112 hpet_force_user = true; 113 if (!strncmp("verbose", str, 7)) 114 hpet_verbose = true; 115 str = next; 116 } 117 return 1; 118 } 119 __setup("hpet=", hpet_setup); 120 121 static int __init disable_hpet(char *str) 122 { 123 boot_hpet_disable = true; 124 return 1; 125 } 126 __setup("nohpet", disable_hpet); 127 128 static inline int is_hpet_capable(void) 129 { 130 return !boot_hpet_disable && hpet_address; 131 } 132 133 /** 134 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled 135 */ 136 int is_hpet_enabled(void) 137 { 138 return is_hpet_capable() && hpet_legacy_int_enabled; 139 } 140 EXPORT_SYMBOL_GPL(is_hpet_enabled); 141 142 static void _hpet_print_config(const char *function, int line) 143 { 144 u32 i, id, period, cfg, status, channels, l, h; 145 146 pr_info("%s(%d):\n", function, line); 147 148 id = hpet_readl(HPET_ID); 149 period = hpet_readl(HPET_PERIOD); 150 pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period); 151 152 cfg = hpet_readl(HPET_CFG); 153 status = hpet_readl(HPET_STATUS); 154 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); 155 156 l = hpet_readl(HPET_COUNTER); 157 h = hpet_readl(HPET_COUNTER+4); 158 pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 159 160 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 161 162 for (i = 0; i < channels; i++) { 163 l = hpet_readl(HPET_Tn_CFG(i)); 164 h = hpet_readl(HPET_Tn_CFG(i)+4); 165 pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h); 166 167 l = hpet_readl(HPET_Tn_CMP(i)); 168 h = hpet_readl(HPET_Tn_CMP(i)+4); 169 pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h); 170 171 l = hpet_readl(HPET_Tn_ROUTE(i)); 172 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 173 pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h); 174 } 175 } 176 177 #define hpet_print_config() \ 178 do { \ 179 if (hpet_verbose) \ 180 _hpet_print_config(__func__, __LINE__); \ 181 } while (0) 182 183 /* 184 * When the HPET driver (/dev/hpet) is enabled, we need to reserve 185 * timer 0 and timer 1 in case of RTC emulation. 186 */ 187 #ifdef CONFIG_HPET 188 189 static void __init hpet_reserve_platform_timers(void) 190 { 191 struct hpet_data hd; 192 unsigned int i; 193 194 memset(&hd, 0, sizeof(hd)); 195 hd.hd_phys_address = hpet_address; 196 hd.hd_address = hpet_virt_address; 197 hd.hd_nirqs = hpet_base.nr_channels; 198 199 /* 200 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 201 * is wrong for i8259!) not the output IRQ. Many BIOS writers 202 * don't bother configuring *any* comparator interrupts. 203 */ 204 hd.hd_irq[0] = HPET_LEGACY_8254; 205 hd.hd_irq[1] = HPET_LEGACY_RTC; 206 207 for (i = 0; i < hpet_base.nr_channels; i++) { 208 struct hpet_channel *hc = hpet_base.channels + i; 209 210 if (i >= 2) 211 hd.hd_irq[i] = hc->irq; 212 213 switch (hc->mode) { 214 case HPET_MODE_UNUSED: 215 case HPET_MODE_DEVICE: 216 hc->mode = HPET_MODE_DEVICE; 217 break; 218 case HPET_MODE_CLOCKEVT: 219 case HPET_MODE_LEGACY: 220 hpet_reserve_timer(&hd, hc->num); 221 break; 222 } 223 } 224 225 hpet_alloc(&hd); 226 } 227 228 static void __init hpet_select_device_channel(void) 229 { 230 int i; 231 232 for (i = 0; i < hpet_base.nr_channels; i++) { 233 struct hpet_channel *hc = hpet_base.channels + i; 234 235 /* Associate the first unused channel to /dev/hpet */ 236 if (hc->mode == HPET_MODE_UNUSED) { 237 hc->mode = HPET_MODE_DEVICE; 238 return; 239 } 240 } 241 } 242 243 #else 244 static inline void hpet_reserve_platform_timers(void) { } 245 static inline void hpet_select_device_channel(void) {} 246 #endif 247 248 /* Common HPET functions */ 249 static void hpet_stop_counter(void) 250 { 251 u32 cfg = hpet_readl(HPET_CFG); 252 253 cfg &= ~HPET_CFG_ENABLE; 254 hpet_writel(cfg, HPET_CFG); 255 } 256 257 static void hpet_reset_counter(void) 258 { 259 hpet_writel(0, HPET_COUNTER); 260 hpet_writel(0, HPET_COUNTER + 4); 261 } 262 263 static void hpet_start_counter(void) 264 { 265 unsigned int cfg = hpet_readl(HPET_CFG); 266 267 cfg |= HPET_CFG_ENABLE; 268 hpet_writel(cfg, HPET_CFG); 269 } 270 271 static void hpet_restart_counter(void) 272 { 273 hpet_stop_counter(); 274 hpet_reset_counter(); 275 hpet_start_counter(); 276 } 277 278 static void hpet_resume_device(void) 279 { 280 force_hpet_resume(); 281 } 282 283 static void hpet_resume_counter(struct clocksource *cs) 284 { 285 hpet_resume_device(); 286 hpet_restart_counter(); 287 } 288 289 static void hpet_enable_legacy_int(void) 290 { 291 unsigned int cfg = hpet_readl(HPET_CFG); 292 293 cfg |= HPET_CFG_LEGACY; 294 hpet_writel(cfg, HPET_CFG); 295 hpet_legacy_int_enabled = true; 296 } 297 298 static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) 299 { 300 unsigned int channel = clockevent_to_channel(evt)->num; 301 unsigned int cfg, cmp, now; 302 uint64_t delta; 303 304 hpet_stop_counter(); 305 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; 306 delta >>= evt->shift; 307 now = hpet_readl(HPET_COUNTER); 308 cmp = now + (unsigned int)delta; 309 cfg = hpet_readl(HPET_Tn_CFG(channel)); 310 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | 311 HPET_TN_32BIT; 312 hpet_writel(cfg, HPET_Tn_CFG(channel)); 313 hpet_writel(cmp, HPET_Tn_CMP(channel)); 314 udelay(1); 315 /* 316 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 317 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 318 * bit is automatically cleared after the first write. 319 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 320 * Publication # 24674) 321 */ 322 hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel)); 323 hpet_start_counter(); 324 hpet_print_config(); 325 326 return 0; 327 } 328 329 static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt) 330 { 331 unsigned int channel = clockevent_to_channel(evt)->num; 332 unsigned int cfg; 333 334 cfg = hpet_readl(HPET_Tn_CFG(channel)); 335 cfg &= ~HPET_TN_PERIODIC; 336 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 337 hpet_writel(cfg, HPET_Tn_CFG(channel)); 338 339 return 0; 340 } 341 342 static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt) 343 { 344 unsigned int channel = clockevent_to_channel(evt)->num; 345 unsigned int cfg; 346 347 cfg = hpet_readl(HPET_Tn_CFG(channel)); 348 cfg &= ~HPET_TN_ENABLE; 349 hpet_writel(cfg, HPET_Tn_CFG(channel)); 350 351 return 0; 352 } 353 354 static int hpet_clkevt_legacy_resume(struct clock_event_device *evt) 355 { 356 hpet_enable_legacy_int(); 357 hpet_print_config(); 358 return 0; 359 } 360 361 static int 362 hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt) 363 { 364 unsigned int channel = clockevent_to_channel(evt)->num; 365 u32 cnt; 366 s32 res; 367 368 cnt = hpet_readl(HPET_COUNTER); 369 cnt += (u32) delta; 370 hpet_writel(cnt, HPET_Tn_CMP(channel)); 371 372 /* 373 * HPETs are a complete disaster. The compare register is 374 * based on a equal comparison and neither provides a less 375 * than or equal functionality (which would require to take 376 * the wraparound into account) nor a simple count down event 377 * mode. Further the write to the comparator register is 378 * delayed internally up to two HPET clock cycles in certain 379 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even 380 * longer delays. We worked around that by reading back the 381 * compare register, but that required another workaround for 382 * ICH9,10 chips where the first readout after write can 383 * return the old stale value. We already had a minimum 384 * programming delta of 5us enforced, but a NMI or SMI hitting 385 * between the counter readout and the comparator write can 386 * move us behind that point easily. Now instead of reading 387 * the compare register back several times, we make the ETIME 388 * decision based on the following: Return ETIME if the 389 * counter value after the write is less than HPET_MIN_CYCLES 390 * away from the event or if the counter is already ahead of 391 * the event. The minimum programming delta for the generic 392 * clockevents code is set to 1.5 * HPET_MIN_CYCLES. 393 */ 394 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 395 396 return res < HPET_MIN_CYCLES ? -ETIME : 0; 397 } 398 399 static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating) 400 { 401 struct clock_event_device *evt = &hc->evt; 402 403 evt->rating = rating; 404 evt->irq = hc->irq; 405 evt->name = hc->name; 406 evt->cpumask = cpumask_of(hc->cpu); 407 evt->set_state_oneshot = hpet_clkevt_set_state_oneshot; 408 evt->set_next_event = hpet_clkevt_set_next_event; 409 evt->set_state_shutdown = hpet_clkevt_set_state_shutdown; 410 411 evt->features = CLOCK_EVT_FEAT_ONESHOT; 412 if (hc->boot_cfg & HPET_TN_PERIODIC) { 413 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 414 evt->set_state_periodic = hpet_clkevt_set_state_periodic; 415 } 416 } 417 418 static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc) 419 { 420 /* 421 * Start HPET with the boot CPU's cpumask and make it global after 422 * the IO_APIC has been initialized. 423 */ 424 hc->cpu = boot_cpu_data.cpu_index; 425 strscpy(hc->name, "hpet", sizeof(hc->name)); 426 hpet_init_clockevent(hc, 50); 427 428 hc->evt.tick_resume = hpet_clkevt_legacy_resume; 429 430 /* 431 * Legacy horrors and sins from the past. HPET used periodic mode 432 * unconditionally forever on the legacy channel 0. Removing the 433 * below hack and using the conditional in hpet_init_clockevent() 434 * makes at least Qemu and one hardware machine fail to boot. 435 * There are two issues which cause the boot failure: 436 * 437 * #1 After the timer delivery test in IOAPIC and the IOAPIC setup 438 * the next interrupt is not delivered despite the HPET channel 439 * being programmed correctly. Reprogramming the HPET after 440 * switching to IOAPIC makes it work again. After fixing this, 441 * the next issue surfaces: 442 * 443 * #2 Due to the unconditional periodic mode availability the Local 444 * APIC timer calibration can hijack the global clockevents 445 * event handler without causing damage. Using oneshot at this 446 * stage makes if hang because the HPET does not get 447 * reprogrammed due to the handler hijacking. Duh, stupid me! 448 * 449 * Both issues require major surgery and especially the kick HPET 450 * again after enabling IOAPIC results in really nasty hackery. 451 * This 'assume periodic works' magic has survived since HPET 452 * support got added, so it's questionable whether this should be 453 * fixed. Both Qemu and the failing hardware machine support 454 * periodic mode despite the fact that both don't advertise it in 455 * the configuration register and both need that extra kick after 456 * switching to IOAPIC. Seems to be a feature... 457 */ 458 hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC; 459 hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic; 460 461 /* Start HPET legacy interrupts */ 462 hpet_enable_legacy_int(); 463 464 clockevents_config_and_register(&hc->evt, hpet_freq, 465 HPET_MIN_PROG_DELTA, 0x7FFFFFFF); 466 global_clock_event = &hc->evt; 467 pr_debug("Clockevent registered\n"); 468 } 469 470 /* 471 * HPET MSI Support 472 */ 473 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_GENERIC_MSI_IRQ) 474 static void hpet_msi_unmask(struct irq_data *data) 475 { 476 struct hpet_channel *hc = irq_data_get_irq_handler_data(data); 477 unsigned int cfg; 478 479 cfg = hpet_readl(HPET_Tn_CFG(hc->num)); 480 cfg |= HPET_TN_ENABLE | HPET_TN_FSB; 481 hpet_writel(cfg, HPET_Tn_CFG(hc->num)); 482 } 483 484 static void hpet_msi_mask(struct irq_data *data) 485 { 486 struct hpet_channel *hc = irq_data_get_irq_handler_data(data); 487 unsigned int cfg; 488 489 cfg = hpet_readl(HPET_Tn_CFG(hc->num)); 490 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); 491 hpet_writel(cfg, HPET_Tn_CFG(hc->num)); 492 } 493 494 static void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg) 495 { 496 hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num)); 497 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4); 498 } 499 500 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) 501 { 502 hpet_msi_write(irq_data_get_irq_handler_data(data), msg); 503 } 504 505 static struct irq_chip hpet_msi_controller __ro_after_init = { 506 .name = "HPET-MSI", 507 .irq_unmask = hpet_msi_unmask, 508 .irq_mask = hpet_msi_mask, 509 .irq_ack = irq_chip_ack_parent, 510 .irq_set_affinity = msi_domain_set_affinity, 511 .irq_retrigger = irq_chip_retrigger_hierarchy, 512 .irq_write_msi_msg = hpet_msi_write_msg, 513 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, 514 }; 515 516 static int hpet_msi_init(struct irq_domain *domain, 517 struct msi_domain_info *info, unsigned int virq, 518 irq_hw_number_t hwirq, msi_alloc_info_t *arg) 519 { 520 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 521 irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL, 522 handle_edge_irq, arg->data, "edge"); 523 524 return 0; 525 } 526 527 static void hpet_msi_free(struct irq_domain *domain, 528 struct msi_domain_info *info, unsigned int virq) 529 { 530 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); 531 } 532 533 static struct msi_domain_ops hpet_msi_domain_ops = { 534 .msi_init = hpet_msi_init, 535 .msi_free = hpet_msi_free, 536 }; 537 538 static struct msi_domain_info hpet_msi_domain_info = { 539 .ops = &hpet_msi_domain_ops, 540 .chip = &hpet_msi_controller, 541 .flags = MSI_FLAG_USE_DEF_DOM_OPS, 542 }; 543 544 static struct irq_domain *hpet_create_irq_domain(int hpet_id) 545 { 546 struct msi_domain_info *domain_info; 547 struct irq_domain *parent, *d; 548 struct fwnode_handle *fn; 549 struct irq_fwspec fwspec; 550 551 if (x86_vector_domain == NULL) 552 return NULL; 553 554 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); 555 if (!domain_info) 556 return NULL; 557 558 *domain_info = hpet_msi_domain_info; 559 domain_info->data = (void *)(long)hpet_id; 560 561 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, 562 hpet_id); 563 if (!fn) { 564 kfree(domain_info); 565 return NULL; 566 } 567 568 fwspec.fwnode = fn; 569 fwspec.param_count = 1; 570 fwspec.param[0] = hpet_id; 571 572 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_GENERIC_MSI); 573 if (!parent) { 574 irq_domain_free_fwnode(fn); 575 kfree(domain_info); 576 return NULL; 577 } 578 if (parent != x86_vector_domain) 579 hpet_msi_controller.name = "IR-HPET-MSI"; 580 581 d = msi_create_irq_domain(fn, domain_info, parent); 582 if (!d) { 583 irq_domain_free_fwnode(fn); 584 kfree(domain_info); 585 } 586 return d; 587 } 588 589 static inline int hpet_dev_id(struct irq_domain *domain) 590 { 591 struct msi_domain_info *info = msi_get_domain_info(domain); 592 593 return (int)(long)info->data; 594 } 595 596 static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, 597 int dev_num) 598 { 599 struct irq_alloc_info info; 600 601 init_irq_alloc_info(&info, NULL); 602 info.type = X86_IRQ_ALLOC_TYPE_HPET; 603 info.data = hc; 604 info.devid = hpet_dev_id(domain); 605 info.hwirq = dev_num; 606 607 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 608 } 609 610 static int hpet_clkevt_msi_resume(struct clock_event_device *evt) 611 { 612 struct hpet_channel *hc = clockevent_to_channel(evt); 613 struct irq_data *data = irq_get_irq_data(hc->irq); 614 struct msi_msg msg; 615 616 /* Restore the MSI msg and unmask the interrupt */ 617 irq_chip_compose_msi_msg(data, &msg); 618 hpet_msi_write(hc, &msg); 619 hpet_msi_unmask(data); 620 return 0; 621 } 622 623 static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data) 624 { 625 struct hpet_channel *hc = data; 626 struct clock_event_device *evt = &hc->evt; 627 628 if (!evt->event_handler) { 629 pr_info("Spurious interrupt HPET channel %d\n", hc->num); 630 return IRQ_HANDLED; 631 } 632 633 evt->event_handler(evt); 634 return IRQ_HANDLED; 635 } 636 637 static int hpet_setup_msi_irq(struct hpet_channel *hc) 638 { 639 if (request_irq(hc->irq, hpet_msi_interrupt_handler, 640 IRQF_TIMER | IRQF_NOBALANCING, 641 hc->name, hc)) 642 return -1; 643 644 disable_irq(hc->irq); 645 irq_set_affinity(hc->irq, cpumask_of(hc->cpu)); 646 enable_irq(hc->irq); 647 648 pr_debug("%s irq %u for MSI\n", hc->name, hc->irq); 649 650 return 0; 651 } 652 653 /* Invoked from the hotplug callback on @cpu */ 654 static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu) 655 { 656 struct clock_event_device *evt = &hc->evt; 657 658 hc->cpu = cpu; 659 per_cpu(cpu_hpet_channel, cpu) = hc; 660 hpet_setup_msi_irq(hc); 661 662 hpet_init_clockevent(hc, 110); 663 evt->tick_resume = hpet_clkevt_msi_resume; 664 665 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, 666 0x7FFFFFFF); 667 } 668 669 static struct hpet_channel *hpet_get_unused_clockevent(void) 670 { 671 int i; 672 673 for (i = 0; i < hpet_base.nr_channels; i++) { 674 struct hpet_channel *hc = hpet_base.channels + i; 675 676 if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use) 677 continue; 678 hc->in_use = 1; 679 return hc; 680 } 681 return NULL; 682 } 683 684 static int hpet_cpuhp_online(unsigned int cpu) 685 { 686 struct hpet_channel *hc = hpet_get_unused_clockevent(); 687 688 if (hc) 689 init_one_hpet_msi_clockevent(hc, cpu); 690 return 0; 691 } 692 693 static int hpet_cpuhp_dead(unsigned int cpu) 694 { 695 struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu); 696 697 if (!hc) 698 return 0; 699 free_irq(hc->irq, hc); 700 hc->in_use = 0; 701 per_cpu(cpu_hpet_channel, cpu) = NULL; 702 return 0; 703 } 704 705 static void __init hpet_select_clockevents(void) 706 { 707 unsigned int i; 708 709 hpet_base.nr_clockevents = 0; 710 711 /* No point if MSI is disabled or CPU has an Always Running APIC Timer */ 712 if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT)) 713 return; 714 715 hpet_print_config(); 716 717 hpet_domain = hpet_create_irq_domain(hpet_blockid); 718 if (!hpet_domain) 719 return; 720 721 for (i = 0; i < hpet_base.nr_channels; i++) { 722 struct hpet_channel *hc = hpet_base.channels + i; 723 int irq; 724 725 if (hc->mode != HPET_MODE_UNUSED) 726 continue; 727 728 /* Only consider HPET channel with MSI support */ 729 if (!(hc->boot_cfg & HPET_TN_FSB_CAP)) 730 continue; 731 732 sprintf(hc->name, "hpet%d", i); 733 734 irq = hpet_assign_irq(hpet_domain, hc, hc->num); 735 if (irq <= 0) 736 continue; 737 738 hc->irq = irq; 739 hc->mode = HPET_MODE_CLOCKEVT; 740 741 if (++hpet_base.nr_clockevents == num_possible_cpus()) 742 break; 743 } 744 745 pr_info("%d channels of %d reserved for per-cpu timers\n", 746 hpet_base.nr_channels, hpet_base.nr_clockevents); 747 } 748 749 #else 750 751 static inline void hpet_select_clockevents(void) { } 752 753 #define hpet_cpuhp_online NULL 754 #define hpet_cpuhp_dead NULL 755 756 #endif 757 758 /* 759 * Clock source related code 760 */ 761 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) 762 /* 763 * Reading the HPET counter is a very slow operation. If a large number of 764 * CPUs are trying to access the HPET counter simultaneously, it can cause 765 * massive delays and slow down system performance dramatically. This may 766 * happen when HPET is the default clock source instead of TSC. For a 767 * really large system with hundreds of CPUs, the slowdown may be so 768 * severe, that it can actually crash the system because of a NMI watchdog 769 * soft lockup, for example. 770 * 771 * If multiple CPUs are trying to access the HPET counter at the same time, 772 * we don't actually need to read the counter multiple times. Instead, the 773 * other CPUs can use the counter value read by the first CPU in the group. 774 * 775 * This special feature is only enabled on x86-64 systems. It is unlikely 776 * that 32-bit x86 systems will have enough CPUs to require this feature 777 * with its associated locking overhead. We also need 64-bit atomic read. 778 * 779 * The lock and the HPET value are stored together and can be read in a 780 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t 781 * is 32 bits in size. 782 */ 783 union hpet_lock { 784 struct { 785 arch_spinlock_t lock; 786 u32 value; 787 }; 788 u64 lockval; 789 }; 790 791 static union hpet_lock hpet __cacheline_aligned = { 792 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, }, 793 }; 794 795 static u64 read_hpet(struct clocksource *cs) 796 { 797 unsigned long flags; 798 union hpet_lock old, new; 799 800 BUILD_BUG_ON(sizeof(union hpet_lock) != 8); 801 802 /* 803 * Read HPET directly if in NMI. 804 */ 805 if (in_nmi()) 806 return (u64)hpet_readl(HPET_COUNTER); 807 808 /* 809 * Read the current state of the lock and HPET value atomically. 810 */ 811 old.lockval = READ_ONCE(hpet.lockval); 812 813 if (arch_spin_is_locked(&old.lock)) 814 goto contended; 815 816 local_irq_save(flags); 817 if (arch_spin_trylock(&hpet.lock)) { 818 new.value = hpet_readl(HPET_COUNTER); 819 /* 820 * Use WRITE_ONCE() to prevent store tearing. 821 */ 822 WRITE_ONCE(hpet.value, new.value); 823 arch_spin_unlock(&hpet.lock); 824 local_irq_restore(flags); 825 return (u64)new.value; 826 } 827 local_irq_restore(flags); 828 829 contended: 830 /* 831 * Contended case 832 * -------------- 833 * Wait until the HPET value change or the lock is free to indicate 834 * its value is up-to-date. 835 * 836 * It is possible that old.value has already contained the latest 837 * HPET value while the lock holder was in the process of releasing 838 * the lock. Checking for lock state change will enable us to return 839 * the value immediately instead of waiting for the next HPET reader 840 * to come along. 841 */ 842 do { 843 cpu_relax(); 844 new.lockval = READ_ONCE(hpet.lockval); 845 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock)); 846 847 return (u64)new.value; 848 } 849 #else 850 /* 851 * For UP or 32-bit. 852 */ 853 static u64 read_hpet(struct clocksource *cs) 854 { 855 return (u64)hpet_readl(HPET_COUNTER); 856 } 857 #endif 858 859 static struct clocksource clocksource_hpet = { 860 .name = "hpet", 861 .rating = 250, 862 .read = read_hpet, 863 .mask = HPET_MASK, 864 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 865 .resume = hpet_resume_counter, 866 }; 867 868 /* 869 * AMD SB700 based systems with spread spectrum enabled use a SMM based 870 * HPET emulation to provide proper frequency setting. 871 * 872 * On such systems the SMM code is initialized with the first HPET register 873 * access and takes some time to complete. During this time the config 874 * register reads 0xffffffff. We check for max 1000 loops whether the 875 * config register reads a non-0xffffffff value to make sure that the 876 * HPET is up and running before we proceed any further. 877 * 878 * A counting loop is safe, as the HPET access takes thousands of CPU cycles. 879 * 880 * On non-SB700 based machines this check is only done once and has no 881 * side effects. 882 */ 883 static bool __init hpet_cfg_working(void) 884 { 885 int i; 886 887 for (i = 0; i < 1000; i++) { 888 if (hpet_readl(HPET_CFG) != 0xFFFFFFFF) 889 return true; 890 } 891 892 pr_warn("Config register invalid. Disabling HPET\n"); 893 return false; 894 } 895 896 static bool __init hpet_counting(void) 897 { 898 u64 start, now, t1; 899 900 hpet_restart_counter(); 901 902 t1 = hpet_readl(HPET_COUNTER); 903 start = rdtsc(); 904 905 /* 906 * We don't know the TSC frequency yet, but waiting for 907 * 200000 TSC cycles is safe: 908 * 4 GHz == 50us 909 * 1 GHz == 200us 910 */ 911 do { 912 if (t1 != hpet_readl(HPET_COUNTER)) 913 return true; 914 now = rdtsc(); 915 } while ((now - start) < 200000UL); 916 917 pr_warn("Counter not counting. HPET disabled\n"); 918 return false; 919 } 920 921 static bool __init mwait_pc10_supported(void) 922 { 923 unsigned int eax, ebx, ecx, mwait_substates; 924 925 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 926 return false; 927 928 if (!cpu_feature_enabled(X86_FEATURE_MWAIT)) 929 return false; 930 931 cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &mwait_substates); 932 933 return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) && 934 (ecx & CPUID5_ECX_INTERRUPT_BREAK) && 935 (mwait_substates & (0xF << 28)); 936 } 937 938 /* 939 * Check whether the system supports PC10. If so force disable HPET as that 940 * stops counting in PC10. This check is overbroad as it does not take any 941 * of the following into account: 942 * 943 * - ACPI tables 944 * - Enablement of intel_idle 945 * - Command line arguments which limit intel_idle C-state support 946 * 947 * That's perfectly fine. HPET is a piece of hardware designed by committee 948 * and the only reasons why it is still in use on modern systems is the 949 * fact that it is impossible to reliably query TSC and CPU frequency via 950 * CPUID or firmware. 951 * 952 * If HPET is functional it is useful for calibrating TSC, but this can be 953 * done via PMTIMER as well which seems to be the last remaining timer on 954 * X86/INTEL platforms that has not been completely wreckaged by feature 955 * creep. 956 * 957 * In theory HPET support should be removed altogether, but there are older 958 * systems out there which depend on it because TSC and APIC timer are 959 * dysfunctional in deeper C-states. 960 * 961 * It's only 20 years now that hardware people have been asked to provide 962 * reliable and discoverable facilities which can be used for timekeeping 963 * and per CPU timer interrupts. 964 * 965 * The probability that this problem is going to be solved in the 966 * foreseeable future is close to zero, so the kernel has to be cluttered 967 * with heuristics to keep up with the ever growing amount of hardware and 968 * firmware trainwrecks. Hopefully some day hardware people will understand 969 * that the approach of "This can be fixed in software" is not sustainable. 970 * Hope dies last... 971 */ 972 static bool __init hpet_is_pc10_damaged(void) 973 { 974 unsigned long long pcfg; 975 976 /* Check whether PC10 substates are supported */ 977 if (!mwait_pc10_supported()) 978 return false; 979 980 /* Check whether PC10 is enabled in PKG C-state limit */ 981 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg); 982 if ((pcfg & 0xF) < 8) 983 return false; 984 985 if (hpet_force_user) { 986 pr_warn("HPET force enabled via command line, but dysfunctional in PC10.\n"); 987 return false; 988 } 989 990 pr_info("HPET dysfunctional in PC10. Force disabled.\n"); 991 boot_hpet_disable = true; 992 return true; 993 } 994 995 /** 996 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 997 */ 998 int __init hpet_enable(void) 999 { 1000 u32 hpet_period, cfg, id, irq; 1001 unsigned int i, channels; 1002 struct hpet_channel *hc; 1003 u64 freq; 1004 1005 if (!is_hpet_capable()) 1006 return 0; 1007 1008 if (hpet_is_pc10_damaged()) 1009 return 0; 1010 1011 hpet_set_mapping(); 1012 if (!hpet_virt_address) 1013 return 0; 1014 1015 /* Validate that the config register is working */ 1016 if (!hpet_cfg_working()) 1017 goto out_nohpet; 1018 1019 /* 1020 * Read the period and check for a sane value: 1021 */ 1022 hpet_period = hpet_readl(HPET_PERIOD); 1023 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 1024 goto out_nohpet; 1025 1026 /* The period is a femtoseconds value. Convert it to a frequency. */ 1027 freq = FSEC_PER_SEC; 1028 do_div(freq, hpet_period); 1029 hpet_freq = freq; 1030 1031 /* 1032 * Read the HPET ID register to retrieve the IRQ routing 1033 * information and the number of channels 1034 */ 1035 id = hpet_readl(HPET_ID); 1036 hpet_print_config(); 1037 1038 /* This is the HPET channel number which is zero based */ 1039 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 1040 1041 /* 1042 * The legacy routing mode needs at least two channels, tick timer 1043 * and the rtc emulation channel. 1044 */ 1045 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2) 1046 goto out_nohpet; 1047 1048 hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL); 1049 if (!hc) { 1050 pr_warn("Disabling HPET.\n"); 1051 goto out_nohpet; 1052 } 1053 hpet_base.channels = hc; 1054 hpet_base.nr_channels = channels; 1055 1056 /* Read, store and sanitize the global configuration */ 1057 cfg = hpet_readl(HPET_CFG); 1058 hpet_base.boot_cfg = cfg; 1059 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); 1060 hpet_writel(cfg, HPET_CFG); 1061 if (cfg) 1062 pr_warn("Global config: Unknown bits %#x\n", cfg); 1063 1064 /* Read, store and sanitize the per channel configuration */ 1065 for (i = 0; i < channels; i++, hc++) { 1066 hc->num = i; 1067 1068 cfg = hpet_readl(HPET_Tn_CFG(i)); 1069 hc->boot_cfg = cfg; 1070 irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 1071 hc->irq = irq; 1072 1073 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); 1074 hpet_writel(cfg, HPET_Tn_CFG(i)); 1075 1076 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP 1077 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE 1078 | HPET_TN_FSB | HPET_TN_FSB_CAP); 1079 if (cfg) 1080 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg); 1081 } 1082 hpet_print_config(); 1083 1084 /* 1085 * Validate that the counter is counting. This needs to be done 1086 * after sanitizing the config registers to properly deal with 1087 * force enabled HPETs. 1088 */ 1089 if (!hpet_counting()) 1090 goto out_nohpet; 1091 1092 if (tsc_clocksource_watchdog_disabled()) 1093 clocksource_hpet.flags |= CLOCK_SOURCE_MUST_VERIFY; 1094 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 1095 1096 if (id & HPET_ID_LEGSUP) { 1097 hpet_legacy_clockevent_register(&hpet_base.channels[0]); 1098 hpet_base.channels[0].mode = HPET_MODE_LEGACY; 1099 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC)) 1100 hpet_base.channels[1].mode = HPET_MODE_LEGACY; 1101 return 1; 1102 } 1103 return 0; 1104 1105 out_nohpet: 1106 kfree(hpet_base.channels); 1107 hpet_base.channels = NULL; 1108 hpet_base.nr_channels = 0; 1109 hpet_clear_mapping(); 1110 hpet_address = 0; 1111 return 0; 1112 } 1113 1114 /* 1115 * The late initialization runs after the PCI quirks have been invoked 1116 * which might have detected a system on which the HPET can be enforced. 1117 * 1118 * Also, the MSI machinery is not working yet when the HPET is initialized 1119 * early. 1120 * 1121 * If the HPET is enabled, then: 1122 * 1123 * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y 1124 * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents 1125 * 3) Setup /dev/hpet if CONFIG_HPET=y 1126 * 4) Register hotplug callbacks when clockevents are available 1127 */ 1128 static __init int hpet_late_init(void) 1129 { 1130 int ret; 1131 1132 if (!hpet_address) { 1133 if (!force_hpet_address) 1134 return -ENODEV; 1135 1136 hpet_address = force_hpet_address; 1137 hpet_enable(); 1138 } 1139 1140 if (!hpet_virt_address) 1141 return -ENODEV; 1142 1143 hpet_select_device_channel(); 1144 hpet_select_clockevents(); 1145 hpet_reserve_platform_timers(); 1146 hpet_print_config(); 1147 1148 if (!hpet_base.nr_clockevents) 1149 return 0; 1150 1151 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online", 1152 hpet_cpuhp_online, NULL); 1153 if (ret) 1154 return ret; 1155 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL, 1156 hpet_cpuhp_dead); 1157 if (ret) 1158 goto err_cpuhp; 1159 return 0; 1160 1161 err_cpuhp: 1162 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); 1163 return ret; 1164 } 1165 fs_initcall(hpet_late_init); 1166 1167 void hpet_disable(void) 1168 { 1169 unsigned int i; 1170 u32 cfg; 1171 1172 if (!is_hpet_capable() || !hpet_virt_address) 1173 return; 1174 1175 /* Restore boot configuration with the enable bit cleared */ 1176 cfg = hpet_base.boot_cfg; 1177 cfg &= ~HPET_CFG_ENABLE; 1178 hpet_writel(cfg, HPET_CFG); 1179 1180 /* Restore the channel boot configuration */ 1181 for (i = 0; i < hpet_base.nr_channels; i++) 1182 hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i)); 1183 1184 /* If the HPET was enabled at boot time, reenable it */ 1185 if (hpet_base.boot_cfg & HPET_CFG_ENABLE) 1186 hpet_writel(hpet_base.boot_cfg, HPET_CFG); 1187 } 1188 1189 #ifdef CONFIG_HPET_EMULATE_RTC 1190 1191 /* 1192 * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET 1193 * is enabled, we support RTC interrupt functionality in software. 1194 * 1195 * RTC has 3 kinds of interrupts: 1196 * 1197 * 1) Update Interrupt - generate an interrupt, every second, when the 1198 * RTC clock is updated 1199 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 1200 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 1201 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2) 1202 * 1203 * (1) and (2) above are implemented using polling at a frequency of 64 Hz: 1204 * DEFAULT_RTC_INT_FREQ. 1205 * 1206 * The exact frequency is a tradeoff between accuracy and interrupt overhead. 1207 * 1208 * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency, 1209 * if it's higher. 1210 */ 1211 #include <linux/mc146818rtc.h> 1212 #include <linux/rtc.h> 1213 1214 #define DEFAULT_RTC_INT_FREQ 64 1215 #define DEFAULT_RTC_SHIFT 6 1216 #define RTC_NUM_INTS 1 1217 1218 static unsigned long hpet_rtc_flags; 1219 static int hpet_prev_update_sec; 1220 static struct rtc_time hpet_alarm_time; 1221 static unsigned long hpet_pie_count; 1222 static u32 hpet_t1_cmp; 1223 static u32 hpet_default_delta; 1224 static u32 hpet_pie_delta; 1225 static unsigned long hpet_pie_limit; 1226 1227 static rtc_irq_handler irq_handler; 1228 1229 /* 1230 * Check that the HPET counter c1 is ahead of c2 1231 */ 1232 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1233 { 1234 return (s32)(c2 - c1) < 0; 1235 } 1236 1237 /* 1238 * Registers a IRQ handler. 1239 */ 1240 int hpet_register_irq_handler(rtc_irq_handler handler) 1241 { 1242 if (!is_hpet_enabled()) 1243 return -ENODEV; 1244 if (irq_handler) 1245 return -EBUSY; 1246 1247 irq_handler = handler; 1248 1249 return 0; 1250 } 1251 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1252 1253 /* 1254 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1255 * and does cleanup. 1256 */ 1257 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1258 { 1259 if (!is_hpet_enabled()) 1260 return; 1261 1262 irq_handler = NULL; 1263 hpet_rtc_flags = 0; 1264 } 1265 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1266 1267 /* 1268 * Channel 1 for RTC emulation. We use one shot mode, as periodic mode 1269 * is not supported by all HPET implementations for channel 1. 1270 * 1271 * hpet_rtc_timer_init() is called when the rtc is initialized. 1272 */ 1273 int hpet_rtc_timer_init(void) 1274 { 1275 unsigned int cfg, cnt, delta; 1276 unsigned long flags; 1277 1278 if (!is_hpet_enabled()) 1279 return 0; 1280 1281 if (!hpet_default_delta) { 1282 struct clock_event_device *evt = &hpet_base.channels[0].evt; 1283 uint64_t clc; 1284 1285 clc = (uint64_t) evt->mult * NSEC_PER_SEC; 1286 clc >>= evt->shift + DEFAULT_RTC_SHIFT; 1287 hpet_default_delta = clc; 1288 } 1289 1290 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1291 delta = hpet_default_delta; 1292 else 1293 delta = hpet_pie_delta; 1294 1295 local_irq_save(flags); 1296 1297 cnt = delta + hpet_readl(HPET_COUNTER); 1298 hpet_writel(cnt, HPET_T1_CMP); 1299 hpet_t1_cmp = cnt; 1300 1301 cfg = hpet_readl(HPET_T1_CFG); 1302 cfg &= ~HPET_TN_PERIODIC; 1303 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1304 hpet_writel(cfg, HPET_T1_CFG); 1305 1306 local_irq_restore(flags); 1307 1308 return 1; 1309 } 1310 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1311 1312 static void hpet_disable_rtc_channel(void) 1313 { 1314 u32 cfg = hpet_readl(HPET_T1_CFG); 1315 1316 cfg &= ~HPET_TN_ENABLE; 1317 hpet_writel(cfg, HPET_T1_CFG); 1318 } 1319 1320 /* 1321 * The functions below are called from rtc driver. 1322 * Return 0 if HPET is not being used. 1323 * Otherwise do the necessary changes and return 1. 1324 */ 1325 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1326 { 1327 if (!is_hpet_enabled()) 1328 return 0; 1329 1330 hpet_rtc_flags &= ~bit_mask; 1331 if (unlikely(!hpet_rtc_flags)) 1332 hpet_disable_rtc_channel(); 1333 1334 return 1; 1335 } 1336 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1337 1338 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1339 { 1340 unsigned long oldbits = hpet_rtc_flags; 1341 1342 if (!is_hpet_enabled()) 1343 return 0; 1344 1345 hpet_rtc_flags |= bit_mask; 1346 1347 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1348 hpet_prev_update_sec = -1; 1349 1350 if (!oldbits) 1351 hpet_rtc_timer_init(); 1352 1353 return 1; 1354 } 1355 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1356 1357 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) 1358 { 1359 if (!is_hpet_enabled()) 1360 return 0; 1361 1362 hpet_alarm_time.tm_hour = hrs; 1363 hpet_alarm_time.tm_min = min; 1364 hpet_alarm_time.tm_sec = sec; 1365 1366 return 1; 1367 } 1368 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1369 1370 int hpet_set_periodic_freq(unsigned long freq) 1371 { 1372 uint64_t clc; 1373 1374 if (!is_hpet_enabled()) 1375 return 0; 1376 1377 if (freq <= DEFAULT_RTC_INT_FREQ) { 1378 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1379 } else { 1380 struct clock_event_device *evt = &hpet_base.channels[0].evt; 1381 1382 clc = (uint64_t) evt->mult * NSEC_PER_SEC; 1383 do_div(clc, freq); 1384 clc >>= evt->shift; 1385 hpet_pie_delta = clc; 1386 hpet_pie_limit = 0; 1387 } 1388 1389 return 1; 1390 } 1391 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1392 1393 int hpet_rtc_dropped_irq(void) 1394 { 1395 return is_hpet_enabled(); 1396 } 1397 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1398 1399 static void hpet_rtc_timer_reinit(void) 1400 { 1401 unsigned int delta; 1402 int lost_ints = -1; 1403 1404 if (unlikely(!hpet_rtc_flags)) 1405 hpet_disable_rtc_channel(); 1406 1407 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1408 delta = hpet_default_delta; 1409 else 1410 delta = hpet_pie_delta; 1411 1412 /* 1413 * Increment the comparator value until we are ahead of the 1414 * current count. 1415 */ 1416 do { 1417 hpet_t1_cmp += delta; 1418 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1419 lost_ints++; 1420 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1421 1422 if (lost_ints) { 1423 if (hpet_rtc_flags & RTC_PIE) 1424 hpet_pie_count += lost_ints; 1425 if (printk_ratelimit()) 1426 pr_warn("Lost %d RTC interrupts\n", lost_ints); 1427 } 1428 } 1429 1430 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1431 { 1432 struct rtc_time curr_time; 1433 unsigned long rtc_int_flag = 0; 1434 1435 hpet_rtc_timer_reinit(); 1436 memset(&curr_time, 0, sizeof(struct rtc_time)); 1437 1438 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) { 1439 if (unlikely(mc146818_get_time(&curr_time, 10) < 0)) { 1440 pr_err_ratelimited("unable to read current time from RTC\n"); 1441 return IRQ_HANDLED; 1442 } 1443 } 1444 1445 if (hpet_rtc_flags & RTC_UIE && 1446 curr_time.tm_sec != hpet_prev_update_sec) { 1447 if (hpet_prev_update_sec >= 0) 1448 rtc_int_flag = RTC_UF; 1449 hpet_prev_update_sec = curr_time.tm_sec; 1450 } 1451 1452 if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) { 1453 rtc_int_flag |= RTC_PF; 1454 hpet_pie_count = 0; 1455 } 1456 1457 if (hpet_rtc_flags & RTC_AIE && 1458 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1459 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1460 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1461 rtc_int_flag |= RTC_AF; 1462 1463 if (rtc_int_flag) { 1464 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1465 if (irq_handler) 1466 irq_handler(rtc_int_flag, dev_id); 1467 } 1468 return IRQ_HANDLED; 1469 } 1470 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1471 #endif 1472