1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/sysdev.h> 5 #include <linux/delay.h> 6 #include <linux/errno.h> 7 #include <linux/slab.h> 8 #include <linux/hpet.h> 9 #include <linux/init.h> 10 #include <linux/cpu.h> 11 #include <linux/pm.h> 12 #include <linux/io.h> 13 14 #include <asm/fixmap.h> 15 #include <asm/i8253.h> 16 #include <asm/hpet.h> 17 18 #define HPET_MASK CLOCKSOURCE_MASK(32) 19 20 /* FSEC = 10^-15 21 NSEC = 10^-9 */ 22 #define FSEC_PER_NSEC 1000000L 23 24 #define HPET_DEV_USED_BIT 2 25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 26 #define HPET_DEV_VALID 0x8 27 #define HPET_DEV_FSB_CAP 0x1000 28 #define HPET_DEV_PERI_CAP 0x2000 29 30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) 31 32 /* 33 * HPET address is set in acpi/boot.c, when an ACPI entry exists 34 */ 35 unsigned long hpet_address; 36 u8 hpet_blockid; /* OS timer block num */ 37 u8 hpet_msi_disable; 38 39 #ifdef CONFIG_PCI_MSI 40 static unsigned long hpet_num_timers; 41 #endif 42 static void __iomem *hpet_virt_address; 43 44 struct hpet_dev { 45 struct clock_event_device evt; 46 unsigned int num; 47 int cpu; 48 unsigned int irq; 49 unsigned int flags; 50 char name[10]; 51 }; 52 53 inline unsigned int hpet_readl(unsigned int a) 54 { 55 return readl(hpet_virt_address + a); 56 } 57 58 static inline void hpet_writel(unsigned int d, unsigned int a) 59 { 60 writel(d, hpet_virt_address + a); 61 } 62 63 #ifdef CONFIG_X86_64 64 #include <asm/pgtable.h> 65 #endif 66 67 static inline void hpet_set_mapping(void) 68 { 69 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 70 #ifdef CONFIG_X86_64 71 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); 72 #endif 73 } 74 75 static inline void hpet_clear_mapping(void) 76 { 77 iounmap(hpet_virt_address); 78 hpet_virt_address = NULL; 79 } 80 81 /* 82 * HPET command line enable / disable 83 */ 84 static int boot_hpet_disable; 85 int hpet_force_user; 86 static int hpet_verbose; 87 88 static int __init hpet_setup(char *str) 89 { 90 if (str) { 91 if (!strncmp("disable", str, 7)) 92 boot_hpet_disable = 1; 93 if (!strncmp("force", str, 5)) 94 hpet_force_user = 1; 95 if (!strncmp("verbose", str, 7)) 96 hpet_verbose = 1; 97 } 98 return 1; 99 } 100 __setup("hpet=", hpet_setup); 101 102 static int __init disable_hpet(char *str) 103 { 104 boot_hpet_disable = 1; 105 return 1; 106 } 107 __setup("nohpet", disable_hpet); 108 109 static inline int is_hpet_capable(void) 110 { 111 return !boot_hpet_disable && hpet_address; 112 } 113 114 /* 115 * HPET timer interrupt enable / disable 116 */ 117 static int hpet_legacy_int_enabled; 118 119 /** 120 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 121 */ 122 int is_hpet_enabled(void) 123 { 124 return is_hpet_capable() && hpet_legacy_int_enabled; 125 } 126 EXPORT_SYMBOL_GPL(is_hpet_enabled); 127 128 static void _hpet_print_config(const char *function, int line) 129 { 130 u32 i, timers, l, h; 131 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 132 l = hpet_readl(HPET_ID); 133 h = hpet_readl(HPET_PERIOD); 134 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 135 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 136 l = hpet_readl(HPET_CFG); 137 h = hpet_readl(HPET_STATUS); 138 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 139 l = hpet_readl(HPET_COUNTER); 140 h = hpet_readl(HPET_COUNTER+4); 141 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 142 143 for (i = 0; i < timers; i++) { 144 l = hpet_readl(HPET_Tn_CFG(i)); 145 h = hpet_readl(HPET_Tn_CFG(i)+4); 146 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 147 i, l, h); 148 l = hpet_readl(HPET_Tn_CMP(i)); 149 h = hpet_readl(HPET_Tn_CMP(i)+4); 150 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 151 i, l, h); 152 l = hpet_readl(HPET_Tn_ROUTE(i)); 153 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 154 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 155 i, l, h); 156 } 157 } 158 159 #define hpet_print_config() \ 160 do { \ 161 if (hpet_verbose) \ 162 _hpet_print_config(__FUNCTION__, __LINE__); \ 163 } while (0) 164 165 /* 166 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 167 * timer 0 and timer 1 in case of RTC emulation. 168 */ 169 #ifdef CONFIG_HPET 170 171 static void hpet_reserve_msi_timers(struct hpet_data *hd); 172 173 static void hpet_reserve_platform_timers(unsigned int id) 174 { 175 struct hpet __iomem *hpet = hpet_virt_address; 176 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 177 unsigned int nrtimers, i; 178 struct hpet_data hd; 179 180 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 181 182 memset(&hd, 0, sizeof(hd)); 183 hd.hd_phys_address = hpet_address; 184 hd.hd_address = hpet; 185 hd.hd_nirqs = nrtimers; 186 hpet_reserve_timer(&hd, 0); 187 188 #ifdef CONFIG_HPET_EMULATE_RTC 189 hpet_reserve_timer(&hd, 1); 190 #endif 191 192 /* 193 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 194 * is wrong for i8259!) not the output IRQ. Many BIOS writers 195 * don't bother configuring *any* comparator interrupts. 196 */ 197 hd.hd_irq[0] = HPET_LEGACY_8254; 198 hd.hd_irq[1] = HPET_LEGACY_RTC; 199 200 for (i = 2; i < nrtimers; timer++, i++) { 201 hd.hd_irq[i] = (readl(&timer->hpet_config) & 202 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 203 } 204 205 hpet_reserve_msi_timers(&hd); 206 207 hpet_alloc(&hd); 208 209 } 210 #else 211 static void hpet_reserve_platform_timers(unsigned int id) { } 212 #endif 213 214 /* 215 * Common hpet info 216 */ 217 static unsigned long hpet_period; 218 219 static void hpet_legacy_set_mode(enum clock_event_mode mode, 220 struct clock_event_device *evt); 221 static int hpet_legacy_next_event(unsigned long delta, 222 struct clock_event_device *evt); 223 224 /* 225 * The hpet clock event device 226 */ 227 static struct clock_event_device hpet_clockevent = { 228 .name = "hpet", 229 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 230 .set_mode = hpet_legacy_set_mode, 231 .set_next_event = hpet_legacy_next_event, 232 .shift = 32, 233 .irq = 0, 234 .rating = 50, 235 }; 236 237 static void hpet_stop_counter(void) 238 { 239 unsigned long cfg = hpet_readl(HPET_CFG); 240 cfg &= ~HPET_CFG_ENABLE; 241 hpet_writel(cfg, HPET_CFG); 242 } 243 244 static void hpet_reset_counter(void) 245 { 246 hpet_writel(0, HPET_COUNTER); 247 hpet_writel(0, HPET_COUNTER + 4); 248 } 249 250 static void hpet_start_counter(void) 251 { 252 unsigned int cfg = hpet_readl(HPET_CFG); 253 cfg |= HPET_CFG_ENABLE; 254 hpet_writel(cfg, HPET_CFG); 255 } 256 257 static void hpet_restart_counter(void) 258 { 259 hpet_stop_counter(); 260 hpet_reset_counter(); 261 hpet_start_counter(); 262 } 263 264 static void hpet_resume_device(void) 265 { 266 force_hpet_resume(); 267 } 268 269 static void hpet_resume_counter(struct clocksource *cs) 270 { 271 hpet_resume_device(); 272 hpet_restart_counter(); 273 } 274 275 static void hpet_enable_legacy_int(void) 276 { 277 unsigned int cfg = hpet_readl(HPET_CFG); 278 279 cfg |= HPET_CFG_LEGACY; 280 hpet_writel(cfg, HPET_CFG); 281 hpet_legacy_int_enabled = 1; 282 } 283 284 static void hpet_legacy_clockevent_register(void) 285 { 286 /* Start HPET legacy interrupts */ 287 hpet_enable_legacy_int(); 288 289 /* 290 * The mult factor is defined as (include/linux/clockchips.h) 291 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) 292 * hpet_period is in units of femtoseconds (per cycle), so 293 * mult/2^shift = cyc/ns = 10^6/hpet_period 294 * mult = (10^6 * 2^shift)/hpet_period 295 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period 296 */ 297 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, 298 hpet_period, hpet_clockevent.shift); 299 /* Calculate the min / max delta */ 300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 301 &hpet_clockevent); 302 /* 5 usec minimum reprogramming delta. */ 303 hpet_clockevent.min_delta_ns = 5000; 304 305 /* 306 * Start hpet with the boot cpu mask and make it 307 * global after the IO_APIC has been initialized. 308 */ 309 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 310 clockevents_register_device(&hpet_clockevent); 311 global_clock_event = &hpet_clockevent; 312 printk(KERN_DEBUG "hpet clockevent registered\n"); 313 } 314 315 static int hpet_setup_msi_irq(unsigned int irq); 316 317 static void hpet_set_mode(enum clock_event_mode mode, 318 struct clock_event_device *evt, int timer) 319 { 320 unsigned int cfg, cmp, now; 321 uint64_t delta; 322 323 switch (mode) { 324 case CLOCK_EVT_MODE_PERIODIC: 325 hpet_stop_counter(); 326 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; 327 delta >>= evt->shift; 328 now = hpet_readl(HPET_COUNTER); 329 cmp = now + (unsigned int) delta; 330 cfg = hpet_readl(HPET_Tn_CFG(timer)); 331 /* Make sure we use edge triggered interrupts */ 332 cfg &= ~HPET_TN_LEVEL; 333 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 334 HPET_TN_SETVAL | HPET_TN_32BIT; 335 hpet_writel(cfg, HPET_Tn_CFG(timer)); 336 hpet_writel(cmp, HPET_Tn_CMP(timer)); 337 udelay(1); 338 /* 339 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 340 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 341 * bit is automatically cleared after the first write. 342 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 343 * Publication # 24674) 344 */ 345 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); 346 hpet_start_counter(); 347 hpet_print_config(); 348 break; 349 350 case CLOCK_EVT_MODE_ONESHOT: 351 cfg = hpet_readl(HPET_Tn_CFG(timer)); 352 cfg &= ~HPET_TN_PERIODIC; 353 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 354 hpet_writel(cfg, HPET_Tn_CFG(timer)); 355 break; 356 357 case CLOCK_EVT_MODE_UNUSED: 358 case CLOCK_EVT_MODE_SHUTDOWN: 359 cfg = hpet_readl(HPET_Tn_CFG(timer)); 360 cfg &= ~HPET_TN_ENABLE; 361 hpet_writel(cfg, HPET_Tn_CFG(timer)); 362 break; 363 364 case CLOCK_EVT_MODE_RESUME: 365 if (timer == 0) { 366 hpet_enable_legacy_int(); 367 } else { 368 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 369 hpet_setup_msi_irq(hdev->irq); 370 disable_irq(hdev->irq); 371 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 372 enable_irq(hdev->irq); 373 } 374 hpet_print_config(); 375 break; 376 } 377 } 378 379 static int hpet_next_event(unsigned long delta, 380 struct clock_event_device *evt, int timer) 381 { 382 u32 cnt; 383 s32 res; 384 385 cnt = hpet_readl(HPET_COUNTER); 386 cnt += (u32) delta; 387 hpet_writel(cnt, HPET_Tn_CMP(timer)); 388 389 /* 390 * HPETs are a complete disaster. The compare register is 391 * based on a equal comparison and neither provides a less 392 * than or equal functionality (which would require to take 393 * the wraparound into account) nor a simple count down event 394 * mode. Further the write to the comparator register is 395 * delayed internally up to two HPET clock cycles in certain 396 * chipsets (ATI, ICH9,10). We worked around that by reading 397 * back the compare register, but that required another 398 * workaround for ICH9,10 chips where the first readout after 399 * write can return the old stale value. We already have a 400 * minimum delta of 5us enforced, but a NMI or SMI hitting 401 * between the counter readout and the comparator write can 402 * move us behind that point easily. Now instead of reading 403 * the compare register back several times, we make the ETIME 404 * decision based on the following: Return ETIME if the 405 * counter value after the write is less than 8 HPET cycles 406 * away from the event or if the counter is already ahead of 407 * the event. 408 */ 409 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 410 411 return res < 8 ? -ETIME : 0; 412 } 413 414 static void hpet_legacy_set_mode(enum clock_event_mode mode, 415 struct clock_event_device *evt) 416 { 417 hpet_set_mode(mode, evt, 0); 418 } 419 420 static int hpet_legacy_next_event(unsigned long delta, 421 struct clock_event_device *evt) 422 { 423 return hpet_next_event(delta, evt, 0); 424 } 425 426 /* 427 * HPET MSI Support 428 */ 429 #ifdef CONFIG_PCI_MSI 430 431 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 432 static struct hpet_dev *hpet_devs; 433 434 void hpet_msi_unmask(struct irq_data *data) 435 { 436 struct hpet_dev *hdev = data->handler_data; 437 unsigned int cfg; 438 439 /* unmask it */ 440 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 441 cfg |= HPET_TN_FSB; 442 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 443 } 444 445 void hpet_msi_mask(struct irq_data *data) 446 { 447 struct hpet_dev *hdev = data->handler_data; 448 unsigned int cfg; 449 450 /* mask it */ 451 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 452 cfg &= ~HPET_TN_FSB; 453 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 454 } 455 456 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) 457 { 458 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 459 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 460 } 461 462 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) 463 { 464 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 465 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 466 msg->address_hi = 0; 467 } 468 469 static void hpet_msi_set_mode(enum clock_event_mode mode, 470 struct clock_event_device *evt) 471 { 472 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 473 hpet_set_mode(mode, evt, hdev->num); 474 } 475 476 static int hpet_msi_next_event(unsigned long delta, 477 struct clock_event_device *evt) 478 { 479 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 480 return hpet_next_event(delta, evt, hdev->num); 481 } 482 483 static int hpet_setup_msi_irq(unsigned int irq) 484 { 485 if (arch_setup_hpet_msi(irq, hpet_blockid)) { 486 destroy_irq(irq); 487 return -EINVAL; 488 } 489 return 0; 490 } 491 492 static int hpet_assign_irq(struct hpet_dev *dev) 493 { 494 unsigned int irq; 495 496 irq = create_irq_nr(0, -1); 497 if (!irq) 498 return -EINVAL; 499 500 set_irq_data(irq, dev); 501 502 if (hpet_setup_msi_irq(irq)) 503 return -EINVAL; 504 505 dev->irq = irq; 506 return 0; 507 } 508 509 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 510 { 511 struct hpet_dev *dev = (struct hpet_dev *)data; 512 struct clock_event_device *hevt = &dev->evt; 513 514 if (!hevt->event_handler) { 515 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 516 dev->num); 517 return IRQ_HANDLED; 518 } 519 520 hevt->event_handler(hevt); 521 return IRQ_HANDLED; 522 } 523 524 static int hpet_setup_irq(struct hpet_dev *dev) 525 { 526 527 if (request_irq(dev->irq, hpet_interrupt_handler, 528 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, 529 dev->name, dev)) 530 return -1; 531 532 disable_irq(dev->irq); 533 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 534 enable_irq(dev->irq); 535 536 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 537 dev->name, dev->irq); 538 539 return 0; 540 } 541 542 /* This should be called in specific @cpu */ 543 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 544 { 545 struct clock_event_device *evt = &hdev->evt; 546 uint64_t hpet_freq; 547 548 WARN_ON(cpu != smp_processor_id()); 549 if (!(hdev->flags & HPET_DEV_VALID)) 550 return; 551 552 if (hpet_setup_msi_irq(hdev->irq)) 553 return; 554 555 hdev->cpu = cpu; 556 per_cpu(cpu_hpet_dev, cpu) = hdev; 557 evt->name = hdev->name; 558 hpet_setup_irq(hdev); 559 evt->irq = hdev->irq; 560 561 evt->rating = 110; 562 evt->features = CLOCK_EVT_FEAT_ONESHOT; 563 if (hdev->flags & HPET_DEV_PERI_CAP) 564 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 565 566 evt->set_mode = hpet_msi_set_mode; 567 evt->set_next_event = hpet_msi_next_event; 568 evt->shift = 32; 569 570 /* 571 * The period is a femto seconds value. We need to calculate the 572 * scaled math multiplication factor for nanosecond to hpet tick 573 * conversion. 574 */ 575 hpet_freq = FSEC_PER_SEC; 576 do_div(hpet_freq, hpet_period); 577 evt->mult = div_sc((unsigned long) hpet_freq, 578 NSEC_PER_SEC, evt->shift); 579 /* Calculate the max delta */ 580 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); 581 /* 5 usec minimum reprogramming delta. */ 582 evt->min_delta_ns = 5000; 583 584 evt->cpumask = cpumask_of(hdev->cpu); 585 clockevents_register_device(evt); 586 } 587 588 #ifdef CONFIG_HPET 589 /* Reserve at least one timer for userspace (/dev/hpet) */ 590 #define RESERVE_TIMERS 1 591 #else 592 #define RESERVE_TIMERS 0 593 #endif 594 595 static void hpet_msi_capability_lookup(unsigned int start_timer) 596 { 597 unsigned int id; 598 unsigned int num_timers; 599 unsigned int num_timers_used = 0; 600 int i; 601 602 if (hpet_msi_disable) 603 return; 604 605 if (boot_cpu_has(X86_FEATURE_ARAT)) 606 return; 607 id = hpet_readl(HPET_ID); 608 609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 610 num_timers++; /* Value read out starts from 0 */ 611 hpet_print_config(); 612 613 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 614 if (!hpet_devs) 615 return; 616 617 hpet_num_timers = num_timers; 618 619 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 620 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 621 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 622 623 /* Only consider HPET timer with MSI support */ 624 if (!(cfg & HPET_TN_FSB_CAP)) 625 continue; 626 627 hdev->flags = 0; 628 if (cfg & HPET_TN_PERIODIC_CAP) 629 hdev->flags |= HPET_DEV_PERI_CAP; 630 hdev->num = i; 631 632 sprintf(hdev->name, "hpet%d", i); 633 if (hpet_assign_irq(hdev)) 634 continue; 635 636 hdev->flags |= HPET_DEV_FSB_CAP; 637 hdev->flags |= HPET_DEV_VALID; 638 num_timers_used++; 639 if (num_timers_used == num_possible_cpus()) 640 break; 641 } 642 643 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 644 num_timers, num_timers_used); 645 } 646 647 #ifdef CONFIG_HPET 648 static void hpet_reserve_msi_timers(struct hpet_data *hd) 649 { 650 int i; 651 652 if (!hpet_devs) 653 return; 654 655 for (i = 0; i < hpet_num_timers; i++) { 656 struct hpet_dev *hdev = &hpet_devs[i]; 657 658 if (!(hdev->flags & HPET_DEV_VALID)) 659 continue; 660 661 hd->hd_irq[hdev->num] = hdev->irq; 662 hpet_reserve_timer(hd, hdev->num); 663 } 664 } 665 #endif 666 667 static struct hpet_dev *hpet_get_unused_timer(void) 668 { 669 int i; 670 671 if (!hpet_devs) 672 return NULL; 673 674 for (i = 0; i < hpet_num_timers; i++) { 675 struct hpet_dev *hdev = &hpet_devs[i]; 676 677 if (!(hdev->flags & HPET_DEV_VALID)) 678 continue; 679 if (test_and_set_bit(HPET_DEV_USED_BIT, 680 (unsigned long *)&hdev->flags)) 681 continue; 682 return hdev; 683 } 684 return NULL; 685 } 686 687 struct hpet_work_struct { 688 struct delayed_work work; 689 struct completion complete; 690 }; 691 692 static void hpet_work(struct work_struct *w) 693 { 694 struct hpet_dev *hdev; 695 int cpu = smp_processor_id(); 696 struct hpet_work_struct *hpet_work; 697 698 hpet_work = container_of(w, struct hpet_work_struct, work.work); 699 700 hdev = hpet_get_unused_timer(); 701 if (hdev) 702 init_one_hpet_msi_clockevent(hdev, cpu); 703 704 complete(&hpet_work->complete); 705 } 706 707 static int hpet_cpuhp_notify(struct notifier_block *n, 708 unsigned long action, void *hcpu) 709 { 710 unsigned long cpu = (unsigned long)hcpu; 711 struct hpet_work_struct work; 712 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 713 714 switch (action & 0xf) { 715 case CPU_ONLINE: 716 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); 717 init_completion(&work.complete); 718 /* FIXME: add schedule_work_on() */ 719 schedule_delayed_work_on(cpu, &work.work, 0); 720 wait_for_completion(&work.complete); 721 destroy_timer_on_stack(&work.work.timer); 722 break; 723 case CPU_DEAD: 724 if (hdev) { 725 free_irq(hdev->irq, hdev); 726 hdev->flags &= ~HPET_DEV_USED; 727 per_cpu(cpu_hpet_dev, cpu) = NULL; 728 } 729 break; 730 } 731 return NOTIFY_OK; 732 } 733 #else 734 735 static int hpet_setup_msi_irq(unsigned int irq) 736 { 737 return 0; 738 } 739 static void hpet_msi_capability_lookup(unsigned int start_timer) 740 { 741 return; 742 } 743 744 #ifdef CONFIG_HPET 745 static void hpet_reserve_msi_timers(struct hpet_data *hd) 746 { 747 return; 748 } 749 #endif 750 751 static int hpet_cpuhp_notify(struct notifier_block *n, 752 unsigned long action, void *hcpu) 753 { 754 return NOTIFY_OK; 755 } 756 757 #endif 758 759 /* 760 * Clock source related code 761 */ 762 static cycle_t read_hpet(struct clocksource *cs) 763 { 764 return (cycle_t)hpet_readl(HPET_COUNTER); 765 } 766 767 #ifdef CONFIG_X86_64 768 static cycle_t __vsyscall_fn vread_hpet(void) 769 { 770 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); 771 } 772 #endif 773 774 static struct clocksource clocksource_hpet = { 775 .name = "hpet", 776 .rating = 250, 777 .read = read_hpet, 778 .mask = HPET_MASK, 779 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 780 .resume = hpet_resume_counter, 781 #ifdef CONFIG_X86_64 782 .vread = vread_hpet, 783 #endif 784 }; 785 786 static int hpet_clocksource_register(void) 787 { 788 u64 start, now; 789 u64 hpet_freq; 790 cycle_t t1; 791 792 /* Start the counter */ 793 hpet_restart_counter(); 794 795 /* Verify whether hpet counter works */ 796 t1 = hpet_readl(HPET_COUNTER); 797 rdtscll(start); 798 799 /* 800 * We don't know the TSC frequency yet, but waiting for 801 * 200000 TSC cycles is safe: 802 * 4 GHz == 50us 803 * 1 GHz == 200us 804 */ 805 do { 806 rep_nop(); 807 rdtscll(now); 808 } while ((now - start) < 200000UL); 809 810 if (t1 == hpet_readl(HPET_COUNTER)) { 811 printk(KERN_WARNING 812 "HPET counter not counting. HPET disabled\n"); 813 return -ENODEV; 814 } 815 816 /* 817 * The definition of mult is (include/linux/clocksource.h) 818 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc 819 * so we first need to convert hpet_period to ns/cyc units: 820 * mult/2^shift = ns/cyc = hpet_period/10^6 821 * mult = (hpet_period * 2^shift)/10^6 822 * mult = (hpet_period << shift)/FSEC_PER_NSEC 823 */ 824 825 /* Need to convert hpet_period (fsec/cyc) to cyc/sec: 826 * 827 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc) 828 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period 829 */ 830 hpet_freq = FSEC_PER_SEC; 831 do_div(hpet_freq, hpet_period); 832 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 833 834 return 0; 835 } 836 837 /** 838 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 839 */ 840 int __init hpet_enable(void) 841 { 842 unsigned int id; 843 int i; 844 845 if (!is_hpet_capable()) 846 return 0; 847 848 hpet_set_mapping(); 849 850 /* 851 * Read the period and check for a sane value: 852 */ 853 hpet_period = hpet_readl(HPET_PERIOD); 854 855 /* 856 * AMD SB700 based systems with spread spectrum enabled use a 857 * SMM based HPET emulation to provide proper frequency 858 * setting. The SMM code is initialized with the first HPET 859 * register access and takes some time to complete. During 860 * this time the config register reads 0xffffffff. We check 861 * for max. 1000 loops whether the config register reads a non 862 * 0xffffffff value to make sure that HPET is up and running 863 * before we go further. A counting loop is safe, as the HPET 864 * access takes thousands of CPU cycles. On non SB700 based 865 * machines this check is only done once and has no side 866 * effects. 867 */ 868 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 869 if (i == 1000) { 870 printk(KERN_WARNING 871 "HPET config register value = 0xFFFFFFFF. " 872 "Disabling HPET\n"); 873 goto out_nohpet; 874 } 875 } 876 877 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 878 goto out_nohpet; 879 880 /* 881 * Read the HPET ID register to retrieve the IRQ routing 882 * information and the number of channels 883 */ 884 id = hpet_readl(HPET_ID); 885 hpet_print_config(); 886 887 #ifdef CONFIG_HPET_EMULATE_RTC 888 /* 889 * The legacy routing mode needs at least two channels, tick timer 890 * and the rtc emulation channel. 891 */ 892 if (!(id & HPET_ID_NUMBER)) 893 goto out_nohpet; 894 #endif 895 896 if (hpet_clocksource_register()) 897 goto out_nohpet; 898 899 if (id & HPET_ID_LEGSUP) { 900 hpet_legacy_clockevent_register(); 901 return 1; 902 } 903 return 0; 904 905 out_nohpet: 906 hpet_clear_mapping(); 907 hpet_address = 0; 908 return 0; 909 } 910 911 /* 912 * Needs to be late, as the reserve_timer code calls kalloc ! 913 * 914 * Not a problem on i386 as hpet_enable is called from late_time_init, 915 * but on x86_64 it is necessary ! 916 */ 917 static __init int hpet_late_init(void) 918 { 919 int cpu; 920 921 if (boot_hpet_disable) 922 return -ENODEV; 923 924 if (!hpet_address) { 925 if (!force_hpet_address) 926 return -ENODEV; 927 928 hpet_address = force_hpet_address; 929 hpet_enable(); 930 } 931 932 if (!hpet_virt_address) 933 return -ENODEV; 934 935 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 936 hpet_msi_capability_lookup(2); 937 else 938 hpet_msi_capability_lookup(0); 939 940 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 941 hpet_print_config(); 942 943 if (hpet_msi_disable) 944 return 0; 945 946 if (boot_cpu_has(X86_FEATURE_ARAT)) 947 return 0; 948 949 for_each_online_cpu(cpu) { 950 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); 951 } 952 953 /* This notifier should be called after workqueue is ready */ 954 hotcpu_notifier(hpet_cpuhp_notify, -20); 955 956 return 0; 957 } 958 fs_initcall(hpet_late_init); 959 960 void hpet_disable(void) 961 { 962 if (is_hpet_capable() && hpet_virt_address) { 963 unsigned int cfg = hpet_readl(HPET_CFG); 964 965 if (hpet_legacy_int_enabled) { 966 cfg &= ~HPET_CFG_LEGACY; 967 hpet_legacy_int_enabled = 0; 968 } 969 cfg &= ~HPET_CFG_ENABLE; 970 hpet_writel(cfg, HPET_CFG); 971 } 972 } 973 974 #ifdef CONFIG_HPET_EMULATE_RTC 975 976 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 977 * is enabled, we support RTC interrupt functionality in software. 978 * RTC has 3 kinds of interrupts: 979 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 980 * is updated 981 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 982 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 983 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 984 * (1) and (2) above are implemented using polling at a frequency of 985 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 986 * overhead. (DEFAULT_RTC_INT_FREQ) 987 * For (3), we use interrupts at 64Hz or user specified periodic 988 * frequency, whichever is higher. 989 */ 990 #include <linux/mc146818rtc.h> 991 #include <linux/rtc.h> 992 #include <asm/rtc.h> 993 994 #define DEFAULT_RTC_INT_FREQ 64 995 #define DEFAULT_RTC_SHIFT 6 996 #define RTC_NUM_INTS 1 997 998 static unsigned long hpet_rtc_flags; 999 static int hpet_prev_update_sec; 1000 static struct rtc_time hpet_alarm_time; 1001 static unsigned long hpet_pie_count; 1002 static u32 hpet_t1_cmp; 1003 static u32 hpet_default_delta; 1004 static u32 hpet_pie_delta; 1005 static unsigned long hpet_pie_limit; 1006 1007 static rtc_irq_handler irq_handler; 1008 1009 /* 1010 * Check that the hpet counter c1 is ahead of the c2 1011 */ 1012 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1013 { 1014 return (s32)(c2 - c1) < 0; 1015 } 1016 1017 /* 1018 * Registers a IRQ handler. 1019 */ 1020 int hpet_register_irq_handler(rtc_irq_handler handler) 1021 { 1022 if (!is_hpet_enabled()) 1023 return -ENODEV; 1024 if (irq_handler) 1025 return -EBUSY; 1026 1027 irq_handler = handler; 1028 1029 return 0; 1030 } 1031 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1032 1033 /* 1034 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1035 * and does cleanup. 1036 */ 1037 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1038 { 1039 if (!is_hpet_enabled()) 1040 return; 1041 1042 irq_handler = NULL; 1043 hpet_rtc_flags = 0; 1044 } 1045 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1046 1047 /* 1048 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1049 * is not supported by all HPET implementations for timer 1. 1050 * 1051 * hpet_rtc_timer_init() is called when the rtc is initialized. 1052 */ 1053 int hpet_rtc_timer_init(void) 1054 { 1055 unsigned int cfg, cnt, delta; 1056 unsigned long flags; 1057 1058 if (!is_hpet_enabled()) 1059 return 0; 1060 1061 if (!hpet_default_delta) { 1062 uint64_t clc; 1063 1064 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1065 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1066 hpet_default_delta = clc; 1067 } 1068 1069 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1070 delta = hpet_default_delta; 1071 else 1072 delta = hpet_pie_delta; 1073 1074 local_irq_save(flags); 1075 1076 cnt = delta + hpet_readl(HPET_COUNTER); 1077 hpet_writel(cnt, HPET_T1_CMP); 1078 hpet_t1_cmp = cnt; 1079 1080 cfg = hpet_readl(HPET_T1_CFG); 1081 cfg &= ~HPET_TN_PERIODIC; 1082 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1083 hpet_writel(cfg, HPET_T1_CFG); 1084 1085 local_irq_restore(flags); 1086 1087 return 1; 1088 } 1089 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1090 1091 /* 1092 * The functions below are called from rtc driver. 1093 * Return 0 if HPET is not being used. 1094 * Otherwise do the necessary changes and return 1. 1095 */ 1096 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1097 { 1098 if (!is_hpet_enabled()) 1099 return 0; 1100 1101 hpet_rtc_flags &= ~bit_mask; 1102 return 1; 1103 } 1104 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1105 1106 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1107 { 1108 unsigned long oldbits = hpet_rtc_flags; 1109 1110 if (!is_hpet_enabled()) 1111 return 0; 1112 1113 hpet_rtc_flags |= bit_mask; 1114 1115 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1116 hpet_prev_update_sec = -1; 1117 1118 if (!oldbits) 1119 hpet_rtc_timer_init(); 1120 1121 return 1; 1122 } 1123 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1124 1125 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1126 unsigned char sec) 1127 { 1128 if (!is_hpet_enabled()) 1129 return 0; 1130 1131 hpet_alarm_time.tm_hour = hrs; 1132 hpet_alarm_time.tm_min = min; 1133 hpet_alarm_time.tm_sec = sec; 1134 1135 return 1; 1136 } 1137 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1138 1139 int hpet_set_periodic_freq(unsigned long freq) 1140 { 1141 uint64_t clc; 1142 1143 if (!is_hpet_enabled()) 1144 return 0; 1145 1146 if (freq <= DEFAULT_RTC_INT_FREQ) 1147 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1148 else { 1149 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1150 do_div(clc, freq); 1151 clc >>= hpet_clockevent.shift; 1152 hpet_pie_delta = clc; 1153 hpet_pie_limit = 0; 1154 } 1155 return 1; 1156 } 1157 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1158 1159 int hpet_rtc_dropped_irq(void) 1160 { 1161 return is_hpet_enabled(); 1162 } 1163 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1164 1165 static void hpet_rtc_timer_reinit(void) 1166 { 1167 unsigned int cfg, delta; 1168 int lost_ints = -1; 1169 1170 if (unlikely(!hpet_rtc_flags)) { 1171 cfg = hpet_readl(HPET_T1_CFG); 1172 cfg &= ~HPET_TN_ENABLE; 1173 hpet_writel(cfg, HPET_T1_CFG); 1174 return; 1175 } 1176 1177 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1178 delta = hpet_default_delta; 1179 else 1180 delta = hpet_pie_delta; 1181 1182 /* 1183 * Increment the comparator value until we are ahead of the 1184 * current count. 1185 */ 1186 do { 1187 hpet_t1_cmp += delta; 1188 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1189 lost_ints++; 1190 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1191 1192 if (lost_ints) { 1193 if (hpet_rtc_flags & RTC_PIE) 1194 hpet_pie_count += lost_ints; 1195 if (printk_ratelimit()) 1196 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1197 lost_ints); 1198 } 1199 } 1200 1201 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1202 { 1203 struct rtc_time curr_time; 1204 unsigned long rtc_int_flag = 0; 1205 1206 hpet_rtc_timer_reinit(); 1207 memset(&curr_time, 0, sizeof(struct rtc_time)); 1208 1209 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1210 get_rtc_time(&curr_time); 1211 1212 if (hpet_rtc_flags & RTC_UIE && 1213 curr_time.tm_sec != hpet_prev_update_sec) { 1214 if (hpet_prev_update_sec >= 0) 1215 rtc_int_flag = RTC_UF; 1216 hpet_prev_update_sec = curr_time.tm_sec; 1217 } 1218 1219 if (hpet_rtc_flags & RTC_PIE && 1220 ++hpet_pie_count >= hpet_pie_limit) { 1221 rtc_int_flag |= RTC_PF; 1222 hpet_pie_count = 0; 1223 } 1224 1225 if (hpet_rtc_flags & RTC_AIE && 1226 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1227 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1228 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1229 rtc_int_flag |= RTC_AF; 1230 1231 if (rtc_int_flag) { 1232 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1233 if (irq_handler) 1234 irq_handler(rtc_int_flag, dev_id); 1235 } 1236 return IRQ_HANDLED; 1237 } 1238 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1239 #endif 1240