1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/export.h> 5 #include <linux/delay.h> 6 #include <linux/errno.h> 7 #include <linux/i8253.h> 8 #include <linux/slab.h> 9 #include <linux/hpet.h> 10 #include <linux/init.h> 11 #include <linux/cpu.h> 12 #include <linux/pm.h> 13 #include <linux/io.h> 14 15 #include <asm/cpufeature.h> 16 #include <asm/irqdomain.h> 17 #include <asm/fixmap.h> 18 #include <asm/hpet.h> 19 #include <asm/time.h> 20 21 #define HPET_MASK CLOCKSOURCE_MASK(32) 22 23 /* FSEC = 10^-15 24 NSEC = 10^-9 */ 25 #define FSEC_PER_NSEC 1000000L 26 27 #define HPET_DEV_USED_BIT 2 28 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 29 #define HPET_DEV_VALID 0x8 30 #define HPET_DEV_FSB_CAP 0x1000 31 #define HPET_DEV_PERI_CAP 0x2000 32 33 #define HPET_MIN_CYCLES 128 34 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) 35 36 /* 37 * HPET address is set in acpi/boot.c, when an ACPI entry exists 38 */ 39 unsigned long hpet_address; 40 u8 hpet_blockid; /* OS timer block num */ 41 bool hpet_msi_disable; 42 43 #ifdef CONFIG_PCI_MSI 44 static unsigned int hpet_num_timers; 45 #endif 46 static void __iomem *hpet_virt_address; 47 48 struct hpet_dev { 49 struct clock_event_device evt; 50 unsigned int num; 51 int cpu; 52 unsigned int irq; 53 unsigned int flags; 54 char name[10]; 55 }; 56 57 static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) 58 { 59 return container_of(evtdev, struct hpet_dev, evt); 60 } 61 62 inline unsigned int hpet_readl(unsigned int a) 63 { 64 return readl(hpet_virt_address + a); 65 } 66 67 static inline void hpet_writel(unsigned int d, unsigned int a) 68 { 69 writel(d, hpet_virt_address + a); 70 } 71 72 #ifdef CONFIG_X86_64 73 #include <asm/pgtable.h> 74 #endif 75 76 static inline void hpet_set_mapping(void) 77 { 78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 79 } 80 81 static inline void hpet_clear_mapping(void) 82 { 83 iounmap(hpet_virt_address); 84 hpet_virt_address = NULL; 85 } 86 87 /* 88 * HPET command line enable / disable 89 */ 90 bool boot_hpet_disable; 91 bool hpet_force_user; 92 static bool hpet_verbose; 93 94 static int __init hpet_setup(char *str) 95 { 96 while (str) { 97 char *next = strchr(str, ','); 98 99 if (next) 100 *next++ = 0; 101 if (!strncmp("disable", str, 7)) 102 boot_hpet_disable = true; 103 if (!strncmp("force", str, 5)) 104 hpet_force_user = true; 105 if (!strncmp("verbose", str, 7)) 106 hpet_verbose = true; 107 str = next; 108 } 109 return 1; 110 } 111 __setup("hpet=", hpet_setup); 112 113 static int __init disable_hpet(char *str) 114 { 115 boot_hpet_disable = true; 116 return 1; 117 } 118 __setup("nohpet", disable_hpet); 119 120 static inline int is_hpet_capable(void) 121 { 122 return !boot_hpet_disable && hpet_address; 123 } 124 125 /* 126 * HPET timer interrupt enable / disable 127 */ 128 static bool hpet_legacy_int_enabled; 129 130 /** 131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 132 */ 133 int is_hpet_enabled(void) 134 { 135 return is_hpet_capable() && hpet_legacy_int_enabled; 136 } 137 EXPORT_SYMBOL_GPL(is_hpet_enabled); 138 139 static void _hpet_print_config(const char *function, int line) 140 { 141 u32 i, timers, l, h; 142 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 143 l = hpet_readl(HPET_ID); 144 h = hpet_readl(HPET_PERIOD); 145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 147 l = hpet_readl(HPET_CFG); 148 h = hpet_readl(HPET_STATUS); 149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 150 l = hpet_readl(HPET_COUNTER); 151 h = hpet_readl(HPET_COUNTER+4); 152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 153 154 for (i = 0; i < timers; i++) { 155 l = hpet_readl(HPET_Tn_CFG(i)); 156 h = hpet_readl(HPET_Tn_CFG(i)+4); 157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 158 i, l, h); 159 l = hpet_readl(HPET_Tn_CMP(i)); 160 h = hpet_readl(HPET_Tn_CMP(i)+4); 161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 162 i, l, h); 163 l = hpet_readl(HPET_Tn_ROUTE(i)); 164 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 166 i, l, h); 167 } 168 } 169 170 #define hpet_print_config() \ 171 do { \ 172 if (hpet_verbose) \ 173 _hpet_print_config(__func__, __LINE__); \ 174 } while (0) 175 176 /* 177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 178 * timer 0 and timer 1 in case of RTC emulation. 179 */ 180 #ifdef CONFIG_HPET 181 182 static void hpet_reserve_msi_timers(struct hpet_data *hd); 183 184 static void hpet_reserve_platform_timers(unsigned int id) 185 { 186 struct hpet __iomem *hpet = hpet_virt_address; 187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 188 unsigned int nrtimers, i; 189 struct hpet_data hd; 190 191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 192 193 memset(&hd, 0, sizeof(hd)); 194 hd.hd_phys_address = hpet_address; 195 hd.hd_address = hpet; 196 hd.hd_nirqs = nrtimers; 197 hpet_reserve_timer(&hd, 0); 198 199 #ifdef CONFIG_HPET_EMULATE_RTC 200 hpet_reserve_timer(&hd, 1); 201 #endif 202 203 /* 204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 205 * is wrong for i8259!) not the output IRQ. Many BIOS writers 206 * don't bother configuring *any* comparator interrupts. 207 */ 208 hd.hd_irq[0] = HPET_LEGACY_8254; 209 hd.hd_irq[1] = HPET_LEGACY_RTC; 210 211 for (i = 2; i < nrtimers; timer++, i++) { 212 hd.hd_irq[i] = (readl(&timer->hpet_config) & 213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 214 } 215 216 hpet_reserve_msi_timers(&hd); 217 218 hpet_alloc(&hd); 219 220 } 221 #else 222 static void hpet_reserve_platform_timers(unsigned int id) { } 223 #endif 224 225 /* 226 * Common hpet info 227 */ 228 static unsigned long hpet_freq; 229 230 static struct clock_event_device hpet_clockevent; 231 232 static void hpet_stop_counter(void) 233 { 234 u32 cfg = hpet_readl(HPET_CFG); 235 cfg &= ~HPET_CFG_ENABLE; 236 hpet_writel(cfg, HPET_CFG); 237 } 238 239 static void hpet_reset_counter(void) 240 { 241 hpet_writel(0, HPET_COUNTER); 242 hpet_writel(0, HPET_COUNTER + 4); 243 } 244 245 static void hpet_start_counter(void) 246 { 247 unsigned int cfg = hpet_readl(HPET_CFG); 248 cfg |= HPET_CFG_ENABLE; 249 hpet_writel(cfg, HPET_CFG); 250 } 251 252 static void hpet_restart_counter(void) 253 { 254 hpet_stop_counter(); 255 hpet_reset_counter(); 256 hpet_start_counter(); 257 } 258 259 static void hpet_resume_device(void) 260 { 261 force_hpet_resume(); 262 } 263 264 static void hpet_resume_counter(struct clocksource *cs) 265 { 266 hpet_resume_device(); 267 hpet_restart_counter(); 268 } 269 270 static void hpet_enable_legacy_int(void) 271 { 272 unsigned int cfg = hpet_readl(HPET_CFG); 273 274 cfg |= HPET_CFG_LEGACY; 275 hpet_writel(cfg, HPET_CFG); 276 hpet_legacy_int_enabled = true; 277 } 278 279 static void hpet_legacy_clockevent_register(void) 280 { 281 /* Start HPET legacy interrupts */ 282 hpet_enable_legacy_int(); 283 284 /* 285 * Start hpet with the boot cpu mask and make it 286 * global after the IO_APIC has been initialized. 287 */ 288 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 289 clockevents_config_and_register(&hpet_clockevent, hpet_freq, 290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF); 291 global_clock_event = &hpet_clockevent; 292 printk(KERN_DEBUG "hpet clockevent registered\n"); 293 } 294 295 static int hpet_set_periodic(struct clock_event_device *evt, int timer) 296 { 297 unsigned int cfg, cmp, now; 298 uint64_t delta; 299 300 hpet_stop_counter(); 301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; 302 delta >>= evt->shift; 303 now = hpet_readl(HPET_COUNTER); 304 cmp = now + (unsigned int)delta; 305 cfg = hpet_readl(HPET_Tn_CFG(timer)); 306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | 307 HPET_TN_32BIT; 308 hpet_writel(cfg, HPET_Tn_CFG(timer)); 309 hpet_writel(cmp, HPET_Tn_CMP(timer)); 310 udelay(1); 311 /* 312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 314 * bit is automatically cleared after the first write. 315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 316 * Publication # 24674) 317 */ 318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer)); 319 hpet_start_counter(); 320 hpet_print_config(); 321 322 return 0; 323 } 324 325 static int hpet_set_oneshot(struct clock_event_device *evt, int timer) 326 { 327 unsigned int cfg; 328 329 cfg = hpet_readl(HPET_Tn_CFG(timer)); 330 cfg &= ~HPET_TN_PERIODIC; 331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 332 hpet_writel(cfg, HPET_Tn_CFG(timer)); 333 334 return 0; 335 } 336 337 static int hpet_shutdown(struct clock_event_device *evt, int timer) 338 { 339 unsigned int cfg; 340 341 cfg = hpet_readl(HPET_Tn_CFG(timer)); 342 cfg &= ~HPET_TN_ENABLE; 343 hpet_writel(cfg, HPET_Tn_CFG(timer)); 344 345 return 0; 346 } 347 348 static int hpet_resume(struct clock_event_device *evt, int timer) 349 { 350 if (!timer) { 351 hpet_enable_legacy_int(); 352 } else { 353 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 354 355 irq_domain_activate_irq(irq_get_irq_data(hdev->irq)); 356 disable_irq(hdev->irq); 357 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 358 enable_irq(hdev->irq); 359 } 360 hpet_print_config(); 361 362 return 0; 363 } 364 365 static int hpet_next_event(unsigned long delta, 366 struct clock_event_device *evt, int timer) 367 { 368 u32 cnt; 369 s32 res; 370 371 cnt = hpet_readl(HPET_COUNTER); 372 cnt += (u32) delta; 373 hpet_writel(cnt, HPET_Tn_CMP(timer)); 374 375 /* 376 * HPETs are a complete disaster. The compare register is 377 * based on a equal comparison and neither provides a less 378 * than or equal functionality (which would require to take 379 * the wraparound into account) nor a simple count down event 380 * mode. Further the write to the comparator register is 381 * delayed internally up to two HPET clock cycles in certain 382 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even 383 * longer delays. We worked around that by reading back the 384 * compare register, but that required another workaround for 385 * ICH9,10 chips where the first readout after write can 386 * return the old stale value. We already had a minimum 387 * programming delta of 5us enforced, but a NMI or SMI hitting 388 * between the counter readout and the comparator write can 389 * move us behind that point easily. Now instead of reading 390 * the compare register back several times, we make the ETIME 391 * decision based on the following: Return ETIME if the 392 * counter value after the write is less than HPET_MIN_CYCLES 393 * away from the event or if the counter is already ahead of 394 * the event. The minimum programming delta for the generic 395 * clockevents code is set to 1.5 * HPET_MIN_CYCLES. 396 */ 397 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 398 399 return res < HPET_MIN_CYCLES ? -ETIME : 0; 400 } 401 402 static int hpet_legacy_shutdown(struct clock_event_device *evt) 403 { 404 return hpet_shutdown(evt, 0); 405 } 406 407 static int hpet_legacy_set_oneshot(struct clock_event_device *evt) 408 { 409 return hpet_set_oneshot(evt, 0); 410 } 411 412 static int hpet_legacy_set_periodic(struct clock_event_device *evt) 413 { 414 return hpet_set_periodic(evt, 0); 415 } 416 417 static int hpet_legacy_resume(struct clock_event_device *evt) 418 { 419 return hpet_resume(evt, 0); 420 } 421 422 static int hpet_legacy_next_event(unsigned long delta, 423 struct clock_event_device *evt) 424 { 425 return hpet_next_event(delta, evt, 0); 426 } 427 428 /* 429 * The hpet clock event device 430 */ 431 static struct clock_event_device hpet_clockevent = { 432 .name = "hpet", 433 .features = CLOCK_EVT_FEAT_PERIODIC | 434 CLOCK_EVT_FEAT_ONESHOT, 435 .set_state_periodic = hpet_legacy_set_periodic, 436 .set_state_oneshot = hpet_legacy_set_oneshot, 437 .set_state_shutdown = hpet_legacy_shutdown, 438 .tick_resume = hpet_legacy_resume, 439 .set_next_event = hpet_legacy_next_event, 440 .irq = 0, 441 .rating = 50, 442 }; 443 444 /* 445 * HPET MSI Support 446 */ 447 #ifdef CONFIG_PCI_MSI 448 449 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 450 static struct hpet_dev *hpet_devs; 451 static struct irq_domain *hpet_domain; 452 453 void hpet_msi_unmask(struct irq_data *data) 454 { 455 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); 456 unsigned int cfg; 457 458 /* unmask it */ 459 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 460 cfg |= HPET_TN_ENABLE | HPET_TN_FSB; 461 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 462 } 463 464 void hpet_msi_mask(struct irq_data *data) 465 { 466 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); 467 unsigned int cfg; 468 469 /* mask it */ 470 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 471 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); 472 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 473 } 474 475 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) 476 { 477 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 478 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 479 } 480 481 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) 482 { 483 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 484 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 485 msg->address_hi = 0; 486 } 487 488 static int hpet_msi_shutdown(struct clock_event_device *evt) 489 { 490 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 491 492 return hpet_shutdown(evt, hdev->num); 493 } 494 495 static int hpet_msi_set_oneshot(struct clock_event_device *evt) 496 { 497 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 498 499 return hpet_set_oneshot(evt, hdev->num); 500 } 501 502 static int hpet_msi_set_periodic(struct clock_event_device *evt) 503 { 504 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 505 506 return hpet_set_periodic(evt, hdev->num); 507 } 508 509 static int hpet_msi_resume(struct clock_event_device *evt) 510 { 511 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 512 513 return hpet_resume(evt, hdev->num); 514 } 515 516 static int hpet_msi_next_event(unsigned long delta, 517 struct clock_event_device *evt) 518 { 519 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 520 return hpet_next_event(delta, evt, hdev->num); 521 } 522 523 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 524 { 525 struct hpet_dev *dev = (struct hpet_dev *)data; 526 struct clock_event_device *hevt = &dev->evt; 527 528 if (!hevt->event_handler) { 529 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 530 dev->num); 531 return IRQ_HANDLED; 532 } 533 534 hevt->event_handler(hevt); 535 return IRQ_HANDLED; 536 } 537 538 static int hpet_setup_irq(struct hpet_dev *dev) 539 { 540 541 if (request_irq(dev->irq, hpet_interrupt_handler, 542 IRQF_TIMER | IRQF_NOBALANCING, 543 dev->name, dev)) 544 return -1; 545 546 disable_irq(dev->irq); 547 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 548 enable_irq(dev->irq); 549 550 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 551 dev->name, dev->irq); 552 553 return 0; 554 } 555 556 /* This should be called in specific @cpu */ 557 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 558 { 559 struct clock_event_device *evt = &hdev->evt; 560 561 WARN_ON(cpu != smp_processor_id()); 562 if (!(hdev->flags & HPET_DEV_VALID)) 563 return; 564 565 hdev->cpu = cpu; 566 per_cpu(cpu_hpet_dev, cpu) = hdev; 567 evt->name = hdev->name; 568 hpet_setup_irq(hdev); 569 evt->irq = hdev->irq; 570 571 evt->rating = 110; 572 evt->features = CLOCK_EVT_FEAT_ONESHOT; 573 if (hdev->flags & HPET_DEV_PERI_CAP) { 574 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 575 evt->set_state_periodic = hpet_msi_set_periodic; 576 } 577 578 evt->set_state_shutdown = hpet_msi_shutdown; 579 evt->set_state_oneshot = hpet_msi_set_oneshot; 580 evt->tick_resume = hpet_msi_resume; 581 evt->set_next_event = hpet_msi_next_event; 582 evt->cpumask = cpumask_of(hdev->cpu); 583 584 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, 585 0x7FFFFFFF); 586 } 587 588 #ifdef CONFIG_HPET 589 /* Reserve at least one timer for userspace (/dev/hpet) */ 590 #define RESERVE_TIMERS 1 591 #else 592 #define RESERVE_TIMERS 0 593 #endif 594 595 static void hpet_msi_capability_lookup(unsigned int start_timer) 596 { 597 unsigned int id; 598 unsigned int num_timers; 599 unsigned int num_timers_used = 0; 600 int i, irq; 601 602 if (hpet_msi_disable) 603 return; 604 605 if (boot_cpu_has(X86_FEATURE_ARAT)) 606 return; 607 id = hpet_readl(HPET_ID); 608 609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 610 num_timers++; /* Value read out starts from 0 */ 611 hpet_print_config(); 612 613 hpet_domain = hpet_create_irq_domain(hpet_blockid); 614 if (!hpet_domain) 615 return; 616 617 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 618 if (!hpet_devs) 619 return; 620 621 hpet_num_timers = num_timers; 622 623 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 624 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 625 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 626 627 /* Only consider HPET timer with MSI support */ 628 if (!(cfg & HPET_TN_FSB_CAP)) 629 continue; 630 631 hdev->flags = 0; 632 if (cfg & HPET_TN_PERIODIC_CAP) 633 hdev->flags |= HPET_DEV_PERI_CAP; 634 sprintf(hdev->name, "hpet%d", i); 635 hdev->num = i; 636 637 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num); 638 if (irq <= 0) 639 continue; 640 641 hdev->irq = irq; 642 hdev->flags |= HPET_DEV_FSB_CAP; 643 hdev->flags |= HPET_DEV_VALID; 644 num_timers_used++; 645 if (num_timers_used == num_possible_cpus()) 646 break; 647 } 648 649 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 650 num_timers, num_timers_used); 651 } 652 653 #ifdef CONFIG_HPET 654 static void hpet_reserve_msi_timers(struct hpet_data *hd) 655 { 656 int i; 657 658 if (!hpet_devs) 659 return; 660 661 for (i = 0; i < hpet_num_timers; i++) { 662 struct hpet_dev *hdev = &hpet_devs[i]; 663 664 if (!(hdev->flags & HPET_DEV_VALID)) 665 continue; 666 667 hd->hd_irq[hdev->num] = hdev->irq; 668 hpet_reserve_timer(hd, hdev->num); 669 } 670 } 671 #endif 672 673 static struct hpet_dev *hpet_get_unused_timer(void) 674 { 675 int i; 676 677 if (!hpet_devs) 678 return NULL; 679 680 for (i = 0; i < hpet_num_timers; i++) { 681 struct hpet_dev *hdev = &hpet_devs[i]; 682 683 if (!(hdev->flags & HPET_DEV_VALID)) 684 continue; 685 if (test_and_set_bit(HPET_DEV_USED_BIT, 686 (unsigned long *)&hdev->flags)) 687 continue; 688 return hdev; 689 } 690 return NULL; 691 } 692 693 struct hpet_work_struct { 694 struct delayed_work work; 695 struct completion complete; 696 }; 697 698 static void hpet_work(struct work_struct *w) 699 { 700 struct hpet_dev *hdev; 701 int cpu = smp_processor_id(); 702 struct hpet_work_struct *hpet_work; 703 704 hpet_work = container_of(w, struct hpet_work_struct, work.work); 705 706 hdev = hpet_get_unused_timer(); 707 if (hdev) 708 init_one_hpet_msi_clockevent(hdev, cpu); 709 710 complete(&hpet_work->complete); 711 } 712 713 static int hpet_cpuhp_online(unsigned int cpu) 714 { 715 struct hpet_work_struct work; 716 717 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); 718 init_completion(&work.complete); 719 /* FIXME: add schedule_work_on() */ 720 schedule_delayed_work_on(cpu, &work.work, 0); 721 wait_for_completion(&work.complete); 722 destroy_delayed_work_on_stack(&work.work); 723 return 0; 724 } 725 726 static int hpet_cpuhp_dead(unsigned int cpu) 727 { 728 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 729 730 if (!hdev) 731 return 0; 732 free_irq(hdev->irq, hdev); 733 hdev->flags &= ~HPET_DEV_USED; 734 per_cpu(cpu_hpet_dev, cpu) = NULL; 735 return 0; 736 } 737 #else 738 739 static void hpet_msi_capability_lookup(unsigned int start_timer) 740 { 741 return; 742 } 743 744 #ifdef CONFIG_HPET 745 static void hpet_reserve_msi_timers(struct hpet_data *hd) 746 { 747 return; 748 } 749 #endif 750 751 #define hpet_cpuhp_online NULL 752 #define hpet_cpuhp_dead NULL 753 754 #endif 755 756 /* 757 * Clock source related code 758 */ 759 static cycle_t read_hpet(struct clocksource *cs) 760 { 761 return (cycle_t)hpet_readl(HPET_COUNTER); 762 } 763 764 static struct clocksource clocksource_hpet = { 765 .name = "hpet", 766 .rating = 250, 767 .read = read_hpet, 768 .mask = HPET_MASK, 769 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 770 .resume = hpet_resume_counter, 771 }; 772 773 static int hpet_clocksource_register(void) 774 { 775 u64 start, now; 776 cycle_t t1; 777 778 /* Start the counter */ 779 hpet_restart_counter(); 780 781 /* Verify whether hpet counter works */ 782 t1 = hpet_readl(HPET_COUNTER); 783 start = rdtsc(); 784 785 /* 786 * We don't know the TSC frequency yet, but waiting for 787 * 200000 TSC cycles is safe: 788 * 4 GHz == 50us 789 * 1 GHz == 200us 790 */ 791 do { 792 rep_nop(); 793 now = rdtsc(); 794 } while ((now - start) < 200000UL); 795 796 if (t1 == hpet_readl(HPET_COUNTER)) { 797 printk(KERN_WARNING 798 "HPET counter not counting. HPET disabled\n"); 799 return -ENODEV; 800 } 801 802 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 803 return 0; 804 } 805 806 static u32 *hpet_boot_cfg; 807 808 /** 809 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 810 */ 811 int __init hpet_enable(void) 812 { 813 u32 hpet_period, cfg, id; 814 u64 freq; 815 unsigned int i, last; 816 817 if (!is_hpet_capable()) 818 return 0; 819 820 hpet_set_mapping(); 821 822 /* 823 * Read the period and check for a sane value: 824 */ 825 hpet_period = hpet_readl(HPET_PERIOD); 826 827 /* 828 * AMD SB700 based systems with spread spectrum enabled use a 829 * SMM based HPET emulation to provide proper frequency 830 * setting. The SMM code is initialized with the first HPET 831 * register access and takes some time to complete. During 832 * this time the config register reads 0xffffffff. We check 833 * for max. 1000 loops whether the config register reads a non 834 * 0xffffffff value to make sure that HPET is up and running 835 * before we go further. A counting loop is safe, as the HPET 836 * access takes thousands of CPU cycles. On non SB700 based 837 * machines this check is only done once and has no side 838 * effects. 839 */ 840 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 841 if (i == 1000) { 842 printk(KERN_WARNING 843 "HPET config register value = 0xFFFFFFFF. " 844 "Disabling HPET\n"); 845 goto out_nohpet; 846 } 847 } 848 849 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 850 goto out_nohpet; 851 852 /* 853 * The period is a femto seconds value. Convert it to a 854 * frequency. 855 */ 856 freq = FSEC_PER_SEC; 857 do_div(freq, hpet_period); 858 hpet_freq = freq; 859 860 /* 861 * Read the HPET ID register to retrieve the IRQ routing 862 * information and the number of channels 863 */ 864 id = hpet_readl(HPET_ID); 865 hpet_print_config(); 866 867 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; 868 869 #ifdef CONFIG_HPET_EMULATE_RTC 870 /* 871 * The legacy routing mode needs at least two channels, tick timer 872 * and the rtc emulation channel. 873 */ 874 if (!last) 875 goto out_nohpet; 876 #endif 877 878 cfg = hpet_readl(HPET_CFG); 879 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg), 880 GFP_KERNEL); 881 if (hpet_boot_cfg) 882 *hpet_boot_cfg = cfg; 883 else 884 pr_warn("HPET initial state will not be saved\n"); 885 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); 886 hpet_writel(cfg, HPET_CFG); 887 if (cfg) 888 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n", 889 cfg); 890 891 for (i = 0; i <= last; ++i) { 892 cfg = hpet_readl(HPET_Tn_CFG(i)); 893 if (hpet_boot_cfg) 894 hpet_boot_cfg[i + 1] = cfg; 895 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); 896 hpet_writel(cfg, HPET_Tn_CFG(i)); 897 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP 898 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE 899 | HPET_TN_FSB | HPET_TN_FSB_CAP); 900 if (cfg) 901 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n", 902 cfg, i); 903 } 904 hpet_print_config(); 905 906 if (hpet_clocksource_register()) 907 goto out_nohpet; 908 909 if (id & HPET_ID_LEGSUP) { 910 hpet_legacy_clockevent_register(); 911 return 1; 912 } 913 return 0; 914 915 out_nohpet: 916 hpet_clear_mapping(); 917 hpet_address = 0; 918 return 0; 919 } 920 921 /* 922 * Needs to be late, as the reserve_timer code calls kalloc ! 923 * 924 * Not a problem on i386 as hpet_enable is called from late_time_init, 925 * but on x86_64 it is necessary ! 926 */ 927 static __init int hpet_late_init(void) 928 { 929 int ret; 930 931 if (boot_hpet_disable) 932 return -ENODEV; 933 934 if (!hpet_address) { 935 if (!force_hpet_address) 936 return -ENODEV; 937 938 hpet_address = force_hpet_address; 939 hpet_enable(); 940 } 941 942 if (!hpet_virt_address) 943 return -ENODEV; 944 945 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 946 hpet_msi_capability_lookup(2); 947 else 948 hpet_msi_capability_lookup(0); 949 950 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 951 hpet_print_config(); 952 953 if (hpet_msi_disable) 954 return 0; 955 956 if (boot_cpu_has(X86_FEATURE_ARAT)) 957 return 0; 958 959 /* This notifier should be called after workqueue is ready */ 960 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "AP_X86_HPET_ONLINE", 961 hpet_cpuhp_online, NULL); 962 if (ret) 963 return ret; 964 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "X86_HPET_DEAD", NULL, 965 hpet_cpuhp_dead); 966 if (ret) 967 goto err_cpuhp; 968 return 0; 969 970 err_cpuhp: 971 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); 972 return ret; 973 } 974 fs_initcall(hpet_late_init); 975 976 void hpet_disable(void) 977 { 978 if (is_hpet_capable() && hpet_virt_address) { 979 unsigned int cfg = hpet_readl(HPET_CFG), id, last; 980 981 if (hpet_boot_cfg) 982 cfg = *hpet_boot_cfg; 983 else if (hpet_legacy_int_enabled) { 984 cfg &= ~HPET_CFG_LEGACY; 985 hpet_legacy_int_enabled = false; 986 } 987 cfg &= ~HPET_CFG_ENABLE; 988 hpet_writel(cfg, HPET_CFG); 989 990 if (!hpet_boot_cfg) 991 return; 992 993 id = hpet_readl(HPET_ID); 994 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 995 996 for (id = 0; id <= last; ++id) 997 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); 998 999 if (*hpet_boot_cfg & HPET_CFG_ENABLE) 1000 hpet_writel(*hpet_boot_cfg, HPET_CFG); 1001 } 1002 } 1003 1004 #ifdef CONFIG_HPET_EMULATE_RTC 1005 1006 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 1007 * is enabled, we support RTC interrupt functionality in software. 1008 * RTC has 3 kinds of interrupts: 1009 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 1010 * is updated 1011 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 1012 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 1013 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 1014 * (1) and (2) above are implemented using polling at a frequency of 1015 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 1016 * overhead. (DEFAULT_RTC_INT_FREQ) 1017 * For (3), we use interrupts at 64Hz or user specified periodic 1018 * frequency, whichever is higher. 1019 */ 1020 #include <linux/mc146818rtc.h> 1021 #include <linux/rtc.h> 1022 1023 #define DEFAULT_RTC_INT_FREQ 64 1024 #define DEFAULT_RTC_SHIFT 6 1025 #define RTC_NUM_INTS 1 1026 1027 static unsigned long hpet_rtc_flags; 1028 static int hpet_prev_update_sec; 1029 static struct rtc_time hpet_alarm_time; 1030 static unsigned long hpet_pie_count; 1031 static u32 hpet_t1_cmp; 1032 static u32 hpet_default_delta; 1033 static u32 hpet_pie_delta; 1034 static unsigned long hpet_pie_limit; 1035 1036 static rtc_irq_handler irq_handler; 1037 1038 /* 1039 * Check that the hpet counter c1 is ahead of the c2 1040 */ 1041 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1042 { 1043 return (s32)(c2 - c1) < 0; 1044 } 1045 1046 /* 1047 * Registers a IRQ handler. 1048 */ 1049 int hpet_register_irq_handler(rtc_irq_handler handler) 1050 { 1051 if (!is_hpet_enabled()) 1052 return -ENODEV; 1053 if (irq_handler) 1054 return -EBUSY; 1055 1056 irq_handler = handler; 1057 1058 return 0; 1059 } 1060 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1061 1062 /* 1063 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1064 * and does cleanup. 1065 */ 1066 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1067 { 1068 if (!is_hpet_enabled()) 1069 return; 1070 1071 irq_handler = NULL; 1072 hpet_rtc_flags = 0; 1073 } 1074 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1075 1076 /* 1077 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1078 * is not supported by all HPET implementations for timer 1. 1079 * 1080 * hpet_rtc_timer_init() is called when the rtc is initialized. 1081 */ 1082 int hpet_rtc_timer_init(void) 1083 { 1084 unsigned int cfg, cnt, delta; 1085 unsigned long flags; 1086 1087 if (!is_hpet_enabled()) 1088 return 0; 1089 1090 if (!hpet_default_delta) { 1091 uint64_t clc; 1092 1093 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1094 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1095 hpet_default_delta = clc; 1096 } 1097 1098 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1099 delta = hpet_default_delta; 1100 else 1101 delta = hpet_pie_delta; 1102 1103 local_irq_save(flags); 1104 1105 cnt = delta + hpet_readl(HPET_COUNTER); 1106 hpet_writel(cnt, HPET_T1_CMP); 1107 hpet_t1_cmp = cnt; 1108 1109 cfg = hpet_readl(HPET_T1_CFG); 1110 cfg &= ~HPET_TN_PERIODIC; 1111 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1112 hpet_writel(cfg, HPET_T1_CFG); 1113 1114 local_irq_restore(flags); 1115 1116 return 1; 1117 } 1118 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1119 1120 static void hpet_disable_rtc_channel(void) 1121 { 1122 u32 cfg = hpet_readl(HPET_T1_CFG); 1123 cfg &= ~HPET_TN_ENABLE; 1124 hpet_writel(cfg, HPET_T1_CFG); 1125 } 1126 1127 /* 1128 * The functions below are called from rtc driver. 1129 * Return 0 if HPET is not being used. 1130 * Otherwise do the necessary changes and return 1. 1131 */ 1132 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1133 { 1134 if (!is_hpet_enabled()) 1135 return 0; 1136 1137 hpet_rtc_flags &= ~bit_mask; 1138 if (unlikely(!hpet_rtc_flags)) 1139 hpet_disable_rtc_channel(); 1140 1141 return 1; 1142 } 1143 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1144 1145 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1146 { 1147 unsigned long oldbits = hpet_rtc_flags; 1148 1149 if (!is_hpet_enabled()) 1150 return 0; 1151 1152 hpet_rtc_flags |= bit_mask; 1153 1154 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1155 hpet_prev_update_sec = -1; 1156 1157 if (!oldbits) 1158 hpet_rtc_timer_init(); 1159 1160 return 1; 1161 } 1162 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1163 1164 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1165 unsigned char sec) 1166 { 1167 if (!is_hpet_enabled()) 1168 return 0; 1169 1170 hpet_alarm_time.tm_hour = hrs; 1171 hpet_alarm_time.tm_min = min; 1172 hpet_alarm_time.tm_sec = sec; 1173 1174 return 1; 1175 } 1176 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1177 1178 int hpet_set_periodic_freq(unsigned long freq) 1179 { 1180 uint64_t clc; 1181 1182 if (!is_hpet_enabled()) 1183 return 0; 1184 1185 if (freq <= DEFAULT_RTC_INT_FREQ) 1186 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1187 else { 1188 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1189 do_div(clc, freq); 1190 clc >>= hpet_clockevent.shift; 1191 hpet_pie_delta = clc; 1192 hpet_pie_limit = 0; 1193 } 1194 return 1; 1195 } 1196 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1197 1198 int hpet_rtc_dropped_irq(void) 1199 { 1200 return is_hpet_enabled(); 1201 } 1202 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1203 1204 static void hpet_rtc_timer_reinit(void) 1205 { 1206 unsigned int delta; 1207 int lost_ints = -1; 1208 1209 if (unlikely(!hpet_rtc_flags)) 1210 hpet_disable_rtc_channel(); 1211 1212 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1213 delta = hpet_default_delta; 1214 else 1215 delta = hpet_pie_delta; 1216 1217 /* 1218 * Increment the comparator value until we are ahead of the 1219 * current count. 1220 */ 1221 do { 1222 hpet_t1_cmp += delta; 1223 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1224 lost_ints++; 1225 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1226 1227 if (lost_ints) { 1228 if (hpet_rtc_flags & RTC_PIE) 1229 hpet_pie_count += lost_ints; 1230 if (printk_ratelimit()) 1231 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1232 lost_ints); 1233 } 1234 } 1235 1236 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1237 { 1238 struct rtc_time curr_time; 1239 unsigned long rtc_int_flag = 0; 1240 1241 hpet_rtc_timer_reinit(); 1242 memset(&curr_time, 0, sizeof(struct rtc_time)); 1243 1244 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1245 mc146818_set_time(&curr_time); 1246 1247 if (hpet_rtc_flags & RTC_UIE && 1248 curr_time.tm_sec != hpet_prev_update_sec) { 1249 if (hpet_prev_update_sec >= 0) 1250 rtc_int_flag = RTC_UF; 1251 hpet_prev_update_sec = curr_time.tm_sec; 1252 } 1253 1254 if (hpet_rtc_flags & RTC_PIE && 1255 ++hpet_pie_count >= hpet_pie_limit) { 1256 rtc_int_flag |= RTC_PF; 1257 hpet_pie_count = 0; 1258 } 1259 1260 if (hpet_rtc_flags & RTC_AIE && 1261 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1262 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1263 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1264 rtc_int_flag |= RTC_AF; 1265 1266 if (rtc_int_flag) { 1267 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1268 if (irq_handler) 1269 irq_handler(rtc_int_flag, dev_id); 1270 } 1271 return IRQ_HANDLED; 1272 } 1273 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1274 #endif 1275