xref: /linux/arch/x86/kernel/head_64.S (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732) 
1/*
2 *  linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
3 *
4 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
9 */
10
11
12#include <linux/linkage.h>
13#include <linux/threads.h>
14#include <linux/init.h>
15#include <asm/segment.h>
16#include <asm/pgtable.h>
17#include <asm/page.h>
18#include <asm/msr.h>
19#include <asm/cache.h>
20#include <asm/processor-flags.h>
21#include <asm/percpu.h>
22#include <asm/nops.h>
23
24#ifdef CONFIG_PARAVIRT
25#include <asm/asm-offsets.h>
26#include <asm/paravirt.h>
27#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
28#else
29#define GET_CR2_INTO(reg) movq %cr2, reg
30#define INTERRUPT_RETURN iretq
31#endif
32
33/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
34 * because we need identity-mapped pages.
35 *
36 */
37
38#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
39
40L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
41L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
42L4_START_KERNEL = pgd_index(__START_KERNEL_map)
43L3_START_KERNEL = pud_index(__START_KERNEL_map)
44
45	.text
46	__HEAD
47	.code64
48	.globl startup_64
49startup_64:
50	/*
51	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
52	 * and someone has loaded an identity mapped page table
53	 * for us.  These identity mapped page tables map all of the
54	 * kernel pages and possibly all of memory.
55	 *
56	 * %rsi holds a physical pointer to real_mode_data.
57	 *
58	 * We come here either directly from a 64bit bootloader, or from
59	 * arch/x86/boot/compressed/head_64.S.
60	 *
61	 * We only come here initially at boot nothing else comes here.
62	 *
63	 * Since we may be loaded at an address different from what we were
64	 * compiled to run at we first fixup the physical addresses in our page
65	 * tables and then reload them.
66	 */
67
68	/*
69	 * Compute the delta between the address I am compiled to run at and the
70	 * address I am actually running at.
71	 */
72	leaq	_text(%rip), %rbp
73	subq	$_text - __START_KERNEL_map, %rbp
74
75	/* Is the address not 2M aligned? */
76	movq	%rbp, %rax
77	andl	$~PMD_PAGE_MASK, %eax
78	testl	%eax, %eax
79	jnz	bad_address
80
81	/*
82	 * Is the address too large?
83	 */
84	leaq	_text(%rip), %rax
85	shrq	$MAX_PHYSMEM_BITS, %rax
86	jnz	bad_address
87
88	/*
89	 * Fixup the physical addresses in the page table
90	 */
91	addq	%rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
92
93	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
94	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)
95
96	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)
97
98	/*
99	 * Set up the identity mapping for the switchover.  These
100	 * entries should *NOT* have the global bit set!  This also
101	 * creates a bunch of nonsense entries but that is fine --
102	 * it avoids problems around wraparound.
103	 */
104	leaq	_text(%rip), %rdi
105	leaq	early_level4_pgt(%rip), %rbx
106
107	movq	%rdi, %rax
108	shrq	$PGDIR_SHIFT, %rax
109
110	leaq	(4096 + _KERNPG_TABLE)(%rbx), %rdx
111	movq	%rdx, 0(%rbx,%rax,8)
112	movq	%rdx, 8(%rbx,%rax,8)
113
114	addq	$4096, %rdx
115	movq	%rdi, %rax
116	shrq	$PUD_SHIFT, %rax
117	andl	$(PTRS_PER_PUD-1), %eax
118	movq	%rdx, 4096(%rbx,%rax,8)
119	incl	%eax
120	andl	$(PTRS_PER_PUD-1), %eax
121	movq	%rdx, 4096(%rbx,%rax,8)
122
123	addq	$8192, %rbx
124	movq	%rdi, %rax
125	shrq	$PMD_SHIFT, %rdi
126	addq	$(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
127	leaq	(_end - 1)(%rip), %rcx
128	shrq	$PMD_SHIFT, %rcx
129	subq	%rdi, %rcx
130	incl	%ecx
131
1321:
133	andq	$(PTRS_PER_PMD - 1), %rdi
134	movq	%rax, (%rbx,%rdi,8)
135	incq	%rdi
136	addq	$PMD_SIZE, %rax
137	decl	%ecx
138	jnz	1b
139
140	/*
141	 * Fixup the kernel text+data virtual addresses. Note that
142	 * we might write invalid pmds, when the kernel is relocated
143	 * cleanup_highmap() fixes this up along with the mappings
144	 * beyond _end.
145	 */
146	leaq	level2_kernel_pgt(%rip), %rdi
147	leaq	4096(%rdi), %r8
148	/* See if it is a valid page table entry */
1491:	testb	$1, 0(%rdi)
150	jz	2f
151	addq	%rbp, 0(%rdi)
152	/* Go to the next page */
1532:	addq	$8, %rdi
154	cmp	%r8, %rdi
155	jne	1b
156
157	/* Fixup phys_base */
158	addq	%rbp, phys_base(%rip)
159
160	movq	$(early_level4_pgt - __START_KERNEL_map), %rax
161	jmp 1f
162ENTRY(secondary_startup_64)
163	/*
164	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
165	 * and someone has loaded a mapped page table.
166	 *
167	 * %rsi holds a physical pointer to real_mode_data.
168	 *
169	 * We come here either from startup_64 (using physical addresses)
170	 * or from trampoline.S (using virtual addresses).
171	 *
172	 * Using virtual addresses from trampoline.S removes the need
173	 * to have any identity mapped pages in the kernel page table
174	 * after the boot processor executes this code.
175	 */
176
177	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
1781:
179
180	/* Enable PAE mode and PGE */
181	movl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
182	movq	%rcx, %cr4
183
184	/* Setup early boot stage 4 level pagetables. */
185	addq	phys_base(%rip), %rax
186	movq	%rax, %cr3
187
188	/* Ensure I am executing from virtual addresses */
189	movq	$1f, %rax
190	jmp	*%rax
1911:
192
193	/* Check if nx is implemented */
194	movl	$0x80000001, %eax
195	cpuid
196	movl	%edx,%edi
197
198	/* Setup EFER (Extended Feature Enable Register) */
199	movl	$MSR_EFER, %ecx
200	rdmsr
201	btsl	$_EFER_SCE, %eax	/* Enable System Call */
202	btl	$20,%edi		/* No Execute supported? */
203	jnc     1f
204	btsl	$_EFER_NX, %eax
205	btsq	$_PAGE_BIT_NX,early_pmd_flags(%rip)
2061:	wrmsr				/* Make changes effective */
207
208	/* Setup cr0 */
209#define CR0_STATE	(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
210			 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
211			 X86_CR0_PG)
212	movl	$CR0_STATE, %eax
213	/* Make changes effective */
214	movq	%rax, %cr0
215
216	/* Setup a boot time stack */
217	movq stack_start(%rip), %rsp
218
219	/* zero EFLAGS after setting rsp */
220	pushq $0
221	popfq
222
223	/*
224	 * We must switch to a new descriptor in kernel space for the GDT
225	 * because soon the kernel won't have access anymore to the userspace
226	 * addresses where we're currently running on. We have to do that here
227	 * because in 32bit we couldn't load a 64bit linear address.
228	 */
229	lgdt	early_gdt_descr(%rip)
230
231	/* set up data segments */
232	xorl %eax,%eax
233	movl %eax,%ds
234	movl %eax,%ss
235	movl %eax,%es
236
237	/*
238	 * We don't really need to load %fs or %gs, but load them anyway
239	 * to kill any stale realmode selectors.  This allows execution
240	 * under VT hardware.
241	 */
242	movl %eax,%fs
243	movl %eax,%gs
244
245	/* Set up %gs.
246	 *
247	 * The base of %gs always points to the bottom of the irqstack
248	 * union.  If the stack protector canary is enabled, it is
249	 * located at %gs:40.  Note that, on SMP, the boot cpu uses
250	 * init data section till per cpu areas are set up.
251	 */
252	movl	$MSR_GS_BASE,%ecx
253	movl	initial_gs(%rip),%eax
254	movl	initial_gs+4(%rip),%edx
255	wrmsr
256
257	/* rsi is pointer to real mode structure with interesting info.
258	   pass it to C */
259	movq	%rsi, %rdi
260
261	/* Finally jump to run C code and to be on real kernel address
262	 * Since we are running on identity-mapped space we have to jump
263	 * to the full 64bit address, this is only possible as indirect
264	 * jump.  In addition we need to ensure %cs is set so we make this
265	 * a far return.
266	 *
267	 * Note: do not change to far jump indirect with 64bit offset.
268	 *
269	 * AMD does not support far jump indirect with 64bit offset.
270	 * AMD64 Architecture Programmer's Manual, Volume 3: states only
271	 *	JMP FAR mem16:16 FF /5 Far jump indirect,
272	 *		with the target specified by a far pointer in memory.
273	 *	JMP FAR mem16:32 FF /5 Far jump indirect,
274	 *		with the target specified by a far pointer in memory.
275	 *
276	 * Intel64 does support 64bit offset.
277	 * Software Developer Manual Vol 2: states:
278	 *	FF /5 JMP m16:16 Jump far, absolute indirect,
279	 *		address given in m16:16
280	 *	FF /5 JMP m16:32 Jump far, absolute indirect,
281	 *		address given in m16:32.
282	 *	REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
283	 *		address given in m16:64.
284	 */
285	movq	initial_code(%rip),%rax
286	pushq	$0		# fake return address to stop unwinder
287	pushq	$__KERNEL_CS	# set correct cs
288	pushq	%rax		# target address in negative space
289	lretq
290
291#ifdef CONFIG_HOTPLUG_CPU
292/*
293 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
294 * up already except stack. We just set up stack here. Then call
295 * start_secondary().
296 */
297ENTRY(start_cpu0)
298	movq stack_start(%rip),%rsp
299	movq	initial_code(%rip),%rax
300	pushq	$0		# fake return address to stop unwinder
301	pushq	$__KERNEL_CS	# set correct cs
302	pushq	%rax		# target address in negative space
303	lretq
304ENDPROC(start_cpu0)
305#endif
306
307	/* SMP bootup changes these two */
308	__REFDATA
309	.balign	8
310	GLOBAL(initial_code)
311	.quad	x86_64_start_kernel
312	GLOBAL(initial_gs)
313	.quad	INIT_PER_CPU_VAR(irq_stack_union)
314
315	GLOBAL(stack_start)
316	.quad  init_thread_union+THREAD_SIZE-8
317	.word  0
318	__FINITDATA
319
320bad_address:
321	jmp bad_address
322
323	__INIT
324ENTRY(early_idt_handler_array)
325	# 104(%rsp) %rflags
326	#  96(%rsp) %cs
327	#  88(%rsp) %rip
328	#  80(%rsp) error code
329	i = 0
330	.rept NUM_EXCEPTION_VECTORS
331	.ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1
332	pushq $0		# Dummy error code, to make stack frame uniform
333	.endif
334	pushq $i		# 72(%rsp) Vector number
335	jmp early_idt_handler_common
336	i = i + 1
337	.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
338	.endr
339ENDPROC(early_idt_handler_array)
340
341early_idt_handler_common:
342	/*
343	 * The stack is the hardware frame, an error code or zero, and the
344	 * vector number.
345	 */
346	cld
347
348	cmpl $2,(%rsp)		# X86_TRAP_NMI
349	je .Lis_nmi		# Ignore NMI
350
351	cmpl $2,early_recursion_flag(%rip)
352	jz  1f
353	incl early_recursion_flag(%rip)
354
355	pushq %rax		# 64(%rsp)
356	pushq %rcx		# 56(%rsp)
357	pushq %rdx		# 48(%rsp)
358	pushq %rsi		# 40(%rsp)
359	pushq %rdi		# 32(%rsp)
360	pushq %r8		# 24(%rsp)
361	pushq %r9		# 16(%rsp)
362	pushq %r10		#  8(%rsp)
363	pushq %r11		#  0(%rsp)
364
365	cmpl $__KERNEL_CS,96(%rsp)
366	jne 11f
367
368	cmpl $14,72(%rsp)	# Page fault?
369	jnz 10f
370	GET_CR2_INTO(%rdi)	# can clobber any volatile register if pv
371	call early_make_pgtable
372	andl %eax,%eax
373	jz 20f			# All good
374
37510:
376	leaq 88(%rsp),%rdi	# Pointer to %rip
377	call early_fixup_exception
378	andl %eax,%eax
379	jnz 20f			# Found an exception entry
380
38111:
382#ifdef CONFIG_EARLY_PRINTK
383	GET_CR2_INTO(%r9)	# can clobber any volatile register if pv
384	movl 80(%rsp),%r8d	# error code
385	movl 72(%rsp),%esi	# vector number
386	movl 96(%rsp),%edx	# %cs
387	movq 88(%rsp),%rcx	# %rip
388	xorl %eax,%eax
389	leaq early_idt_msg(%rip),%rdi
390	call early_printk
391	cmpl $2,early_recursion_flag(%rip)
392	jz  1f
393	call dump_stack
394#ifdef CONFIG_KALLSYMS
395	leaq early_idt_ripmsg(%rip),%rdi
396	movq 40(%rsp),%rsi	# %rip again
397	call __print_symbol
398#endif
399#endif /* EARLY_PRINTK */
4001:	hlt
401	jmp 1b
402
40320:	# Exception table entry found or page table generated
404	popq %r11
405	popq %r10
406	popq %r9
407	popq %r8
408	popq %rdi
409	popq %rsi
410	popq %rdx
411	popq %rcx
412	popq %rax
413	decl early_recursion_flag(%rip)
414.Lis_nmi:
415	addq $16,%rsp		# drop vector number and error code
416	INTERRUPT_RETURN
417ENDPROC(early_idt_handler_common)
418
419	__INITDATA
420
421	.balign 4
422early_recursion_flag:
423	.long 0
424
425#ifdef CONFIG_EARLY_PRINTK
426early_idt_msg:
427	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
428early_idt_ripmsg:
429	.asciz "RIP %s\n"
430#endif /* CONFIG_EARLY_PRINTK */
431
432#define NEXT_PAGE(name) \
433	.balign	PAGE_SIZE; \
434GLOBAL(name)
435
436/* Automate the creation of 1 to 1 mapping pmd entries */
437#define PMDS(START, PERM, COUNT)			\
438	i = 0 ;						\
439	.rept (COUNT) ;					\
440	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
441	i = i + 1 ;					\
442	.endr
443
444	__INITDATA
445NEXT_PAGE(early_level4_pgt)
446	.fill	511,8,0
447	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
448
449NEXT_PAGE(early_dynamic_pgts)
450	.fill	512*EARLY_DYNAMIC_PAGE_TABLES,8,0
451
452	.data
453
454#ifndef CONFIG_XEN
455NEXT_PAGE(init_level4_pgt)
456	.fill	512,8,0
457#else
458NEXT_PAGE(init_level4_pgt)
459	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
460	.org    init_level4_pgt + L4_PAGE_OFFSET*8, 0
461	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
462	.org    init_level4_pgt + L4_START_KERNEL*8, 0
463	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
464	.quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
465
466NEXT_PAGE(level3_ident_pgt)
467	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
468	.fill	511, 8, 0
469NEXT_PAGE(level2_ident_pgt)
470	/* Since I easily can, map the first 1G.
471	 * Don't set NX because code runs from these pages.
472	 */
473	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
474#endif
475
476NEXT_PAGE(level3_kernel_pgt)
477	.fill	L3_START_KERNEL,8,0
478	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
479	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
480	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
481
482NEXT_PAGE(level2_kernel_pgt)
483	/*
484	 * 512 MB kernel mapping. We spend a full page on this pagetable
485	 * anyway.
486	 *
487	 * The kernel code+data+bss must not be bigger than that.
488	 *
489	 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
490	 *  If you want to increase this then increase MODULES_VADDR
491	 *  too.)
492	 */
493	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
494		KERNEL_IMAGE_SIZE/PMD_SIZE)
495
496NEXT_PAGE(level2_fixmap_pgt)
497	.fill	506,8,0
498	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
499	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
500	.fill	5,8,0
501
502NEXT_PAGE(level1_fixmap_pgt)
503	.fill	512,8,0
504
505#undef PMDS
506
507	.data
508	.align 16
509	.globl early_gdt_descr
510early_gdt_descr:
511	.word	GDT_ENTRIES*8-1
512early_gdt_descr_base:
513	.quad	INIT_PER_CPU_VAR(gdt_page)
514
515ENTRY(phys_base)
516	/* This must match the first entry in level2_kernel_pgt */
517	.quad   0x0000000000000000
518
519#include "../../x86/xen/xen-head.S"
520
521	__PAGE_ALIGNED_BSS
522NEXT_PAGE(empty_zero_page)
523	.skip PAGE_SIZE
524
525