1 /* 2 * x86 FPU boot time init code: 3 */ 4 #include <asm/fpu/internal.h> 5 #include <asm/tlbflush.h> 6 7 /* 8 * Initialize the TS bit in CR0 according to the style of context-switches 9 * we are using: 10 */ 11 static void fpu__init_cpu_ctx_switch(void) 12 { 13 if (!cpu_has_eager_fpu) 14 stts(); 15 else 16 clts(); 17 } 18 19 /* 20 * Initialize the registers found in all CPUs, CR0 and CR4: 21 */ 22 static void fpu__init_cpu_generic(void) 23 { 24 unsigned long cr0; 25 unsigned long cr4_mask = 0; 26 27 if (cpu_has_fxsr) 28 cr4_mask |= X86_CR4_OSFXSR; 29 if (cpu_has_xmm) 30 cr4_mask |= X86_CR4_OSXMMEXCPT; 31 if (cr4_mask) 32 cr4_set_bits(cr4_mask); 33 34 cr0 = read_cr0(); 35 cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */ 36 if (!cpu_has_fpu) 37 cr0 |= X86_CR0_EM; 38 write_cr0(cr0); 39 40 /* Flush out any pending x87 state: */ 41 asm volatile ("fninit"); 42 } 43 44 /* 45 * Enable all supported FPU features. Called when a CPU is brought online: 46 */ 47 void fpu__init_cpu(void) 48 { 49 fpu__init_cpu_generic(); 50 fpu__init_cpu_xstate(); 51 fpu__init_cpu_ctx_switch(); 52 } 53 54 /* 55 * The earliest FPU detection code. 56 * 57 * Set the X86_FEATURE_FPU CPU-capability bit based on 58 * trying to execute an actual sequence of FPU instructions: 59 */ 60 static void fpu__init_system_early_generic(struct cpuinfo_x86 *c) 61 { 62 unsigned long cr0; 63 u16 fsw, fcw; 64 65 fsw = fcw = 0xffff; 66 67 cr0 = read_cr0(); 68 cr0 &= ~(X86_CR0_TS | X86_CR0_EM); 69 write_cr0(cr0); 70 71 asm volatile("fninit ; fnstsw %0 ; fnstcw %1" 72 : "+m" (fsw), "+m" (fcw)); 73 74 if (fsw == 0 && (fcw & 0x103f) == 0x003f) 75 set_cpu_cap(c, X86_FEATURE_FPU); 76 else 77 clear_cpu_cap(c, X86_FEATURE_FPU); 78 79 #ifndef CONFIG_MATH_EMULATION 80 if (!cpu_has_fpu) { 81 pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n"); 82 for (;;) 83 asm volatile("hlt"); 84 } 85 #endif 86 } 87 88 /* 89 * Boot time FPU feature detection code: 90 */ 91 unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; 92 93 static void __init fpu__init_system_mxcsr(void) 94 { 95 unsigned int mask = 0; 96 97 if (cpu_has_fxsr) { 98 /* Static because GCC does not get 16-byte stack alignment right: */ 99 static struct fxregs_state fxregs __initdata; 100 101 asm volatile("fxsave %0" : "+m" (fxregs)); 102 103 mask = fxregs.mxcsr_mask; 104 105 /* 106 * If zero then use the default features mask, 107 * which has all features set, except the 108 * denormals-are-zero feature bit: 109 */ 110 if (mask == 0) 111 mask = 0x0000ffbf; 112 } 113 mxcsr_feature_mask &= mask; 114 } 115 116 /* 117 * Once per bootup FPU initialization sequences that will run on most x86 CPUs: 118 */ 119 static void __init fpu__init_system_generic(void) 120 { 121 /* 122 * Set up the legacy init FPU context. (xstate init might overwrite this 123 * with a more modern format, if the CPU supports it.) 124 */ 125 fpstate_init_fxstate(&init_fpstate.fxsave); 126 127 fpu__init_system_mxcsr(); 128 } 129 130 /* 131 * Size of the FPU context state. All tasks in the system use the 132 * same context size, regardless of what portion they use. 133 * This is inherent to the XSAVE architecture which puts all state 134 * components into a single, continuous memory block: 135 */ 136 unsigned int xstate_size; 137 EXPORT_SYMBOL_GPL(xstate_size); 138 139 /* 140 * Set up the xstate_size based on the legacy FPU context size. 141 * 142 * We set this up first, and later it will be overwritten by 143 * fpu__init_system_xstate() if the CPU knows about xstates. 144 */ 145 static void __init fpu__init_system_xstate_size_legacy(void) 146 { 147 static int on_boot_cpu = 1; 148 149 WARN_ON_FPU(!on_boot_cpu); 150 on_boot_cpu = 0; 151 152 /* 153 * Note that xstate_size might be overwriten later during 154 * fpu__init_system_xstate(). 155 */ 156 157 if (!cpu_has_fpu) { 158 /* 159 * Disable xsave as we do not support it if i387 160 * emulation is enabled. 161 */ 162 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 164 xstate_size = sizeof(struct swregs_state); 165 } else { 166 if (cpu_has_fxsr) 167 xstate_size = sizeof(struct fxregs_state); 168 else 169 xstate_size = sizeof(struct fregs_state); 170 } 171 /* 172 * Quirk: we don't yet handle the XSAVES* instructions 173 * correctly, as we don't correctly convert between 174 * standard and compacted format when interfacing 175 * with user-space - so disable it for now. 176 * 177 * The difference is small: with recent CPUs the 178 * compacted format is only marginally smaller than 179 * the standard FPU state format. 180 * 181 * ( This is easy to backport while we are fixing 182 * XSAVES* support. ) 183 */ 184 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 185 } 186 187 /* 188 * FPU context switching strategies: 189 * 190 * Against popular belief, we don't do lazy FPU saves, due to the 191 * task migration complications it brings on SMP - we only do 192 * lazy FPU restores. 193 * 194 * 'lazy' is the traditional strategy, which is based on setting 195 * CR0::TS to 1 during context-switch (instead of doing a full 196 * restore of the FPU state), which causes the first FPU instruction 197 * after the context switch (whenever it is executed) to fault - at 198 * which point we lazily restore the FPU state into FPU registers. 199 * 200 * Tasks are of course under no obligation to execute FPU instructions, 201 * so it can easily happen that another context-switch occurs without 202 * a single FPU instruction being executed. If we eventually switch 203 * back to the original task (that still owns the FPU) then we have 204 * not only saved the restores along the way, but we also have the 205 * FPU ready to be used for the original task. 206 * 207 * 'eager' switching is used on modern CPUs, there we switch the FPU 208 * state during every context switch, regardless of whether the task 209 * has used FPU instructions in that time slice or not. This is done 210 * because modern FPU context saving instructions are able to optimize 211 * state saving and restoration in hardware: they can detect both 212 * unused and untouched FPU state and optimize accordingly. 213 * 214 * [ Note that even in 'lazy' mode we might optimize context switches 215 * to use 'eager' restores, if we detect that a task is using the FPU 216 * frequently. See the fpu->counter logic in fpu/internal.h for that. ] 217 */ 218 static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO; 219 220 static int __init eager_fpu_setup(char *s) 221 { 222 if (!strcmp(s, "on")) 223 eagerfpu = ENABLE; 224 else if (!strcmp(s, "off")) 225 eagerfpu = DISABLE; 226 else if (!strcmp(s, "auto")) 227 eagerfpu = AUTO; 228 return 1; 229 } 230 __setup("eagerfpu=", eager_fpu_setup); 231 232 /* 233 * Pick the FPU context switching strategy: 234 */ 235 static void __init fpu__init_system_ctx_switch(void) 236 { 237 static bool on_boot_cpu = 1; 238 239 WARN_ON_FPU(!on_boot_cpu); 240 on_boot_cpu = 0; 241 242 WARN_ON_FPU(current->thread.fpu.fpstate_active); 243 current_thread_info()->status = 0; 244 245 /* Auto enable eagerfpu for xsaveopt */ 246 if (cpu_has_xsaveopt && eagerfpu != DISABLE) 247 eagerfpu = ENABLE; 248 249 if (xfeatures_mask & XSTATE_EAGER) { 250 if (eagerfpu == DISABLE) { 251 pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n", 252 xfeatures_mask & XSTATE_EAGER); 253 xfeatures_mask &= ~XSTATE_EAGER; 254 } else { 255 eagerfpu = ENABLE; 256 } 257 } 258 259 if (eagerfpu == ENABLE) 260 setup_force_cpu_cap(X86_FEATURE_EAGER_FPU); 261 262 printk(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy"); 263 } 264 265 /* 266 * Called on the boot CPU once per system bootup, to set up the initial 267 * FPU state that is later cloned into all processes: 268 */ 269 void __init fpu__init_system(struct cpuinfo_x86 *c) 270 { 271 fpu__init_system_early_generic(c); 272 273 /* 274 * The FPU has to be operational for some of the 275 * later FPU init activities: 276 */ 277 fpu__init_cpu(); 278 279 /* 280 * But don't leave CR0::TS set yet, as some of the FPU setup 281 * methods depend on being able to execute FPU instructions 282 * that will fault on a set TS, such as the FXSAVE in 283 * fpu__init_system_mxcsr(). 284 */ 285 clts(); 286 287 fpu__init_system_generic(); 288 fpu__init_system_xstate_size_legacy(); 289 fpu__init_system_xstate(); 290 291 fpu__init_system_ctx_switch(); 292 } 293 294 /* 295 * Boot parameter to turn off FPU support and fall back to math-emu: 296 */ 297 static int __init no_387(char *s) 298 { 299 setup_clear_cpu_cap(X86_FEATURE_FPU); 300 return 1; 301 } 302 __setup("no387", no_387); 303 304 /* 305 * Disable all xstate CPU features: 306 */ 307 static int __init x86_noxsave_setup(char *s) 308 { 309 if (strlen(s)) 310 return 0; 311 312 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 313 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 314 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 315 setup_clear_cpu_cap(X86_FEATURE_AVX); 316 setup_clear_cpu_cap(X86_FEATURE_AVX2); 317 318 return 1; 319 } 320 __setup("noxsave", x86_noxsave_setup); 321 322 /* 323 * Disable the XSAVEOPT instruction specifically: 324 */ 325 static int __init x86_noxsaveopt_setup(char *s) 326 { 327 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 328 329 return 1; 330 } 331 __setup("noxsaveopt", x86_noxsaveopt_setup); 332 333 /* 334 * Disable the XSAVES instruction: 335 */ 336 static int __init x86_noxsaves_setup(char *s) 337 { 338 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 339 340 return 1; 341 } 342 __setup("noxsaves", x86_noxsaves_setup); 343 344 /* 345 * Disable FX save/restore and SSE support: 346 */ 347 static int __init x86_nofxsr_setup(char *s) 348 { 349 setup_clear_cpu_cap(X86_FEATURE_FXSR); 350 setup_clear_cpu_cap(X86_FEATURE_FXSR_OPT); 351 setup_clear_cpu_cap(X86_FEATURE_XMM); 352 353 return 1; 354 } 355 __setup("nofxsr", x86_nofxsr_setup); 356