1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Pentium III FXSR, SSE support 6 * General FPU state handling cleanups 7 * Gareth Hughes <gareth@valinux.com>, May 2000 8 */ 9 #include <asm/fpu/api.h> 10 #include <asm/fpu/regset.h> 11 #include <asm/fpu/sched.h> 12 #include <asm/fpu/signal.h> 13 #include <asm/fpu/types.h> 14 #include <asm/msr.h> 15 #include <asm/traps.h> 16 #include <asm/irq_regs.h> 17 18 #include <uapi/asm/kvm.h> 19 20 #include <linux/hardirq.h> 21 #include <linux/pkeys.h> 22 #include <linux/vmalloc.h> 23 24 #include "context.h" 25 #include "internal.h" 26 #include "legacy.h" 27 #include "xstate.h" 28 29 #define CREATE_TRACE_POINTS 30 #include <asm/trace/fpu.h> 31 32 #ifdef CONFIG_X86_64 33 DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic); 34 DEFINE_PER_CPU(u64, xfd_state); 35 #endif 36 37 /* The FPU state configuration data for kernel and user space */ 38 struct fpu_state_config fpu_kernel_cfg __ro_after_init; 39 struct fpu_state_config fpu_user_cfg __ro_after_init; 40 41 /* 42 * Represents the initial FPU state. It's mostly (but not completely) zeroes, 43 * depending on the FPU hardware format: 44 */ 45 struct fpstate init_fpstate __ro_after_init; 46 47 /* 48 * Track FPU initialization and kernel-mode usage. 'true' means the FPU is 49 * initialized and is not currently being used by the kernel: 50 */ 51 DEFINE_PER_CPU(bool, kernel_fpu_allowed); 52 53 /* 54 * Track which context is using the FPU on the CPU: 55 */ 56 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); 57 58 #ifdef CONFIG_X86_DEBUG_FPU 59 struct fpu *x86_task_fpu(struct task_struct *task) 60 { 61 if (WARN_ON_ONCE(task->flags & PF_KTHREAD)) 62 return NULL; 63 64 return (void *)task + sizeof(*task); 65 } 66 #endif 67 68 /* 69 * Can we use the FPU in kernel mode with the 70 * whole "kernel_fpu_begin/end()" sequence? 71 */ 72 bool irq_fpu_usable(void) 73 { 74 if (WARN_ON_ONCE(in_nmi())) 75 return false; 76 77 /* 78 * Return false in the following cases: 79 * 80 * - FPU is not yet initialized. This can happen only when the call is 81 * coming from CPU onlining, for example for microcode checksumming. 82 * - The kernel is already using the FPU, either because of explicit 83 * nesting (which should never be done), or because of implicit 84 * nesting when a hardirq interrupted a kernel-mode FPU section. 85 * 86 * The single boolean check below handles both cases: 87 */ 88 if (!this_cpu_read(kernel_fpu_allowed)) 89 return false; 90 91 /* 92 * When not in NMI or hard interrupt context, FPU can be used in: 93 * 94 * - Task context except from within fpregs_lock()'ed critical 95 * regions. 96 * 97 * - Soft interrupt processing context which cannot happen 98 * while in a fpregs_lock()'ed critical region. 99 */ 100 if (!in_hardirq()) 101 return true; 102 103 /* 104 * In hard interrupt context it's safe when soft interrupts 105 * are enabled, which means the interrupt did not hit in 106 * a fpregs_lock()'ed critical region. 107 */ 108 return !softirq_count(); 109 } 110 EXPORT_SYMBOL(irq_fpu_usable); 111 112 /* 113 * Track AVX512 state use because it is known to slow the max clock 114 * speed of the core. 115 */ 116 static void update_avx_timestamp(struct fpu *fpu) 117 { 118 119 #define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM) 120 121 if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK) 122 fpu->avx512_timestamp = jiffies; 123 } 124 125 /* 126 * Save the FPU register state in fpu->fpstate->regs. The register state is 127 * preserved. 128 * 129 * Must be called with fpregs_lock() held. 130 * 131 * The legacy FNSAVE instruction clears all FPU state unconditionally, so 132 * register state has to be reloaded. That might be a pointless exercise 133 * when the FPU is going to be used by another task right after that. But 134 * this only affects 20+ years old 32bit systems and avoids conditionals all 135 * over the place. 136 * 137 * FXSAVE and all XSAVE variants preserve the FPU register state. 138 */ 139 void save_fpregs_to_fpstate(struct fpu *fpu) 140 { 141 if (likely(use_xsave())) { 142 os_xsave(fpu->fpstate); 143 update_avx_timestamp(fpu); 144 return; 145 } 146 147 if (likely(use_fxsr())) { 148 fxsave(&fpu->fpstate->regs.fxsave); 149 return; 150 } 151 152 /* 153 * Legacy FPU register saving, FNSAVE always clears FPU registers, 154 * so we have to reload them from the memory state. 155 */ 156 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->fpstate->regs.fsave)); 157 frstor(&fpu->fpstate->regs.fsave); 158 } 159 160 void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask) 161 { 162 /* 163 * AMD K7/K8 and later CPUs up to Zen don't save/restore 164 * FDP/FIP/FOP unless an exception is pending. Clear the x87 state 165 * here by setting it to fixed values. "m" is a random variable 166 * that should be in L1. 167 */ 168 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) { 169 asm volatile( 170 "fnclex\n\t" 171 "emms\n\t" 172 "fildl %[addr]" /* set F?P to defined value */ 173 : : [addr] "m" (*fpstate)); 174 } 175 176 if (use_xsave()) { 177 /* 178 * Dynamically enabled features are enabled in XCR0, but 179 * usage requires also that the corresponding bits in XFD 180 * are cleared. If the bits are set then using a related 181 * instruction will raise #NM. This allows to do the 182 * allocation of the larger FPU buffer lazy from #NM or if 183 * the task has no permission to kill it which would happen 184 * via #UD if the feature is disabled in XCR0. 185 * 186 * XFD state is following the same life time rules as 187 * XSTATE and to restore state correctly XFD has to be 188 * updated before XRSTORS otherwise the component would 189 * stay in or go into init state even if the bits are set 190 * in fpstate::regs::xsave::xfeatures. 191 */ 192 xfd_update_state(fpstate); 193 194 /* 195 * Restoring state always needs to modify all features 196 * which are in @mask even if the current task cannot use 197 * extended features. 198 * 199 * So fpstate->xfeatures cannot be used here, because then 200 * a feature for which the task has no permission but was 201 * used by the previous task would not go into init state. 202 */ 203 mask = fpu_kernel_cfg.max_features & mask; 204 205 os_xrstor(fpstate, mask); 206 } else { 207 if (use_fxsr()) 208 fxrstor(&fpstate->regs.fxsave); 209 else 210 frstor(&fpstate->regs.fsave); 211 } 212 } 213 214 void fpu_reset_from_exception_fixup(void) 215 { 216 restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_FPSTATE); 217 } 218 219 #if IS_ENABLED(CONFIG_KVM) 220 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd); 221 222 static void fpu_lock_guest_permissions(void) 223 { 224 struct fpu_state_perm *fpuperm; 225 u64 perm; 226 227 if (!IS_ENABLED(CONFIG_X86_64)) 228 return; 229 230 spin_lock_irq(¤t->sighand->siglock); 231 fpuperm = &x86_task_fpu(current->group_leader)->guest_perm; 232 perm = fpuperm->__state_perm; 233 234 /* First fpstate allocation locks down permissions. */ 235 WRITE_ONCE(fpuperm->__state_perm, perm | FPU_GUEST_PERM_LOCKED); 236 237 spin_unlock_irq(¤t->sighand->siglock); 238 } 239 240 bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu) 241 { 242 struct fpstate *fpstate; 243 unsigned int size; 244 245 size = fpu_kernel_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64); 246 fpstate = vzalloc(size); 247 if (!fpstate) 248 return false; 249 250 /* Leave xfd to 0 (the reset value defined by spec) */ 251 __fpstate_reset(fpstate, 0); 252 fpstate_init_user(fpstate); 253 fpstate->is_valloc = true; 254 fpstate->is_guest = true; 255 256 gfpu->fpstate = fpstate; 257 gfpu->xfeatures = fpu_kernel_cfg.default_features; 258 259 /* 260 * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state 261 * to userspace, even when XSAVE is unsupported, so that restoring FPU 262 * state on a different CPU that does support XSAVE can cleanly load 263 * the incoming state using its natural XSAVE. In other words, KVM's 264 * uABI size may be larger than this host's default size. Conversely, 265 * the default size should never be larger than KVM's base uABI size; 266 * all features that can expand the uABI size must be opt-in. 267 */ 268 gfpu->uabi_size = sizeof(struct kvm_xsave); 269 if (WARN_ON_ONCE(fpu_user_cfg.default_size > gfpu->uabi_size)) 270 gfpu->uabi_size = fpu_user_cfg.default_size; 271 272 fpu_lock_guest_permissions(); 273 274 return true; 275 } 276 EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate); 277 278 void fpu_free_guest_fpstate(struct fpu_guest *gfpu) 279 { 280 struct fpstate *fpstate = gfpu->fpstate; 281 282 if (!fpstate) 283 return; 284 285 if (WARN_ON_ONCE(!fpstate->is_valloc || !fpstate->is_guest || fpstate->in_use)) 286 return; 287 288 gfpu->fpstate = NULL; 289 vfree(fpstate); 290 } 291 EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate); 292 293 /* 294 * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable 295 * @guest_fpu: Pointer to the guest FPU container 296 * @xfeatures: Features requested by guest CPUID 297 * 298 * Enable all dynamic xfeatures according to guest perm and requested CPUID. 299 * 300 * Return: 0 on success, error code otherwise 301 */ 302 int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures) 303 { 304 lockdep_assert_preemption_enabled(); 305 306 /* Nothing to do if all requested features are already enabled. */ 307 xfeatures &= ~guest_fpu->xfeatures; 308 if (!xfeatures) 309 return 0; 310 311 return __xfd_enable_feature(xfeatures, guest_fpu); 312 } 313 EXPORT_SYMBOL_GPL(fpu_enable_guest_xfd_features); 314 315 #ifdef CONFIG_X86_64 316 void fpu_update_guest_xfd(struct fpu_guest *guest_fpu, u64 xfd) 317 { 318 fpregs_lock(); 319 guest_fpu->fpstate->xfd = xfd; 320 if (guest_fpu->fpstate->in_use) 321 xfd_update_state(guest_fpu->fpstate); 322 fpregs_unlock(); 323 } 324 EXPORT_SYMBOL_GPL(fpu_update_guest_xfd); 325 326 /** 327 * fpu_sync_guest_vmexit_xfd_state - Synchronize XFD MSR and software state 328 * 329 * Must be invoked from KVM after a VMEXIT before enabling interrupts when 330 * XFD write emulation is disabled. This is required because the guest can 331 * freely modify XFD and the state at VMEXIT is not guaranteed to be the 332 * same as the state on VMENTER. So software state has to be updated before 333 * any operation which depends on it can take place. 334 * 335 * Note: It can be invoked unconditionally even when write emulation is 336 * enabled for the price of a then pointless MSR read. 337 */ 338 void fpu_sync_guest_vmexit_xfd_state(void) 339 { 340 struct fpstate *fpstate = x86_task_fpu(current)->fpstate; 341 342 lockdep_assert_irqs_disabled(); 343 if (fpu_state_size_dynamic()) { 344 rdmsrq(MSR_IA32_XFD, fpstate->xfd); 345 __this_cpu_write(xfd_state, fpstate->xfd); 346 } 347 } 348 EXPORT_SYMBOL_GPL(fpu_sync_guest_vmexit_xfd_state); 349 #endif /* CONFIG_X86_64 */ 350 351 int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest) 352 { 353 struct fpstate *guest_fps = guest_fpu->fpstate; 354 struct fpu *fpu = x86_task_fpu(current); 355 struct fpstate *cur_fps = fpu->fpstate; 356 357 fpregs_lock(); 358 if (!cur_fps->is_confidential && !test_thread_flag(TIF_NEED_FPU_LOAD)) 359 save_fpregs_to_fpstate(fpu); 360 361 /* Swap fpstate */ 362 if (enter_guest) { 363 fpu->__task_fpstate = cur_fps; 364 fpu->fpstate = guest_fps; 365 guest_fps->in_use = true; 366 } else { 367 guest_fps->in_use = false; 368 fpu->fpstate = fpu->__task_fpstate; 369 fpu->__task_fpstate = NULL; 370 } 371 372 cur_fps = fpu->fpstate; 373 374 if (!cur_fps->is_confidential) { 375 /* Includes XFD update */ 376 restore_fpregs_from_fpstate(cur_fps, XFEATURE_MASK_FPSTATE); 377 } else { 378 /* 379 * XSTATE is restored by firmware from encrypted 380 * memory. Make sure XFD state is correct while 381 * running with guest fpstate 382 */ 383 xfd_update_state(cur_fps); 384 } 385 386 fpregs_mark_activate(); 387 fpregs_unlock(); 388 return 0; 389 } 390 EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate); 391 392 void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf, 393 unsigned int size, u64 xfeatures, u32 pkru) 394 { 395 struct fpstate *kstate = gfpu->fpstate; 396 union fpregs_state *ustate = buf; 397 struct membuf mb = { .p = buf, .left = size }; 398 399 if (cpu_feature_enabled(X86_FEATURE_XSAVE)) { 400 __copy_xstate_to_uabi_buf(mb, kstate, xfeatures, pkru, 401 XSTATE_COPY_XSAVE); 402 } else { 403 memcpy(&ustate->fxsave, &kstate->regs.fxsave, 404 sizeof(ustate->fxsave)); 405 /* Make it restorable on a XSAVE enabled host */ 406 ustate->xsave.header.xfeatures = XFEATURE_MASK_FPSSE; 407 } 408 } 409 EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi); 410 411 int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf, 412 u64 xcr0, u32 *vpkru) 413 { 414 struct fpstate *kstate = gfpu->fpstate; 415 const union fpregs_state *ustate = buf; 416 417 if (!cpu_feature_enabled(X86_FEATURE_XSAVE)) { 418 if (ustate->xsave.header.xfeatures & ~XFEATURE_MASK_FPSSE) 419 return -EINVAL; 420 if (ustate->fxsave.mxcsr & ~mxcsr_feature_mask) 421 return -EINVAL; 422 memcpy(&kstate->regs.fxsave, &ustate->fxsave, sizeof(ustate->fxsave)); 423 return 0; 424 } 425 426 if (ustate->xsave.header.xfeatures & ~xcr0) 427 return -EINVAL; 428 429 /* 430 * Nullify @vpkru to preserve its current value if PKRU's bit isn't set 431 * in the header. KVM's odd ABI is to leave PKRU untouched in this 432 * case (all other components are eventually re-initialized). 433 */ 434 if (!(ustate->xsave.header.xfeatures & XFEATURE_MASK_PKRU)) 435 vpkru = NULL; 436 437 return copy_uabi_from_kernel_to_xstate(kstate, ustate, vpkru); 438 } 439 EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate); 440 #endif /* CONFIG_KVM */ 441 442 void kernel_fpu_begin_mask(unsigned int kfpu_mask) 443 { 444 if (!irqs_disabled()) 445 fpregs_lock(); 446 447 WARN_ON_FPU(!irq_fpu_usable()); 448 449 /* Toggle kernel_fpu_allowed to false: */ 450 WARN_ON_FPU(!this_cpu_read(kernel_fpu_allowed)); 451 this_cpu_write(kernel_fpu_allowed, false); 452 453 if (!(current->flags & (PF_KTHREAD | PF_USER_WORKER)) && 454 !test_thread_flag(TIF_NEED_FPU_LOAD)) { 455 set_thread_flag(TIF_NEED_FPU_LOAD); 456 save_fpregs_to_fpstate(x86_task_fpu(current)); 457 } 458 __cpu_invalidate_fpregs_state(); 459 460 /* Put sane initial values into the control registers. */ 461 if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM)) 462 ldmxcsr(MXCSR_DEFAULT); 463 464 if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU)) 465 asm volatile ("fninit"); 466 } 467 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask); 468 469 void kernel_fpu_end(void) 470 { 471 /* Toggle kernel_fpu_allowed back to true: */ 472 WARN_ON_FPU(this_cpu_read(kernel_fpu_allowed)); 473 this_cpu_write(kernel_fpu_allowed, true); 474 475 if (!irqs_disabled()) 476 fpregs_unlock(); 477 } 478 EXPORT_SYMBOL_GPL(kernel_fpu_end); 479 480 /* 481 * Sync the FPU register state to current's memory register state when the 482 * current task owns the FPU. The hardware register state is preserved. 483 */ 484 void fpu_sync_fpstate(struct fpu *fpu) 485 { 486 WARN_ON_FPU(fpu != x86_task_fpu(current)); 487 488 fpregs_lock(); 489 trace_x86_fpu_before_save(fpu); 490 491 if (!test_thread_flag(TIF_NEED_FPU_LOAD)) 492 save_fpregs_to_fpstate(fpu); 493 494 trace_x86_fpu_after_save(fpu); 495 fpregs_unlock(); 496 } 497 498 static inline unsigned int init_fpstate_copy_size(void) 499 { 500 if (!use_xsave()) 501 return fpu_kernel_cfg.default_size; 502 503 /* XSAVE(S) just needs the legacy and the xstate header part */ 504 return sizeof(init_fpstate.regs.xsave); 505 } 506 507 static inline void fpstate_init_fxstate(struct fpstate *fpstate) 508 { 509 fpstate->regs.fxsave.cwd = 0x37f; 510 fpstate->regs.fxsave.mxcsr = MXCSR_DEFAULT; 511 } 512 513 /* 514 * Legacy x87 fpstate state init: 515 */ 516 static inline void fpstate_init_fstate(struct fpstate *fpstate) 517 { 518 fpstate->regs.fsave.cwd = 0xffff037fu; 519 fpstate->regs.fsave.swd = 0xffff0000u; 520 fpstate->regs.fsave.twd = 0xffffffffu; 521 fpstate->regs.fsave.fos = 0xffff0000u; 522 } 523 524 /* 525 * Used in two places: 526 * 1) Early boot to setup init_fpstate for non XSAVE systems 527 * 2) fpu_alloc_guest_fpstate() which is invoked from KVM 528 */ 529 void fpstate_init_user(struct fpstate *fpstate) 530 { 531 if (!cpu_feature_enabled(X86_FEATURE_FPU)) { 532 fpstate_init_soft(&fpstate->regs.soft); 533 return; 534 } 535 536 xstate_init_xcomp_bv(&fpstate->regs.xsave, fpstate->xfeatures); 537 538 if (cpu_feature_enabled(X86_FEATURE_FXSR)) 539 fpstate_init_fxstate(fpstate); 540 else 541 fpstate_init_fstate(fpstate); 542 } 543 544 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd) 545 { 546 /* Initialize sizes and feature masks */ 547 fpstate->size = fpu_kernel_cfg.default_size; 548 fpstate->user_size = fpu_user_cfg.default_size; 549 fpstate->xfeatures = fpu_kernel_cfg.default_features; 550 fpstate->user_xfeatures = fpu_user_cfg.default_features; 551 fpstate->xfd = xfd; 552 } 553 554 void fpstate_reset(struct fpu *fpu) 555 { 556 /* Set the fpstate pointer to the default fpstate */ 557 fpu->fpstate = &fpu->__fpstate; 558 __fpstate_reset(fpu->fpstate, init_fpstate.xfd); 559 560 /* Initialize the permission related info in fpu */ 561 fpu->perm.__state_perm = fpu_kernel_cfg.default_features; 562 fpu->perm.__state_size = fpu_kernel_cfg.default_size; 563 fpu->perm.__user_state_size = fpu_user_cfg.default_size; 564 /* Same defaults for guests */ 565 fpu->guest_perm = fpu->perm; 566 } 567 568 static inline void fpu_inherit_perms(struct fpu *dst_fpu) 569 { 570 if (fpu_state_size_dynamic()) { 571 struct fpu *src_fpu = x86_task_fpu(current->group_leader); 572 573 spin_lock_irq(¤t->sighand->siglock); 574 /* Fork also inherits the permissions of the parent */ 575 dst_fpu->perm = src_fpu->perm; 576 dst_fpu->guest_perm = src_fpu->guest_perm; 577 spin_unlock_irq(¤t->sighand->siglock); 578 } 579 } 580 581 /* A passed ssp of zero will not cause any update */ 582 static int update_fpu_shstk(struct task_struct *dst, unsigned long ssp) 583 { 584 #ifdef CONFIG_X86_USER_SHADOW_STACK 585 struct cet_user_state *xstate; 586 587 /* If ssp update is not needed. */ 588 if (!ssp) 589 return 0; 590 591 xstate = get_xsave_addr(&x86_task_fpu(dst)->fpstate->regs.xsave, 592 XFEATURE_CET_USER); 593 594 /* 595 * If there is a non-zero ssp, then 'dst' must be configured with a shadow 596 * stack and the fpu state should be up to date since it was just copied 597 * from the parent in fpu_clone(). So there must be a valid non-init CET 598 * state location in the buffer. 599 */ 600 if (WARN_ON_ONCE(!xstate)) 601 return 1; 602 603 xstate->user_ssp = (u64)ssp; 604 #endif 605 return 0; 606 } 607 608 /* Clone current's FPU state on fork */ 609 int fpu_clone(struct task_struct *dst, unsigned long clone_flags, bool minimal, 610 unsigned long ssp) 611 { 612 /* 613 * We allocate the new FPU structure right after the end of the task struct. 614 * task allocation size already took this into account. 615 * 616 * This is safe because task_struct size is a multiple of cacheline size, 617 * thus x86_task_fpu() will always be cacheline aligned as well. 618 */ 619 struct fpu *dst_fpu = (void *)dst + sizeof(*dst); 620 621 BUILD_BUG_ON(sizeof(*dst) % SMP_CACHE_BYTES != 0); 622 623 /* The new task's FPU state cannot be valid in the hardware. */ 624 dst_fpu->last_cpu = -1; 625 626 fpstate_reset(dst_fpu); 627 628 if (!cpu_feature_enabled(X86_FEATURE_FPU)) 629 return 0; 630 631 /* 632 * Enforce reload for user space tasks and prevent kernel threads 633 * from trying to save the FPU registers on context switch. 634 */ 635 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD); 636 637 /* 638 * No FPU state inheritance for kernel threads and IO 639 * worker threads. 640 */ 641 if (minimal) { 642 /* Clear out the minimal state */ 643 memcpy(&dst_fpu->fpstate->regs, &init_fpstate.regs, 644 init_fpstate_copy_size()); 645 return 0; 646 } 647 648 /* 649 * If a new feature is added, ensure all dynamic features are 650 * caller-saved from here! 651 */ 652 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA); 653 654 /* 655 * Save the default portion of the current FPU state into the 656 * clone. Assume all dynamic features to be defined as caller- 657 * saved, which enables skipping both the expansion of fpstate 658 * and the copying of any dynamic state. 659 * 660 * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because 661 * copying is not valid when current uses non-default states. 662 */ 663 fpregs_lock(); 664 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 665 fpregs_restore_userregs(); 666 save_fpregs_to_fpstate(dst_fpu); 667 fpregs_unlock(); 668 if (!(clone_flags & CLONE_THREAD)) 669 fpu_inherit_perms(dst_fpu); 670 671 /* 672 * Children never inherit PASID state. 673 * Force it to have its init value: 674 */ 675 if (use_xsave()) 676 dst_fpu->fpstate->regs.xsave.header.xfeatures &= ~XFEATURE_MASK_PASID; 677 678 /* 679 * Update shadow stack pointer, in case it changed during clone. 680 */ 681 if (update_fpu_shstk(dst, ssp)) 682 return 1; 683 684 trace_x86_fpu_copy_dst(dst_fpu); 685 686 return 0; 687 } 688 689 /* 690 * While struct fpu is no longer part of struct thread_struct, it is still 691 * allocated after struct task_struct in the "task_struct" kmem cache. But 692 * since FPU is expected to be part of struct thread_struct, we have to 693 * adjust for it here. 694 */ 695 void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size) 696 { 697 /* The allocation follows struct task_struct. */ 698 *offset = sizeof(struct task_struct) - offsetof(struct task_struct, thread); 699 *offset += offsetof(struct fpu, __fpstate.regs); 700 *size = fpu_kernel_cfg.default_size; 701 } 702 703 /* 704 * Drops current FPU state: deactivates the fpregs and 705 * the fpstate. NOTE: it still leaves previous contents 706 * in the fpregs in the eager-FPU case. 707 * 708 * This function can be used in cases where we know that 709 * a state-restore is coming: either an explicit one, 710 * or a reschedule. 711 */ 712 void fpu__drop(struct task_struct *tsk) 713 { 714 struct fpu *fpu; 715 716 if (test_tsk_thread_flag(tsk, TIF_NEED_FPU_LOAD)) 717 return; 718 719 fpu = x86_task_fpu(tsk); 720 721 preempt_disable(); 722 723 if (fpu == x86_task_fpu(current)) { 724 /* Ignore delayed exceptions from user space */ 725 asm volatile("1: fwait\n" 726 "2:\n" 727 _ASM_EXTABLE(1b, 2b)); 728 fpregs_deactivate(fpu); 729 } 730 731 trace_x86_fpu_dropped(fpu); 732 733 preempt_enable(); 734 } 735 736 /* 737 * Clear FPU registers by setting them up from the init fpstate. 738 * Caller must do fpregs_[un]lock() around it. 739 */ 740 static inline void restore_fpregs_from_init_fpstate(u64 features_mask) 741 { 742 if (use_xsave()) 743 os_xrstor(&init_fpstate, features_mask); 744 else if (use_fxsr()) 745 fxrstor(&init_fpstate.regs.fxsave); 746 else 747 frstor(&init_fpstate.regs.fsave); 748 749 pkru_write_default(); 750 } 751 752 /* 753 * Reset current->fpu memory state to the init values. 754 */ 755 static void fpu_reset_fpstate_regs(void) 756 { 757 struct fpu *fpu = x86_task_fpu(current); 758 759 fpregs_lock(); 760 __fpu_invalidate_fpregs_state(fpu); 761 /* 762 * This does not change the actual hardware registers. It just 763 * resets the memory image and sets TIF_NEED_FPU_LOAD so a 764 * subsequent return to usermode will reload the registers from the 765 * task's memory image. 766 * 767 * Do not use fpstate_init() here. Just copy init_fpstate which has 768 * the correct content already except for PKRU. 769 * 770 * PKRU handling does not rely on the xstate when restoring for 771 * user space as PKRU is eagerly written in switch_to() and 772 * flush_thread(). 773 */ 774 memcpy(&fpu->fpstate->regs, &init_fpstate.regs, init_fpstate_copy_size()); 775 set_thread_flag(TIF_NEED_FPU_LOAD); 776 fpregs_unlock(); 777 } 778 779 /* 780 * Reset current's user FPU states to the init states. current's 781 * supervisor states, if any, are not modified by this function. The 782 * caller guarantees that the XSTATE header in memory is intact. 783 */ 784 void fpu__clear_user_states(struct fpu *fpu) 785 { 786 WARN_ON_FPU(fpu != x86_task_fpu(current)); 787 788 fpregs_lock(); 789 if (!cpu_feature_enabled(X86_FEATURE_FPU)) { 790 fpu_reset_fpstate_regs(); 791 fpregs_unlock(); 792 return; 793 } 794 795 /* 796 * Ensure that current's supervisor states are loaded into their 797 * corresponding registers. 798 */ 799 if (xfeatures_mask_supervisor() && 800 !fpregs_state_valid(fpu, smp_processor_id())) 801 os_xrstor_supervisor(fpu->fpstate); 802 803 /* Reset user states in registers. */ 804 restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE); 805 806 /* 807 * Now all FPU registers have their desired values. Inform the FPU 808 * state machine that current's FPU registers are in the hardware 809 * registers. The memory image does not need to be updated because 810 * any operation relying on it has to save the registers first when 811 * current's FPU is marked active. 812 */ 813 fpregs_mark_activate(); 814 fpregs_unlock(); 815 } 816 817 void fpu_flush_thread(void) 818 { 819 fpstate_reset(x86_task_fpu(current)); 820 fpu_reset_fpstate_regs(); 821 } 822 /* 823 * Load FPU context before returning to userspace. 824 */ 825 void switch_fpu_return(void) 826 { 827 if (!static_cpu_has(X86_FEATURE_FPU)) 828 return; 829 830 fpregs_restore_userregs(); 831 } 832 EXPORT_SYMBOL_GPL(switch_fpu_return); 833 834 void fpregs_lock_and_load(void) 835 { 836 /* 837 * fpregs_lock() only disables preemption (mostly). So modifying state 838 * in an interrupt could screw up some in progress fpregs operation. 839 * Warn about it. 840 */ 841 WARN_ON_ONCE(!irq_fpu_usable()); 842 WARN_ON_ONCE(current->flags & PF_KTHREAD); 843 844 fpregs_lock(); 845 846 fpregs_assert_state_consistent(); 847 848 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 849 fpregs_restore_userregs(); 850 } 851 852 #ifdef CONFIG_X86_DEBUG_FPU 853 /* 854 * If current FPU state according to its tracking (loaded FPU context on this 855 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is 856 * loaded on return to userland. 857 */ 858 void fpregs_assert_state_consistent(void) 859 { 860 struct fpu *fpu = x86_task_fpu(current); 861 862 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 863 return; 864 865 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id())); 866 } 867 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent); 868 #endif 869 870 void fpregs_mark_activate(void) 871 { 872 struct fpu *fpu = x86_task_fpu(current); 873 874 fpregs_activate(fpu); 875 fpu->last_cpu = smp_processor_id(); 876 clear_thread_flag(TIF_NEED_FPU_LOAD); 877 } 878 879 /* 880 * x87 math exception handling: 881 */ 882 883 int fpu__exception_code(struct fpu *fpu, int trap_nr) 884 { 885 int err; 886 887 if (trap_nr == X86_TRAP_MF) { 888 unsigned short cwd, swd; 889 /* 890 * (~cwd & swd) will mask out exceptions that are not set to unmasked 891 * status. 0x3f is the exception bits in these regs, 0x200 is the 892 * C1 reg you need in case of a stack fault, 0x040 is the stack 893 * fault bit. We should only be taking one exception at a time, 894 * so if this combination doesn't produce any single exception, 895 * then we have a bad program that isn't synchronizing its FPU usage 896 * and it will suffer the consequences since we won't be able to 897 * fully reproduce the context of the exception. 898 */ 899 if (boot_cpu_has(X86_FEATURE_FXSR)) { 900 cwd = fpu->fpstate->regs.fxsave.cwd; 901 swd = fpu->fpstate->regs.fxsave.swd; 902 } else { 903 cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd; 904 swd = (unsigned short)fpu->fpstate->regs.fsave.swd; 905 } 906 907 err = swd & ~cwd; 908 } else { 909 /* 910 * The SIMD FPU exceptions are handled a little differently, as there 911 * is only a single status/control register. Thus, to determine which 912 * unmasked exception was caught we must mask the exception mask bits 913 * at 0x1f80, and then use these to mask the exception bits at 0x3f. 914 */ 915 unsigned short mxcsr = MXCSR_DEFAULT; 916 917 if (boot_cpu_has(X86_FEATURE_XMM)) 918 mxcsr = fpu->fpstate->regs.fxsave.mxcsr; 919 920 err = ~(mxcsr >> 7) & mxcsr; 921 } 922 923 if (err & 0x001) { /* Invalid op */ 924 /* 925 * swd & 0x240 == 0x040: Stack Underflow 926 * swd & 0x240 == 0x240: Stack Overflow 927 * User must clear the SF bit (0x40) if set 928 */ 929 return FPE_FLTINV; 930 } else if (err & 0x004) { /* Divide by Zero */ 931 return FPE_FLTDIV; 932 } else if (err & 0x008) { /* Overflow */ 933 return FPE_FLTOVF; 934 } else if (err & 0x012) { /* Denormal, Underflow */ 935 return FPE_FLTUND; 936 } else if (err & 0x020) { /* Precision */ 937 return FPE_FLTRES; 938 } 939 940 /* 941 * If we're using IRQ 13, or supposedly even some trap 942 * X86_TRAP_MF implementations, it's possible 943 * we get a spurious trap, which is not an error. 944 */ 945 return 0; 946 } 947 948 /* 949 * Initialize register state that may prevent from entering low-power idle. 950 * This function will be invoked from the cpuidle driver only when needed. 951 */ 952 noinstr void fpu_idle_fpregs(void) 953 { 954 /* Note: AMX_TILE being enabled implies XGETBV1 support */ 955 if (cpu_feature_enabled(X86_FEATURE_AMX_TILE) && 956 (xfeatures_in_use() & XFEATURE_MASK_XTILE)) { 957 tile_release(); 958 __this_cpu_write(fpu_fpregs_owner_ctx, NULL); 959 } 960 } 961