1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/sched.h> 3 #include <linux/sched/clock.h> 4 5 #include <asm/cpu.h> 6 #include <asm/cpufeature.h> 7 #include <asm/cpuid/api.h> 8 #include <asm/msr.h> 9 10 #include "cpu.h" 11 12 #define MSR_ZHAOXIN_FCR57 0x00001257 13 14 #define ACE_PRESENT (1 << 6) 15 #define ACE_ENABLED (1 << 7) 16 #define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */ 17 18 #define RNG_PRESENT (1 << 2) 19 #define RNG_ENABLED (1 << 3) 20 #define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */ 21 22 static void init_zhaoxin_cap(struct cpuinfo_x86 *c) 23 { 24 u64 msr; 25 26 /* Test for Extended Feature Flags presence */ 27 if (cpuid_eax(0xC0000000) >= 0xC0000001) { 28 u32 tmp = cpuid_edx(0xC0000001); 29 30 /* Enable ACE unit, if present and disabled */ 31 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { 32 rdmsrq(MSR_ZHAOXIN_FCR57, msr); 33 /* Enable ACE unit */ 34 wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR); 35 pr_info("CPU: Enabled ACE h/w crypto\n"); 36 } 37 38 /* Enable RNG unit, if present and disabled */ 39 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { 40 rdmsrq(MSR_ZHAOXIN_FCR57, msr); 41 /* Enable RNG unit */ 42 wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE); 43 pr_info("CPU: Enabled h/w RNG\n"); 44 } 45 46 /* 47 * Store Extended Feature Flags as word 5 of the CPU 48 * capability bit array 49 */ 50 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); 51 } 52 53 if (c->x86 >= 0x6) 54 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 55 } 56 57 static void early_init_zhaoxin(struct cpuinfo_x86 *c) 58 { 59 if (c->x86 >= 0x6) 60 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 61 62 if (c->x86_power & (1 << 8)) { 63 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 64 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 65 } 66 } 67 68 static void init_zhaoxin(struct cpuinfo_x86 *c) 69 { 70 early_init_zhaoxin(c); 71 init_intel_cacheinfo(c); 72 73 if (c->cpuid_level > 9) { 74 unsigned int eax = cpuid_eax(10); 75 76 /* 77 * Check for version and the number of counters 78 * Version(eax[7:0]) can't be 0; 79 * Counters(eax[15:8]) should be greater than 1; 80 */ 81 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) 82 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 83 } 84 85 if (c->x86 >= 0x6) 86 init_zhaoxin_cap(c); 87 #ifdef CONFIG_X86_64 88 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 89 #endif 90 91 init_ia32_feat_ctl(c); 92 } 93 94 #ifdef CONFIG_X86_32 95 static unsigned int 96 zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size) 97 { 98 return size; 99 } 100 #endif 101 102 static const struct cpu_dev zhaoxin_cpu_dev = { 103 .c_vendor = "zhaoxin", 104 .c_ident = { " Shanghai " }, 105 .c_early_init = early_init_zhaoxin, 106 .c_init = init_zhaoxin, 107 #ifdef CONFIG_X86_32 108 .legacy_cache_size = zhaoxin_size_cache, 109 #endif 110 .c_x86_vendor = X86_VENDOR_ZHAOXIN, 111 }; 112 113 cpu_dev_register(zhaoxin_cpu_dev); 114