1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/cpu.h> 3 4 #include <asm/apic.h> 5 #include <asm/memtype.h> 6 #include <asm/processor.h> 7 8 #include "cpu.h" 9 10 enum topo_types { 11 INVALID_TYPE = 0, 12 SMT_TYPE = 1, 13 CORE_TYPE = 2, 14 MAX_TYPE_0B = 3, 15 MODULE_TYPE = 3, 16 TILE_TYPE = 4, 17 DIE_TYPE = 5, 18 DIEGRP_TYPE = 6, 19 MAX_TYPE_1F = 7, 20 }; 21 22 /* 23 * Use a lookup table for the case that there are future types > 6 which 24 * describe an intermediate domain level which does not exist today. 25 */ 26 static const unsigned int topo_domain_map_0b_1f[MAX_TYPE_1F] = { 27 [SMT_TYPE] = TOPO_SMT_DOMAIN, 28 [CORE_TYPE] = TOPO_CORE_DOMAIN, 29 [MODULE_TYPE] = TOPO_MODULE_DOMAIN, 30 [TILE_TYPE] = TOPO_TILE_DOMAIN, 31 [DIE_TYPE] = TOPO_DIE_DOMAIN, 32 [DIEGRP_TYPE] = TOPO_DIEGRP_DOMAIN, 33 }; 34 35 static inline bool topo_subleaf(struct topo_scan *tscan, u32 leaf, u32 subleaf, 36 unsigned int *last_dom) 37 { 38 unsigned int dom, maxtype; 39 const unsigned int *map; 40 struct { 41 // eax 42 u32 x2apic_shift : 5, // Number of bits to shift APIC ID right 43 // for the topology ID at the next level 44 : 27; // Reserved 45 // ebx 46 u32 num_processors : 16, // Number of processors at current level 47 : 16; // Reserved 48 // ecx 49 u32 level : 8, // Current topology level. Same as sub leaf number 50 type : 8, // Level type. If 0, invalid 51 : 16; // Reserved 52 // edx 53 u32 x2apic_id : 32; // X2APIC ID of the current logical processor 54 } sl; 55 56 switch (leaf) { 57 case 0x0b: maxtype = MAX_TYPE_0B; map = topo_domain_map_0b_1f; break; 58 case 0x1f: maxtype = MAX_TYPE_1F; map = topo_domain_map_0b_1f; break; 59 default: return false; 60 } 61 62 cpuid_subleaf(leaf, subleaf, &sl); 63 64 if (!sl.num_processors || sl.type == INVALID_TYPE) 65 return false; 66 67 if (sl.type >= maxtype) { 68 pr_err_once("Topology: leaf 0x%x:%d Unknown domain type %u\n", 69 leaf, subleaf, sl.type); 70 /* 71 * It really would have been too obvious to make the domain 72 * type space sparse and leave a few reserved types between 73 * the points which might change instead of following the 74 * usual "this can be fixed in software" principle. 75 */ 76 dom = *last_dom + 1; 77 } else { 78 dom = map[sl.type]; 79 *last_dom = dom; 80 } 81 82 if (!dom) { 83 tscan->c->topo.initial_apicid = sl.x2apic_id; 84 } else if (tscan->c->topo.initial_apicid != sl.x2apic_id) { 85 pr_warn_once(FW_BUG "CPUID leaf 0x%x subleaf %d APIC ID mismatch %x != %x\n", 86 leaf, subleaf, tscan->c->topo.initial_apicid, sl.x2apic_id); 87 } 88 89 topology_set_dom(tscan, dom, sl.x2apic_shift, sl.num_processors); 90 return true; 91 } 92 93 static bool parse_topology_leaf(struct topo_scan *tscan, u32 leaf) 94 { 95 unsigned int last_dom; 96 u32 subleaf; 97 98 /* Read all available subleafs and populate the levels */ 99 for (subleaf = 0, last_dom = 0; topo_subleaf(tscan, leaf, subleaf, &last_dom); subleaf++); 100 101 /* If subleaf 0 failed to parse, give up */ 102 if (!subleaf) 103 return false; 104 105 /* 106 * There are machines in the wild which have shift 0 in the subleaf 107 * 0, but advertise 2 logical processors at that level. They are 108 * truly SMT. 109 */ 110 if (!tscan->dom_shifts[TOPO_SMT_DOMAIN] && tscan->dom_ncpus[TOPO_SMT_DOMAIN] > 1) { 111 unsigned int sft = get_count_order(tscan->dom_ncpus[TOPO_SMT_DOMAIN]); 112 113 pr_warn_once(FW_BUG "CPUID leaf 0x%x subleaf 0 has shift level 0 but %u CPUs. Fixing it up.\n", 114 leaf, tscan->dom_ncpus[TOPO_SMT_DOMAIN]); 115 topology_update_dom(tscan, TOPO_SMT_DOMAIN, sft, tscan->dom_ncpus[TOPO_SMT_DOMAIN]); 116 } 117 118 set_cpu_cap(tscan->c, X86_FEATURE_XTOPOLOGY); 119 return true; 120 } 121 122 bool cpu_parse_topology_ext(struct topo_scan *tscan) 123 { 124 /* Intel: Try leaf 0x1F first. */ 125 if (tscan->c->cpuid_level >= 0x1f && parse_topology_leaf(tscan, 0x1f)) 126 return true; 127 128 /* Intel/AMD: Fall back to leaf 0xB if available */ 129 return tscan->c->cpuid_level >= 0x0b && parse_topology_leaf(tscan, 0x0b); 130 } 131