1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/cpu.h> 3 4 #include <xen/xen.h> 5 6 #include <asm/intel-family.h> 7 #include <asm/apic.h> 8 #include <asm/processor.h> 9 #include <asm/cpuid/api.h> 10 #include <asm/smp.h> 11 12 #include "cpu.h" 13 14 struct x86_topology_system x86_topo_system __ro_after_init; 15 EXPORT_SYMBOL_GPL(x86_topo_system); 16 17 unsigned int __amd_nodes_per_pkg __ro_after_init; 18 EXPORT_SYMBOL_GPL(__amd_nodes_per_pkg); 19 20 /* CPUs which are the primary SMT threads */ 21 struct cpumask __cpu_primary_thread_mask __read_mostly; 22 23 void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom, 24 unsigned int shift, unsigned int ncpus) 25 { 26 topology_update_dom(tscan, dom, shift, ncpus); 27 28 /* Propagate to the upper levels */ 29 for (dom++; dom < TOPO_MAX_DOMAIN; dom++) { 30 tscan->dom_shifts[dom] = tscan->dom_shifts[dom - 1]; 31 tscan->dom_ncpus[dom] = tscan->dom_ncpus[dom - 1]; 32 } 33 } 34 35 enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c) 36 { 37 if (c->x86_vendor == X86_VENDOR_INTEL) { 38 switch (c->topo.intel_type) { 39 case INTEL_CPU_TYPE_ATOM: return TOPO_CPU_TYPE_EFFICIENCY; 40 case INTEL_CPU_TYPE_CORE: return TOPO_CPU_TYPE_PERFORMANCE; 41 } 42 } 43 if (c->x86_vendor == X86_VENDOR_AMD) { 44 switch (c->topo.amd_type) { 45 case 0: return TOPO_CPU_TYPE_PERFORMANCE; 46 case 1: return TOPO_CPU_TYPE_EFFICIENCY; 47 } 48 } 49 50 return TOPO_CPU_TYPE_UNKNOWN; 51 } 52 53 const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) 54 { 55 switch (get_topology_cpu_type(c)) { 56 case TOPO_CPU_TYPE_PERFORMANCE: 57 return "performance"; 58 case TOPO_CPU_TYPE_EFFICIENCY: 59 return "efficiency"; 60 default: 61 return "unknown"; 62 } 63 } 64 65 static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) 66 { 67 struct { 68 u32 cache_type : 5, 69 unused : 21, 70 ncores : 6; 71 } eax; 72 73 if (c->cpuid_level < 4) 74 return 1; 75 76 cpuid_subleaf_reg(4, 0, CPUID_EAX, &eax); 77 if (!eax.cache_type) 78 return 1; 79 80 return eax.ncores + 1; 81 } 82 83 static void parse_legacy(struct topo_scan *tscan) 84 { 85 unsigned int cores, core_shift, smt_shift = 0; 86 struct cpuinfo_x86 *c = tscan->c; 87 88 cores = parse_num_cores_legacy(c); 89 core_shift = get_count_order(cores); 90 91 if (cpu_has(c, X86_FEATURE_HT)) { 92 if (!WARN_ON_ONCE(tscan->ebx1_nproc_shift < core_shift)) 93 smt_shift = tscan->ebx1_nproc_shift - core_shift; 94 /* 95 * The parser expects leaf 0xb/0x1f format, which means 96 * the number of logical processors at core level is 97 * counting threads. 98 */ 99 core_shift += smt_shift; 100 cores <<= smt_shift; 101 } 102 103 topology_set_dom(tscan, TOPO_SMT_DOMAIN, smt_shift, 1U << smt_shift); 104 topology_set_dom(tscan, TOPO_CORE_DOMAIN, core_shift, cores); 105 } 106 107 static bool fake_topology(struct topo_scan *tscan) 108 { 109 /* 110 * Preset the CORE level shift for CPUID less systems and XEN_PV, 111 * which has useless CPUID information. 112 */ 113 topology_set_dom(tscan, TOPO_SMT_DOMAIN, 0, 1); 114 topology_set_dom(tscan, TOPO_CORE_DOMAIN, 0, 1); 115 116 return tscan->c->cpuid_level < 1; 117 } 118 119 static void parse_topology(struct topo_scan *tscan, bool early) 120 { 121 const struct cpuinfo_topology topo_defaults = { 122 .cu_id = 0xff, 123 .llc_id = BAD_APICID, 124 .l2c_id = BAD_APICID, 125 .cpu_type = TOPO_CPU_TYPE_UNKNOWN, 126 }; 127 struct cpuinfo_x86 *c = tscan->c; 128 struct { 129 u32 unused0 : 16, 130 nproc : 8, 131 apicid : 8; 132 } ebx; 133 134 c->topo = topo_defaults; 135 136 if (fake_topology(tscan)) 137 return; 138 139 /* Preset Initial APIC ID from CPUID leaf 1 */ 140 cpuid_leaf_reg(1, CPUID_EBX, &ebx); 141 c->topo.initial_apicid = ebx.apicid; 142 143 /* 144 * The initial invocation from early_identify_cpu() happens before 145 * the APIC is mapped or X2APIC enabled. For establishing the 146 * topology, that's not required. Use the initial APIC ID. 147 */ 148 if (early) 149 c->topo.apicid = c->topo.initial_apicid; 150 else 151 c->topo.apicid = read_apic_id(); 152 153 /* The above is sufficient for UP */ 154 if (!IS_ENABLED(CONFIG_SMP)) 155 return; 156 157 tscan->ebx1_nproc_shift = get_count_order(ebx.nproc); 158 159 switch (c->x86_vendor) { 160 case X86_VENDOR_AMD: 161 case X86_VENDOR_HYGON: 162 cpu_parse_topology_amd(tscan); 163 break; 164 case X86_VENDOR_CENTAUR: 165 case X86_VENDOR_ZHAOXIN: 166 parse_legacy(tscan); 167 break; 168 case X86_VENDOR_INTEL: 169 if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) 170 parse_legacy(tscan); 171 if (c->cpuid_level >= 0x1a) 172 c->topo.cpu_type = cpuid_eax(0x1a); 173 break; 174 } 175 } 176 177 static void topo_set_ids(struct topo_scan *tscan, bool early) 178 { 179 struct cpuinfo_x86 *c = tscan->c; 180 u32 apicid = c->topo.apicid; 181 182 c->topo.pkg_id = topo_shift_apicid(apicid, TOPO_PKG_DOMAIN); 183 c->topo.die_id = topo_shift_apicid(apicid, TOPO_DIE_DOMAIN); 184 185 if (!early) { 186 c->topo.logical_pkg_id = topology_get_logical_id(apicid, TOPO_PKG_DOMAIN); 187 c->topo.logical_die_id = topology_get_logical_id(apicid, TOPO_DIE_DOMAIN); 188 c->topo.logical_core_id = topology_get_logical_id(apicid, TOPO_CORE_DOMAIN); 189 } 190 191 /* Package relative core ID */ 192 c->topo.core_id = (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> 193 x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; 194 195 c->topo.amd_node_id = tscan->amd_node_id; 196 197 if (c->x86_vendor == X86_VENDOR_AMD) 198 cpu_topology_fixup_amd(tscan); 199 } 200 201 void cpu_parse_topology(struct cpuinfo_x86 *c) 202 { 203 unsigned int dom, cpu = smp_processor_id(); 204 struct topo_scan tscan = { .c = c, }; 205 206 parse_topology(&tscan, false); 207 208 if (IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { 209 if (c->topo.initial_apicid != c->topo.apicid) { 210 pr_err(FW_BUG "CPU%4u: APIC ID mismatch. CPUID: 0x%04x APIC: 0x%04x\n", 211 cpu, c->topo.initial_apicid, c->topo.apicid); 212 } 213 214 if (c->topo.apicid != cpuid_to_apicid[cpu]) { 215 pr_err(FW_BUG "CPU%4u: APIC ID mismatch. Firmware: 0x%04x APIC: 0x%04x\n", 216 cpu, cpuid_to_apicid[cpu], c->topo.apicid); 217 } 218 } 219 220 for (dom = TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) { 221 if (tscan.dom_shifts[dom] == x86_topo_system.dom_shifts[dom]) 222 continue; 223 pr_err(FW_BUG "CPU%d: Topology domain %u shift %u != %u\n", cpu, dom, 224 tscan.dom_shifts[dom], x86_topo_system.dom_shifts[dom]); 225 } 226 227 topo_set_ids(&tscan, false); 228 } 229 230 void __init cpu_init_topology(struct cpuinfo_x86 *c) 231 { 232 struct topo_scan tscan = { .c = c, }; 233 unsigned int dom, sft; 234 235 parse_topology(&tscan, true); 236 237 /* Copy the shift values and calculate the unit sizes. */ 238 memcpy(x86_topo_system.dom_shifts, tscan.dom_shifts, sizeof(x86_topo_system.dom_shifts)); 239 240 dom = TOPO_SMT_DOMAIN; 241 x86_topo_system.dom_size[dom] = 1U << x86_topo_system.dom_shifts[dom]; 242 243 for (dom++; dom < TOPO_MAX_DOMAIN; dom++) { 244 sft = x86_topo_system.dom_shifts[dom] - x86_topo_system.dom_shifts[dom - 1]; 245 x86_topo_system.dom_size[dom] = 1U << sft; 246 } 247 248 topo_set_ids(&tscan, true); 249 250 /* 251 * AMD systems have Nodes per package which cannot be mapped to 252 * APIC ID. 253 */ 254 __amd_nodes_per_pkg = tscan.amd_nodes_per_pkg; 255 } 256