1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_RESCTRL_INTERNAL_H 3 #define _ASM_X86_RESCTRL_INTERNAL_H 4 5 #include <linux/resctrl.h> 6 7 #define L3_QOS_CDP_ENABLE 0x01ULL 8 9 #define L2_QOS_CDP_ENABLE 0x01ULL 10 11 #define MBM_CNTR_WIDTH_BASE 24 12 13 #define MBA_IS_LINEAR 0x4 14 15 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 16 17 #define RMID_VAL_ERROR BIT_ULL(63) 18 19 #define RMID_VAL_UNAVAIL BIT_ULL(62) 20 21 /* 22 * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for 23 * data to be returned. The counter width is discovered from the hardware 24 * as an offset from MBM_CNTR_WIDTH_BASE. 25 */ 26 #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) 27 28 /** 29 * struct arch_mbm_state - values used to compute resctrl_arch_rmid_read()s 30 * return value. 31 * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes) 32 * @prev_msr: Value of IA32_QM_CTR last time it was read for the RMID used to 33 * find this struct. 34 */ 35 struct arch_mbm_state { 36 u64 chunks; 37 u64 prev_msr; 38 }; 39 40 /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ 41 #define ABMC_ENABLE_BIT 0 42 43 /* 44 * Qos Event Identifiers. 45 */ 46 #define ABMC_EXTENDED_EVT_ID BIT(31) 47 #define ABMC_EVT_ID BIT(0) 48 49 /* Setting bit 1 in MSR_IA32_L3_QOS_EXT_CFG enables the SDCIAE feature. */ 50 #define SDCIAE_ENABLE_BIT 1 51 52 /** 53 * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share 54 * a resource for a control function 55 * @d_resctrl: Properties exposed to the resctrl file system 56 * @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID) 57 * 58 * Members of this structure are accessed via helpers that provide abstraction. 59 */ 60 struct rdt_hw_ctrl_domain { 61 struct rdt_ctrl_domain d_resctrl; 62 u32 *ctrl_val; 63 }; 64 65 /** 66 * struct rdt_hw_mon_domain - Arch private attributes of a set of CPUs that share 67 * a resource for a monitor function 68 * @d_resctrl: Properties exposed to the resctrl file system 69 * @arch_mbm_states: Per-event pointer to the MBM event's saved state. 70 * An MBM event's state is an array of struct arch_mbm_state 71 * indexed by RMID on x86. 72 * 73 * Members of this structure are accessed via helpers that provide abstraction. 74 */ 75 struct rdt_hw_mon_domain { 76 struct rdt_mon_domain d_resctrl; 77 struct arch_mbm_state *arch_mbm_states[QOS_NUM_L3_MBM_EVENTS]; 78 }; 79 80 static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct rdt_ctrl_domain *r) 81 { 82 return container_of(r, struct rdt_hw_ctrl_domain, d_resctrl); 83 } 84 85 static inline struct rdt_hw_mon_domain *resctrl_to_arch_mon_dom(struct rdt_mon_domain *r) 86 { 87 return container_of(r, struct rdt_hw_mon_domain, d_resctrl); 88 } 89 90 /** 91 * struct msr_param - set a range of MSRs from a domain 92 * @res: The resource to use 93 * @dom: The domain to update 94 * @low: Beginning index from base MSR 95 * @high: End index 96 */ 97 struct msr_param { 98 struct rdt_resource *res; 99 struct rdt_ctrl_domain *dom; 100 u32 low; 101 u32 high; 102 }; 103 104 /** 105 * struct rdt_hw_resource - arch private attributes of a resctrl resource 106 * @r_resctrl: Attributes of the resource used directly by resctrl. 107 * @num_closid: Maximum number of closid this hardware can support, 108 * regardless of CDP. This is exposed via 109 * resctrl_arch_get_num_closid() to avoid confusion 110 * with struct resctrl_schema's property of the same name, 111 * which has been corrected for features like CDP. 112 * @msr_base: Base MSR address for CBMs 113 * @msr_update: Function pointer to update QOS MSRs 114 * @mon_scale: cqm counter * mon_scale = occupancy in bytes 115 * @mbm_width: Monitor width, to detect and correct for overflow. 116 * @cdp_enabled: CDP state of this resource 117 * @mbm_cntr_assign_enabled: ABMC feature is enabled 118 * @sdciae_enabled: SDCIAE feature (backing "io_alloc") is enabled. 119 * 120 * Members of this structure are either private to the architecture 121 * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. 122 * msr_update and msr_base. 123 */ 124 struct rdt_hw_resource { 125 struct rdt_resource r_resctrl; 126 u32 num_closid; 127 unsigned int msr_base; 128 void (*msr_update)(struct msr_param *m); 129 unsigned int mon_scale; 130 unsigned int mbm_width; 131 bool cdp_enabled; 132 bool mbm_cntr_assign_enabled; 133 bool sdciae_enabled; 134 }; 135 136 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) 137 { 138 return container_of(r, struct rdt_hw_resource, r_resctrl); 139 } 140 141 extern struct rdt_hw_resource rdt_resources_all[]; 142 143 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain *d); 144 145 /* CPUID.(EAX=10H, ECX=ResID=1).EAX */ 146 union cpuid_0x10_1_eax { 147 struct { 148 unsigned int cbm_len:5; 149 } split; 150 unsigned int full; 151 }; 152 153 /* CPUID.(EAX=10H, ECX=ResID=3).EAX */ 154 union cpuid_0x10_3_eax { 155 struct { 156 unsigned int max_delay:12; 157 } split; 158 unsigned int full; 159 }; 160 161 /* CPUID.(EAX=10H, ECX=ResID).ECX */ 162 union cpuid_0x10_x_ecx { 163 struct { 164 unsigned int reserved:3; 165 unsigned int noncont:1; 166 } split; 167 unsigned int full; 168 }; 169 170 /* CPUID.(EAX=10H, ECX=ResID).EDX */ 171 union cpuid_0x10_x_edx { 172 struct { 173 unsigned int cos_max:16; 174 } split; 175 unsigned int full; 176 }; 177 178 /* 179 * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG. 180 * 181 * @bw_type : Event configuration that represents the memory 182 * transactions being tracked by the @cntr_id. 183 * @bw_src : Bandwidth source (RMID or CLOSID). 184 * @reserved1 : Reserved. 185 * @is_clos : @bw_src field is a CLOSID (not an RMID). 186 * @cntr_id : Counter identifier. 187 * @reserved : Reserved. 188 * @cntr_en : Counting enable bit. 189 * @cfg_en : Configuration enable bit. 190 * 191 * Configuration and counting: 192 * Counter can be configured across multiple writes to MSR. Configuration 193 * is applied only when @cfg_en = 1. Counter @cntr_id is reset when the 194 * configuration is applied. 195 * @cfg_en = 1, @cntr_en = 0 : Apply @cntr_id configuration but do not 196 * count events. 197 * @cfg_en = 1, @cntr_en = 1 : Apply @cntr_id configuration and start 198 * counting events. 199 */ 200 union l3_qos_abmc_cfg { 201 struct { 202 unsigned long bw_type :32, 203 bw_src :12, 204 reserved1: 3, 205 is_clos : 1, 206 cntr_id : 5, 207 reserved : 9, 208 cntr_en : 1, 209 cfg_en : 1; 210 } split; 211 unsigned long full; 212 }; 213 214 void rdt_ctrl_update(void *arg); 215 216 int rdt_get_mon_l3_config(struct rdt_resource *r); 217 218 bool rdt_cpu_has(int flag); 219 220 void __init intel_rdt_mbm_apply_quirk(void); 221 222 void rdt_domain_reconfigure_cdp(struct rdt_resource *r); 223 void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r); 224 225 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ 226