1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_RESCTRL_INTERNAL_H 3 #define _ASM_X86_RESCTRL_INTERNAL_H 4 5 #include <linux/resctrl.h> 6 7 #define L3_QOS_CDP_ENABLE 0x01ULL 8 9 #define L2_QOS_CDP_ENABLE 0x01ULL 10 11 #define MBM_CNTR_WIDTH_BASE 24 12 13 #define MBA_IS_LINEAR 0x4 14 15 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 16 17 /* Hygon MBM counter width as an offset from MBM_CNTR_WIDTH_BASE */ 18 #define MBM_CNTR_WIDTH_OFFSET_HYGON 8 19 20 #define RMID_VAL_ERROR BIT_ULL(63) 21 22 #define RMID_VAL_UNAVAIL BIT_ULL(62) 23 24 /* 25 * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for 26 * data to be returned. The counter width is discovered from the hardware 27 * as an offset from MBM_CNTR_WIDTH_BASE. 28 */ 29 #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) 30 31 /** 32 * struct arch_mbm_state - values used to compute resctrl_arch_rmid_read()s 33 * return value. 34 * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes) 35 * @prev_msr: Value of IA32_QM_CTR last time it was read for the RMID used to 36 * find this struct. 37 */ 38 struct arch_mbm_state { 39 u64 chunks; 40 u64 prev_msr; 41 }; 42 43 /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ 44 #define ABMC_ENABLE_BIT 0 45 46 /* 47 * Qos Event Identifiers. 48 */ 49 #define ABMC_EXTENDED_EVT_ID BIT(31) 50 #define ABMC_EVT_ID BIT(0) 51 52 /* Setting bit 1 in MSR_IA32_L3_QOS_EXT_CFG enables the SDCIAE feature. */ 53 #define SDCIAE_ENABLE_BIT 1 54 55 /** 56 * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share 57 * a resource for a control function 58 * @d_resctrl: Properties exposed to the resctrl file system 59 * @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID) 60 * 61 * Members of this structure are accessed via helpers that provide abstraction. 62 */ 63 struct rdt_hw_ctrl_domain { 64 struct rdt_ctrl_domain d_resctrl; 65 u32 *ctrl_val; 66 }; 67 68 /** 69 * struct rdt_hw_mon_domain - Arch private attributes of a set of CPUs that share 70 * a resource for a monitor function 71 * @d_resctrl: Properties exposed to the resctrl file system 72 * @arch_mbm_states: Per-event pointer to the MBM event's saved state. 73 * An MBM event's state is an array of struct arch_mbm_state 74 * indexed by RMID on x86. 75 * 76 * Members of this structure are accessed via helpers that provide abstraction. 77 */ 78 struct rdt_hw_mon_domain { 79 struct rdt_mon_domain d_resctrl; 80 struct arch_mbm_state *arch_mbm_states[QOS_NUM_L3_MBM_EVENTS]; 81 }; 82 83 static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct rdt_ctrl_domain *r) 84 { 85 return container_of(r, struct rdt_hw_ctrl_domain, d_resctrl); 86 } 87 88 static inline struct rdt_hw_mon_domain *resctrl_to_arch_mon_dom(struct rdt_mon_domain *r) 89 { 90 return container_of(r, struct rdt_hw_mon_domain, d_resctrl); 91 } 92 93 /** 94 * struct msr_param - set a range of MSRs from a domain 95 * @res: The resource to use 96 * @dom: The domain to update 97 * @low: Beginning index from base MSR 98 * @high: End index 99 */ 100 struct msr_param { 101 struct rdt_resource *res; 102 struct rdt_ctrl_domain *dom; 103 u32 low; 104 u32 high; 105 }; 106 107 /** 108 * struct rdt_hw_resource - arch private attributes of a resctrl resource 109 * @r_resctrl: Attributes of the resource used directly by resctrl. 110 * @num_closid: Maximum number of closid this hardware can support, 111 * regardless of CDP. This is exposed via 112 * resctrl_arch_get_num_closid() to avoid confusion 113 * with struct resctrl_schema's property of the same name, 114 * which has been corrected for features like CDP. 115 * @msr_base: Base MSR address for CBMs 116 * @msr_update: Function pointer to update QOS MSRs 117 * @mon_scale: cqm counter * mon_scale = occupancy in bytes 118 * @mbm_width: Monitor width, to detect and correct for overflow. 119 * @cdp_enabled: CDP state of this resource 120 * @mbm_cntr_assign_enabled: ABMC feature is enabled 121 * @sdciae_enabled: SDCIAE feature (backing "io_alloc") is enabled. 122 * 123 * Members of this structure are either private to the architecture 124 * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. 125 * msr_update and msr_base. 126 */ 127 struct rdt_hw_resource { 128 struct rdt_resource r_resctrl; 129 u32 num_closid; 130 unsigned int msr_base; 131 void (*msr_update)(struct msr_param *m); 132 unsigned int mon_scale; 133 unsigned int mbm_width; 134 bool cdp_enabled; 135 bool mbm_cntr_assign_enabled; 136 bool sdciae_enabled; 137 }; 138 139 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) 140 { 141 return container_of(r, struct rdt_hw_resource, r_resctrl); 142 } 143 144 extern struct rdt_hw_resource rdt_resources_all[]; 145 146 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain *d); 147 148 /* CPUID.(EAX=10H, ECX=ResID=1).EAX */ 149 union cpuid_0x10_1_eax { 150 struct { 151 unsigned int cbm_len:5; 152 } split; 153 unsigned int full; 154 }; 155 156 /* CPUID.(EAX=10H, ECX=ResID=3).EAX */ 157 union cpuid_0x10_3_eax { 158 struct { 159 unsigned int max_delay:12; 160 } split; 161 unsigned int full; 162 }; 163 164 /* CPUID.(EAX=10H, ECX=ResID).ECX */ 165 union cpuid_0x10_x_ecx { 166 struct { 167 unsigned int reserved:3; 168 unsigned int noncont:1; 169 } split; 170 unsigned int full; 171 }; 172 173 /* CPUID.(EAX=10H, ECX=ResID).EDX */ 174 union cpuid_0x10_x_edx { 175 struct { 176 unsigned int cos_max:16; 177 } split; 178 unsigned int full; 179 }; 180 181 /* 182 * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG. 183 * 184 * @bw_type : Event configuration that represents the memory 185 * transactions being tracked by the @cntr_id. 186 * @bw_src : Bandwidth source (RMID or CLOSID). 187 * @reserved1 : Reserved. 188 * @is_clos : @bw_src field is a CLOSID (not an RMID). 189 * @cntr_id : Counter identifier. 190 * @reserved : Reserved. 191 * @cntr_en : Counting enable bit. 192 * @cfg_en : Configuration enable bit. 193 * 194 * Configuration and counting: 195 * Counter can be configured across multiple writes to MSR. Configuration 196 * is applied only when @cfg_en = 1. Counter @cntr_id is reset when the 197 * configuration is applied. 198 * @cfg_en = 1, @cntr_en = 0 : Apply @cntr_id configuration but do not 199 * count events. 200 * @cfg_en = 1, @cntr_en = 1 : Apply @cntr_id configuration and start 201 * counting events. 202 */ 203 union l3_qos_abmc_cfg { 204 struct { 205 unsigned long bw_type :32, 206 bw_src :12, 207 reserved1: 3, 208 is_clos : 1, 209 cntr_id : 5, 210 reserved : 9, 211 cntr_en : 1, 212 cfg_en : 1; 213 } split; 214 unsigned long full; 215 }; 216 217 void rdt_ctrl_update(void *arg); 218 219 int rdt_get_mon_l3_config(struct rdt_resource *r); 220 221 bool rdt_cpu_has(int flag); 222 223 void __init intel_rdt_mbm_apply_quirk(void); 224 225 void rdt_domain_reconfigure_cdp(struct rdt_resource *r); 226 void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r); 227 228 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ 229