1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Resource Director Technology(RDT) 4 * - Cache Allocation code. 5 * 6 * Copyright (C) 2016 Intel Corporation 7 * 8 * Authors: 9 * Fenghua Yu <fenghua.yu@intel.com> 10 * Tony Luck <tony.luck@intel.com> 11 * Vikas Shivappa <vikas.shivappa@intel.com> 12 * 13 * More information about RDT be found in the Intel (R) x86 Architecture 14 * Software Developer Manual June 2016, volume 3, section 17.17. 15 */ 16 17 #define pr_fmt(fmt) "resctrl: " fmt 18 19 #include <linux/cpu.h> 20 #include <linux/slab.h> 21 #include <linux/err.h> 22 #include <linux/cpuhotplug.h> 23 24 #include <asm/cpu_device_id.h> 25 #include <asm/msr.h> 26 #include <asm/resctrl.h> 27 #include "internal.h" 28 29 /* 30 * rdt_domain structures are kfree()d when their last CPU goes offline, 31 * and allocated when the first CPU in a new domain comes online. 32 * The rdt_resource's domain list is updated when this happens. Readers of 33 * the domain list must either take cpus_read_lock(), or rely on an RCU 34 * read-side critical section, to avoid observing concurrent modification. 35 * All writers take this mutex: 36 */ 37 static DEFINE_MUTEX(domain_list_lock); 38 39 /* 40 * The cached resctrl_pqr_state is strictly per CPU and can never be 41 * updated from a remote CPU. Functions which modify the state 42 * are called with interrupts disabled and no preemption, which 43 * is sufficient for the protection. 44 */ 45 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); 46 47 /* 48 * Global boolean for rdt_alloc which is true if any 49 * resource allocation is enabled. 50 */ 51 bool rdt_alloc_capable; 52 53 static void mba_wrmsr_intel(struct msr_param *m); 54 static void cat_wrmsr(struct msr_param *m); 55 static void mba_wrmsr_amd(struct msr_param *m); 56 57 #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains) 58 #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) 59 60 struct rdt_hw_resource rdt_resources_all[RDT_NUM_RESOURCES] = { 61 [RDT_RESOURCE_L3] = 62 { 63 .r_resctrl = { 64 .name = "L3", 65 .ctrl_scope = RESCTRL_L3_CACHE, 66 .mon_scope = RESCTRL_L3_CACHE, 67 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3), 68 .mon_domains = mon_domain_init(RDT_RESOURCE_L3), 69 .schema_fmt = RESCTRL_SCHEMA_BITMAP, 70 }, 71 .msr_base = MSR_IA32_L3_CBM_BASE, 72 .msr_update = cat_wrmsr, 73 }, 74 [RDT_RESOURCE_L2] = 75 { 76 .r_resctrl = { 77 .name = "L2", 78 .ctrl_scope = RESCTRL_L2_CACHE, 79 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2), 80 .schema_fmt = RESCTRL_SCHEMA_BITMAP, 81 }, 82 .msr_base = MSR_IA32_L2_CBM_BASE, 83 .msr_update = cat_wrmsr, 84 }, 85 [RDT_RESOURCE_MBA] = 86 { 87 .r_resctrl = { 88 .name = "MB", 89 .ctrl_scope = RESCTRL_L3_CACHE, 90 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA), 91 .schema_fmt = RESCTRL_SCHEMA_RANGE, 92 }, 93 }, 94 [RDT_RESOURCE_SMBA] = 95 { 96 .r_resctrl = { 97 .name = "SMBA", 98 .ctrl_scope = RESCTRL_L3_CACHE, 99 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA), 100 .schema_fmt = RESCTRL_SCHEMA_RANGE, 101 }, 102 }, 103 }; 104 105 u32 resctrl_arch_system_num_rmid_idx(void) 106 { 107 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 108 109 /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */ 110 return r->num_rmid; 111 } 112 113 struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) 114 { 115 if (l >= RDT_NUM_RESOURCES) 116 return NULL; 117 118 return &rdt_resources_all[l].r_resctrl; 119 } 120 121 /* 122 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs 123 * as they do not have CPUID enumeration support for Cache allocation. 124 * The check for Vendor/Family/Model is not enough to guarantee that 125 * the MSRs won't #GP fault because only the following SKUs support 126 * CAT: 127 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz 128 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz 129 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz 130 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz 131 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz 132 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz 133 * 134 * Probe by trying to write the first of the L3 cache mask registers 135 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length 136 * is always 20 on hsw server parts. The minimum cache bitmask length 137 * allowed for HSW server is always 2 bits. Hardcode all of them. 138 */ 139 static inline void cache_alloc_hsw_probe(void) 140 { 141 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; 142 struct rdt_resource *r = &hw_res->r_resctrl; 143 u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0; 144 145 if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) 146 return; 147 148 rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0); 149 150 /* If all the bits were set in MSR, return success */ 151 if (l3_cbm_0 != max_cbm) 152 return; 153 154 hw_res->num_closid = 4; 155 r->cache.cbm_len = 20; 156 r->cache.shareable_bits = 0xc0000; 157 r->cache.min_cbm_bits = 2; 158 r->cache.arch_has_sparse_bitmasks = false; 159 r->alloc_capable = true; 160 161 rdt_alloc_capable = true; 162 } 163 164 /* 165 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values 166 * exposed to user interface and the h/w understandable delay values. 167 * 168 * The non-linear delay values have the granularity of power of two 169 * and also the h/w does not guarantee a curve for configured delay 170 * values vs. actual b/w enforced. 171 * Hence we need a mapping that is pre calibrated so the user can 172 * express the memory b/w as a percentage value. 173 */ 174 static inline bool rdt_get_mb_table(struct rdt_resource *r) 175 { 176 /* 177 * There are no Intel SKUs as of now to support non-linear delay. 178 */ 179 pr_info("MBA b/w map not implemented for cpu:%d, model:%d", 180 boot_cpu_data.x86, boot_cpu_data.x86_model); 181 182 return false; 183 } 184 185 static __init bool __get_mem_config_intel(struct rdt_resource *r) 186 { 187 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 188 union cpuid_0x10_3_eax eax; 189 union cpuid_0x10_x_edx edx; 190 u32 ebx, ecx, max_delay; 191 192 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); 193 hw_res->num_closid = edx.split.cos_max + 1; 194 max_delay = eax.split.max_delay + 1; 195 r->membw.max_bw = MAX_MBA_BW; 196 r->membw.arch_needs_linear = true; 197 if (ecx & MBA_IS_LINEAR) { 198 r->membw.delay_linear = true; 199 r->membw.min_bw = MAX_MBA_BW - max_delay; 200 r->membw.bw_gran = MAX_MBA_BW - max_delay; 201 } else { 202 if (!rdt_get_mb_table(r)) 203 return false; 204 r->membw.arch_needs_linear = false; 205 } 206 207 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) 208 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; 209 else 210 r->membw.throttle_mode = THREAD_THROTTLE_MAX; 211 212 r->alloc_capable = true; 213 214 return true; 215 } 216 217 static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r) 218 { 219 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 220 u32 eax, ebx, ecx, edx, subleaf; 221 222 /* 223 * Query CPUID_Fn80000020_EDX_x01 for MBA and 224 * CPUID_Fn80000020_EDX_x02 for SMBA 225 */ 226 subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1; 227 228 cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); 229 hw_res->num_closid = edx + 1; 230 r->membw.max_bw = 1 << eax; 231 232 /* AMD does not use delay */ 233 r->membw.delay_linear = false; 234 r->membw.arch_needs_linear = false; 235 236 /* 237 * AMD does not use memory delay throttle model to control 238 * the allocation like Intel does. 239 */ 240 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; 241 r->membw.min_bw = 0; 242 r->membw.bw_gran = 1; 243 244 r->alloc_capable = true; 245 246 return true; 247 } 248 249 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 250 { 251 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 252 union cpuid_0x10_1_eax eax; 253 union cpuid_0x10_x_ecx ecx; 254 union cpuid_0x10_x_edx edx; 255 u32 ebx, default_ctrl; 256 257 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); 258 hw_res->num_closid = edx.split.cos_max + 1; 259 r->cache.cbm_len = eax.split.cbm_len + 1; 260 default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; 261 r->cache.shareable_bits = ebx & default_ctrl; 262 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 263 r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; 264 r->alloc_capable = true; 265 } 266 267 static void rdt_get_cdp_config(int level) 268 { 269 /* 270 * By default, CDP is disabled. CDP can be enabled by mount parameter 271 * "cdp" during resctrl file system mount time. 272 */ 273 rdt_resources_all[level].cdp_enabled = false; 274 rdt_resources_all[level].r_resctrl.cdp_capable = true; 275 } 276 277 static void rdt_get_cdp_l3_config(void) 278 { 279 rdt_get_cdp_config(RDT_RESOURCE_L3); 280 } 281 282 static void rdt_get_cdp_l2_config(void) 283 { 284 rdt_get_cdp_config(RDT_RESOURCE_L2); 285 } 286 287 static void mba_wrmsr_amd(struct msr_param *m) 288 { 289 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 290 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 291 unsigned int i; 292 293 for (i = m->low; i < m->high; i++) 294 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 295 } 296 297 /* 298 * Map the memory b/w percentage value to delay values 299 * that can be written to QOS_MSRs. 300 * There are currently no SKUs which support non linear delay values. 301 */ 302 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) 303 { 304 if (r->membw.delay_linear) 305 return MAX_MBA_BW - bw; 306 307 pr_warn_once("Non Linear delay-bw map not supported but queried\n"); 308 return MAX_MBA_BW; 309 } 310 311 static void mba_wrmsr_intel(struct msr_param *m) 312 { 313 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 314 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 315 unsigned int i; 316 317 /* Write the delay values for mba. */ 318 for (i = m->low; i < m->high; i++) 319 wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); 320 } 321 322 static void cat_wrmsr(struct msr_param *m) 323 { 324 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 325 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 326 unsigned int i; 327 328 for (i = m->low; i < m->high; i++) 329 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 330 } 331 332 u32 resctrl_arch_get_num_closid(struct rdt_resource *r) 333 { 334 return resctrl_to_arch_res(r)->num_closid; 335 } 336 337 void rdt_ctrl_update(void *arg) 338 { 339 struct rdt_hw_resource *hw_res; 340 struct msr_param *m = arg; 341 342 hw_res = resctrl_to_arch_res(m->res); 343 hw_res->msr_update(m); 344 } 345 346 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc) 347 { 348 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 349 int i; 350 351 /* 352 * Initialize the Control MSRs to having no control. 353 * For Cache Allocation: Set all bits in cbm 354 * For Memory Allocation: Set b/w requested to 100% 355 */ 356 for (i = 0; i < hw_res->num_closid; i++, dc++) 357 *dc = resctrl_get_default_ctrl(r); 358 } 359 360 static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom) 361 { 362 kfree(hw_dom->ctrl_val); 363 kfree(hw_dom); 364 } 365 366 static void mon_domain_free(struct rdt_hw_mon_domain *hw_dom) 367 { 368 kfree(hw_dom->arch_mbm_total); 369 kfree(hw_dom->arch_mbm_local); 370 kfree(hw_dom); 371 } 372 373 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d) 374 { 375 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); 376 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 377 struct msr_param m; 378 u32 *dc; 379 380 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), 381 GFP_KERNEL); 382 if (!dc) 383 return -ENOMEM; 384 385 hw_dom->ctrl_val = dc; 386 setup_default_ctrlval(r, dc); 387 388 m.res = r; 389 m.dom = d; 390 m.low = 0; 391 m.high = hw_res->num_closid; 392 hw_res->msr_update(&m); 393 return 0; 394 } 395 396 /** 397 * arch_domain_mbm_alloc() - Allocate arch private storage for the MBM counters 398 * @num_rmid: The size of the MBM counter array 399 * @hw_dom: The domain that owns the allocated arrays 400 */ 401 static int arch_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_mon_domain *hw_dom) 402 { 403 size_t tsize; 404 405 if (resctrl_arch_is_mbm_total_enabled()) { 406 tsize = sizeof(*hw_dom->arch_mbm_total); 407 hw_dom->arch_mbm_total = kcalloc(num_rmid, tsize, GFP_KERNEL); 408 if (!hw_dom->arch_mbm_total) 409 return -ENOMEM; 410 } 411 if (resctrl_arch_is_mbm_local_enabled()) { 412 tsize = sizeof(*hw_dom->arch_mbm_local); 413 hw_dom->arch_mbm_local = kcalloc(num_rmid, tsize, GFP_KERNEL); 414 if (!hw_dom->arch_mbm_local) { 415 kfree(hw_dom->arch_mbm_total); 416 hw_dom->arch_mbm_total = NULL; 417 return -ENOMEM; 418 } 419 } 420 421 return 0; 422 } 423 424 static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope) 425 { 426 switch (scope) { 427 case RESCTRL_L2_CACHE: 428 case RESCTRL_L3_CACHE: 429 return get_cpu_cacheinfo_id(cpu, scope); 430 case RESCTRL_L3_NODE: 431 return cpu_to_node(cpu); 432 default: 433 break; 434 } 435 436 return -EINVAL; 437 } 438 439 static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r) 440 { 441 int id = get_domain_id_from_scope(cpu, r->ctrl_scope); 442 struct rdt_hw_ctrl_domain *hw_dom; 443 struct list_head *add_pos = NULL; 444 struct rdt_domain_hdr *hdr; 445 struct rdt_ctrl_domain *d; 446 int err; 447 448 lockdep_assert_held(&domain_list_lock); 449 450 if (id < 0) { 451 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", 452 cpu, r->ctrl_scope, r->name); 453 return; 454 } 455 456 hdr = resctrl_find_domain(&r->ctrl_domains, id, &add_pos); 457 if (hdr) { 458 if (WARN_ON_ONCE(hdr->type != RESCTRL_CTRL_DOMAIN)) 459 return; 460 d = container_of(hdr, struct rdt_ctrl_domain, hdr); 461 462 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 463 if (r->cache.arch_has_per_cpu_cfg) 464 rdt_domain_reconfigure_cdp(r); 465 return; 466 } 467 468 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 469 if (!hw_dom) 470 return; 471 472 d = &hw_dom->d_resctrl; 473 d->hdr.id = id; 474 d->hdr.type = RESCTRL_CTRL_DOMAIN; 475 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 476 477 rdt_domain_reconfigure_cdp(r); 478 479 if (domain_setup_ctrlval(r, d)) { 480 ctrl_domain_free(hw_dom); 481 return; 482 } 483 484 list_add_tail_rcu(&d->hdr.list, add_pos); 485 486 err = resctrl_online_ctrl_domain(r, d); 487 if (err) { 488 list_del_rcu(&d->hdr.list); 489 synchronize_rcu(); 490 ctrl_domain_free(hw_dom); 491 } 492 } 493 494 static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) 495 { 496 int id = get_domain_id_from_scope(cpu, r->mon_scope); 497 struct list_head *add_pos = NULL; 498 struct rdt_hw_mon_domain *hw_dom; 499 struct rdt_domain_hdr *hdr; 500 struct rdt_mon_domain *d; 501 struct cacheinfo *ci; 502 int err; 503 504 lockdep_assert_held(&domain_list_lock); 505 506 if (id < 0) { 507 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n", 508 cpu, r->mon_scope, r->name); 509 return; 510 } 511 512 hdr = resctrl_find_domain(&r->mon_domains, id, &add_pos); 513 if (hdr) { 514 if (WARN_ON_ONCE(hdr->type != RESCTRL_MON_DOMAIN)) 515 return; 516 d = container_of(hdr, struct rdt_mon_domain, hdr); 517 518 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 519 return; 520 } 521 522 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 523 if (!hw_dom) 524 return; 525 526 d = &hw_dom->d_resctrl; 527 d->hdr.id = id; 528 d->hdr.type = RESCTRL_MON_DOMAIN; 529 ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); 530 if (!ci) { 531 pr_warn_once("Can't find L3 cache for CPU:%d resource %s\n", cpu, r->name); 532 mon_domain_free(hw_dom); 533 return; 534 } 535 d->ci_id = ci->id; 536 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 537 538 arch_mon_domain_online(r, d); 539 540 if (arch_domain_mbm_alloc(r->num_rmid, hw_dom)) { 541 mon_domain_free(hw_dom); 542 return; 543 } 544 545 list_add_tail_rcu(&d->hdr.list, add_pos); 546 547 err = resctrl_online_mon_domain(r, d); 548 if (err) { 549 list_del_rcu(&d->hdr.list); 550 synchronize_rcu(); 551 mon_domain_free(hw_dom); 552 } 553 } 554 555 static void domain_add_cpu(int cpu, struct rdt_resource *r) 556 { 557 if (r->alloc_capable) 558 domain_add_cpu_ctrl(cpu, r); 559 if (r->mon_capable) 560 domain_add_cpu_mon(cpu, r); 561 } 562 563 static void domain_remove_cpu_ctrl(int cpu, struct rdt_resource *r) 564 { 565 int id = get_domain_id_from_scope(cpu, r->ctrl_scope); 566 struct rdt_hw_ctrl_domain *hw_dom; 567 struct rdt_domain_hdr *hdr; 568 struct rdt_ctrl_domain *d; 569 570 lockdep_assert_held(&domain_list_lock); 571 572 if (id < 0) { 573 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", 574 cpu, r->ctrl_scope, r->name); 575 return; 576 } 577 578 hdr = resctrl_find_domain(&r->ctrl_domains, id, NULL); 579 if (!hdr) { 580 pr_warn("Can't find control domain for id=%d for CPU %d for resource %s\n", 581 id, cpu, r->name); 582 return; 583 } 584 585 if (WARN_ON_ONCE(hdr->type != RESCTRL_CTRL_DOMAIN)) 586 return; 587 588 d = container_of(hdr, struct rdt_ctrl_domain, hdr); 589 hw_dom = resctrl_to_arch_ctrl_dom(d); 590 591 cpumask_clear_cpu(cpu, &d->hdr.cpu_mask); 592 if (cpumask_empty(&d->hdr.cpu_mask)) { 593 resctrl_offline_ctrl_domain(r, d); 594 list_del_rcu(&d->hdr.list); 595 synchronize_rcu(); 596 597 /* 598 * rdt_ctrl_domain "d" is going to be freed below, so clear 599 * its pointer from pseudo_lock_region struct. 600 */ 601 if (d->plr) 602 d->plr->d = NULL; 603 ctrl_domain_free(hw_dom); 604 605 return; 606 } 607 } 608 609 static void domain_remove_cpu_mon(int cpu, struct rdt_resource *r) 610 { 611 int id = get_domain_id_from_scope(cpu, r->mon_scope); 612 struct rdt_hw_mon_domain *hw_dom; 613 struct rdt_domain_hdr *hdr; 614 struct rdt_mon_domain *d; 615 616 lockdep_assert_held(&domain_list_lock); 617 618 if (id < 0) { 619 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n", 620 cpu, r->mon_scope, r->name); 621 return; 622 } 623 624 hdr = resctrl_find_domain(&r->mon_domains, id, NULL); 625 if (!hdr) { 626 pr_warn("Can't find monitor domain for id=%d for CPU %d for resource %s\n", 627 id, cpu, r->name); 628 return; 629 } 630 631 if (WARN_ON_ONCE(hdr->type != RESCTRL_MON_DOMAIN)) 632 return; 633 634 d = container_of(hdr, struct rdt_mon_domain, hdr); 635 hw_dom = resctrl_to_arch_mon_dom(d); 636 637 cpumask_clear_cpu(cpu, &d->hdr.cpu_mask); 638 if (cpumask_empty(&d->hdr.cpu_mask)) { 639 resctrl_offline_mon_domain(r, d); 640 list_del_rcu(&d->hdr.list); 641 synchronize_rcu(); 642 mon_domain_free(hw_dom); 643 644 return; 645 } 646 } 647 648 static void domain_remove_cpu(int cpu, struct rdt_resource *r) 649 { 650 if (r->alloc_capable) 651 domain_remove_cpu_ctrl(cpu, r); 652 if (r->mon_capable) 653 domain_remove_cpu_mon(cpu, r); 654 } 655 656 static void clear_closid_rmid(int cpu) 657 { 658 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); 659 660 state->default_closid = RESCTRL_RESERVED_CLOSID; 661 state->default_rmid = RESCTRL_RESERVED_RMID; 662 state->cur_closid = RESCTRL_RESERVED_CLOSID; 663 state->cur_rmid = RESCTRL_RESERVED_RMID; 664 wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID, 665 RESCTRL_RESERVED_CLOSID); 666 } 667 668 static int resctrl_arch_online_cpu(unsigned int cpu) 669 { 670 struct rdt_resource *r; 671 672 mutex_lock(&domain_list_lock); 673 for_each_capable_rdt_resource(r) 674 domain_add_cpu(cpu, r); 675 mutex_unlock(&domain_list_lock); 676 677 clear_closid_rmid(cpu); 678 resctrl_online_cpu(cpu); 679 680 return 0; 681 } 682 683 static int resctrl_arch_offline_cpu(unsigned int cpu) 684 { 685 struct rdt_resource *r; 686 687 resctrl_offline_cpu(cpu); 688 689 mutex_lock(&domain_list_lock); 690 for_each_capable_rdt_resource(r) 691 domain_remove_cpu(cpu, r); 692 mutex_unlock(&domain_list_lock); 693 694 clear_closid_rmid(cpu); 695 696 return 0; 697 } 698 699 enum { 700 RDT_FLAG_CMT, 701 RDT_FLAG_MBM_TOTAL, 702 RDT_FLAG_MBM_LOCAL, 703 RDT_FLAG_L3_CAT, 704 RDT_FLAG_L3_CDP, 705 RDT_FLAG_L2_CAT, 706 RDT_FLAG_L2_CDP, 707 RDT_FLAG_MBA, 708 RDT_FLAG_SMBA, 709 RDT_FLAG_BMEC, 710 }; 711 712 #define RDT_OPT(idx, n, f) \ 713 [idx] = { \ 714 .name = n, \ 715 .flag = f \ 716 } 717 718 struct rdt_options { 719 char *name; 720 int flag; 721 bool force_off, force_on; 722 }; 723 724 static struct rdt_options rdt_options[] __ro_after_init = { 725 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), 726 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), 727 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), 728 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), 729 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), 730 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), 731 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), 732 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), 733 RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), 734 RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), 735 }; 736 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) 737 738 static int __init set_rdt_options(char *str) 739 { 740 struct rdt_options *o; 741 bool force_off; 742 char *tok; 743 744 if (*str == '=') 745 str++; 746 while ((tok = strsep(&str, ",")) != NULL) { 747 force_off = *tok == '!'; 748 if (force_off) 749 tok++; 750 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 751 if (strcmp(tok, o->name) == 0) { 752 if (force_off) 753 o->force_off = true; 754 else 755 o->force_on = true; 756 break; 757 } 758 } 759 } 760 return 1; 761 } 762 __setup("rdt", set_rdt_options); 763 764 bool rdt_cpu_has(int flag) 765 { 766 bool ret = boot_cpu_has(flag); 767 struct rdt_options *o; 768 769 if (!ret) 770 return ret; 771 772 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 773 if (flag == o->flag) { 774 if (o->force_off) 775 ret = false; 776 if (o->force_on) 777 ret = true; 778 break; 779 } 780 } 781 return ret; 782 } 783 784 bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) 785 { 786 if (!rdt_cpu_has(X86_FEATURE_BMEC)) 787 return false; 788 789 switch (evt) { 790 case QOS_L3_MBM_TOTAL_EVENT_ID: 791 return rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL); 792 case QOS_L3_MBM_LOCAL_EVENT_ID: 793 return rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL); 794 default: 795 return false; 796 } 797 } 798 799 static __init bool get_mem_config(void) 800 { 801 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA]; 802 803 if (!rdt_cpu_has(X86_FEATURE_MBA)) 804 return false; 805 806 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 807 return __get_mem_config_intel(&hw_res->r_resctrl); 808 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 809 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 810 811 return false; 812 } 813 814 static __init bool get_slow_mem_config(void) 815 { 816 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA]; 817 818 if (!rdt_cpu_has(X86_FEATURE_SMBA)) 819 return false; 820 821 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 822 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 823 824 return false; 825 } 826 827 static __init bool get_rdt_alloc_resources(void) 828 { 829 struct rdt_resource *r; 830 bool ret = false; 831 832 if (rdt_alloc_capable) 833 return true; 834 835 if (!boot_cpu_has(X86_FEATURE_RDT_A)) 836 return false; 837 838 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { 839 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 840 rdt_get_cache_alloc_cfg(1, r); 841 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 842 rdt_get_cdp_l3_config(); 843 ret = true; 844 } 845 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { 846 /* CPUID 0x10.2 fields are same format at 0x10.1 */ 847 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl; 848 rdt_get_cache_alloc_cfg(2, r); 849 if (rdt_cpu_has(X86_FEATURE_CDP_L2)) 850 rdt_get_cdp_l2_config(); 851 ret = true; 852 } 853 854 if (get_mem_config()) 855 ret = true; 856 857 if (get_slow_mem_config()) 858 ret = true; 859 860 return ret; 861 } 862 863 static __init bool get_rdt_mon_resources(void) 864 { 865 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 866 867 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) 868 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID); 869 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) 870 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID); 871 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) 872 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID); 873 874 if (!rdt_mon_features) 875 return false; 876 877 return !rdt_get_mon_l3_config(r); 878 } 879 880 static __init void __check_quirks_intel(void) 881 { 882 switch (boot_cpu_data.x86_vfm) { 883 case INTEL_HASWELL_X: 884 if (!rdt_options[RDT_FLAG_L3_CAT].force_off) 885 cache_alloc_hsw_probe(); 886 break; 887 case INTEL_SKYLAKE_X: 888 if (boot_cpu_data.x86_stepping <= 4) 889 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); 890 else 891 set_rdt_options("!l3cat"); 892 fallthrough; 893 case INTEL_BROADWELL_X: 894 intel_rdt_mbm_apply_quirk(); 895 break; 896 } 897 } 898 899 static __init void check_quirks(void) 900 { 901 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 902 __check_quirks_intel(); 903 } 904 905 static __init bool get_rdt_resources(void) 906 { 907 rdt_alloc_capable = get_rdt_alloc_resources(); 908 rdt_mon_capable = get_rdt_mon_resources(); 909 910 return (rdt_mon_capable || rdt_alloc_capable); 911 } 912 913 static __init void rdt_init_res_defs_intel(void) 914 { 915 struct rdt_hw_resource *hw_res; 916 struct rdt_resource *r; 917 918 for_each_rdt_resource(r) { 919 hw_res = resctrl_to_arch_res(r); 920 921 if (r->rid == RDT_RESOURCE_L3 || 922 r->rid == RDT_RESOURCE_L2) { 923 r->cache.arch_has_per_cpu_cfg = false; 924 r->cache.min_cbm_bits = 1; 925 } else if (r->rid == RDT_RESOURCE_MBA) { 926 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; 927 hw_res->msr_update = mba_wrmsr_intel; 928 } 929 } 930 } 931 932 static __init void rdt_init_res_defs_amd(void) 933 { 934 struct rdt_hw_resource *hw_res; 935 struct rdt_resource *r; 936 937 for_each_rdt_resource(r) { 938 hw_res = resctrl_to_arch_res(r); 939 940 if (r->rid == RDT_RESOURCE_L3 || 941 r->rid == RDT_RESOURCE_L2) { 942 r->cache.arch_has_sparse_bitmasks = true; 943 r->cache.arch_has_per_cpu_cfg = true; 944 r->cache.min_cbm_bits = 0; 945 } else if (r->rid == RDT_RESOURCE_MBA) { 946 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; 947 hw_res->msr_update = mba_wrmsr_amd; 948 } else if (r->rid == RDT_RESOURCE_SMBA) { 949 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; 950 hw_res->msr_update = mba_wrmsr_amd; 951 } 952 } 953 } 954 955 static __init void rdt_init_res_defs(void) 956 { 957 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 958 rdt_init_res_defs_intel(); 959 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 960 rdt_init_res_defs_amd(); 961 } 962 963 static enum cpuhp_state rdt_online; 964 965 /* Runs once on the BSP during boot. */ 966 void resctrl_cpu_detect(struct cpuinfo_x86 *c) 967 { 968 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 969 c->x86_cache_max_rmid = -1; 970 c->x86_cache_occ_scale = -1; 971 c->x86_cache_mbm_width_offset = -1; 972 return; 973 } 974 975 /* will be overridden if occupancy monitoring exists */ 976 c->x86_cache_max_rmid = cpuid_ebx(0xf); 977 978 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 979 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 980 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 981 u32 eax, ebx, ecx, edx; 982 983 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 984 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 985 986 c->x86_cache_max_rmid = ecx; 987 c->x86_cache_occ_scale = ebx; 988 c->x86_cache_mbm_width_offset = eax & 0xff; 989 990 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset) 991 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; 992 } 993 } 994 995 static int __init resctrl_arch_late_init(void) 996 { 997 struct rdt_resource *r; 998 int state, ret, i; 999 1000 /* for_each_rdt_resource() requires all rid to be initialised. */ 1001 for (i = 0; i < RDT_NUM_RESOURCES; i++) 1002 rdt_resources_all[i].r_resctrl.rid = i; 1003 1004 /* 1005 * Initialize functions(or definitions) that are different 1006 * between vendors here. 1007 */ 1008 rdt_init_res_defs(); 1009 1010 check_quirks(); 1011 1012 if (!get_rdt_resources()) 1013 return -ENODEV; 1014 1015 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 1016 "x86/resctrl/cat:online:", 1017 resctrl_arch_online_cpu, 1018 resctrl_arch_offline_cpu); 1019 if (state < 0) 1020 return state; 1021 1022 ret = resctrl_init(); 1023 if (ret) { 1024 cpuhp_remove_state(state); 1025 return ret; 1026 } 1027 rdt_online = state; 1028 1029 for_each_alloc_capable_rdt_resource(r) 1030 pr_info("%s allocation detected\n", r->name); 1031 1032 for_each_mon_capable_rdt_resource(r) 1033 pr_info("%s monitoring detected\n", r->name); 1034 1035 return 0; 1036 } 1037 1038 late_initcall(resctrl_arch_late_init); 1039 1040 static void __exit resctrl_arch_exit(void) 1041 { 1042 cpuhp_remove_state(rdt_online); 1043 1044 resctrl_exit(); 1045 } 1046 1047 __exitcall(resctrl_arch_exit); 1048