1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Resource Director Technology(RDT) 4 * - Cache Allocation code. 5 * 6 * Copyright (C) 2016 Intel Corporation 7 * 8 * Authors: 9 * Fenghua Yu <fenghua.yu@intel.com> 10 * Tony Luck <tony.luck@intel.com> 11 * Vikas Shivappa <vikas.shivappa@intel.com> 12 * 13 * More information about RDT be found in the Intel (R) x86 Architecture 14 * Software Developer Manual June 2016, volume 3, section 17.17. 15 */ 16 17 #define pr_fmt(fmt) "resctrl: " fmt 18 19 #include <linux/cpu.h> 20 #include <linux/slab.h> 21 #include <linux/err.h> 22 #include <linux/cpuhotplug.h> 23 24 #include <asm/cpu_device_id.h> 25 #include <asm/msr.h> 26 #include <asm/resctrl.h> 27 #include "internal.h" 28 29 /* 30 * rdt_domain structures are kfree()d when their last CPU goes offline, 31 * and allocated when the first CPU in a new domain comes online. 32 * The rdt_resource's domain list is updated when this happens. Readers of 33 * the domain list must either take cpus_read_lock(), or rely on an RCU 34 * read-side critical section, to avoid observing concurrent modification. 35 * All writers take this mutex: 36 */ 37 static DEFINE_MUTEX(domain_list_lock); 38 39 /* 40 * The cached resctrl_pqr_state is strictly per CPU and can never be 41 * updated from a remote CPU. Functions which modify the state 42 * are called with interrupts disabled and no preemption, which 43 * is sufficient for the protection. 44 */ 45 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); 46 47 /* 48 * Global boolean for rdt_alloc which is true if any 49 * resource allocation is enabled. 50 */ 51 bool rdt_alloc_capable; 52 53 static void mba_wrmsr_intel(struct msr_param *m); 54 static void cat_wrmsr(struct msr_param *m); 55 static void mba_wrmsr_amd(struct msr_param *m); 56 57 #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains) 58 #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) 59 60 struct rdt_hw_resource rdt_resources_all[RDT_NUM_RESOURCES] = { 61 [RDT_RESOURCE_L3] = 62 { 63 .r_resctrl = { 64 .name = "L3", 65 .ctrl_scope = RESCTRL_L3_CACHE, 66 .mon_scope = RESCTRL_L3_CACHE, 67 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3), 68 .mon_domains = mon_domain_init(RDT_RESOURCE_L3), 69 .schema_fmt = RESCTRL_SCHEMA_BITMAP, 70 }, 71 .msr_base = MSR_IA32_L3_CBM_BASE, 72 .msr_update = cat_wrmsr, 73 }, 74 [RDT_RESOURCE_L2] = 75 { 76 .r_resctrl = { 77 .name = "L2", 78 .ctrl_scope = RESCTRL_L2_CACHE, 79 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2), 80 .schema_fmt = RESCTRL_SCHEMA_BITMAP, 81 }, 82 .msr_base = MSR_IA32_L2_CBM_BASE, 83 .msr_update = cat_wrmsr, 84 }, 85 [RDT_RESOURCE_MBA] = 86 { 87 .r_resctrl = { 88 .name = "MB", 89 .ctrl_scope = RESCTRL_L3_CACHE, 90 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA), 91 .schema_fmt = RESCTRL_SCHEMA_RANGE, 92 }, 93 }, 94 [RDT_RESOURCE_SMBA] = 95 { 96 .r_resctrl = { 97 .name = "SMBA", 98 .ctrl_scope = RESCTRL_L3_CACHE, 99 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA), 100 .schema_fmt = RESCTRL_SCHEMA_RANGE, 101 }, 102 }, 103 }; 104 105 u32 resctrl_arch_system_num_rmid_idx(void) 106 { 107 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 108 109 /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */ 110 return r->mon.num_rmid; 111 } 112 113 struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) 114 { 115 if (l >= RDT_NUM_RESOURCES) 116 return NULL; 117 118 return &rdt_resources_all[l].r_resctrl; 119 } 120 121 /* 122 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs 123 * as they do not have CPUID enumeration support for Cache allocation. 124 * The check for Vendor/Family/Model is not enough to guarantee that 125 * the MSRs won't #GP fault because only the following SKUs support 126 * CAT: 127 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz 128 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz 129 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz 130 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz 131 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz 132 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz 133 * 134 * Probe by trying to write the first of the L3 cache mask registers 135 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length 136 * is always 20 on hsw server parts. The minimum cache bitmask length 137 * allowed for HSW server is always 2 bits. Hardcode all of them. 138 */ 139 static inline void cache_alloc_hsw_probe(void) 140 { 141 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; 142 struct rdt_resource *r = &hw_res->r_resctrl; 143 u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0; 144 145 if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) 146 return; 147 148 rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0); 149 150 /* If all the bits were set in MSR, return success */ 151 if (l3_cbm_0 != max_cbm) 152 return; 153 154 hw_res->num_closid = 4; 155 r->cache.cbm_len = 20; 156 r->cache.shareable_bits = 0xc0000; 157 r->cache.min_cbm_bits = 2; 158 r->cache.arch_has_sparse_bitmasks = false; 159 r->alloc_capable = true; 160 161 rdt_alloc_capable = true; 162 } 163 164 /* 165 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values 166 * exposed to user interface and the h/w understandable delay values. 167 * 168 * The non-linear delay values have the granularity of power of two 169 * and also the h/w does not guarantee a curve for configured delay 170 * values vs. actual b/w enforced. 171 * Hence we need a mapping that is pre calibrated so the user can 172 * express the memory b/w as a percentage value. 173 */ 174 static inline bool rdt_get_mb_table(struct rdt_resource *r) 175 { 176 /* 177 * There are no Intel SKUs as of now to support non-linear delay. 178 */ 179 pr_info("MBA b/w map not implemented for cpu:%d, model:%d", 180 boot_cpu_data.x86, boot_cpu_data.x86_model); 181 182 return false; 183 } 184 185 static __init bool __get_mem_config_intel(struct rdt_resource *r) 186 { 187 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 188 union cpuid_0x10_3_eax eax; 189 union cpuid_0x10_x_edx edx; 190 u32 ebx, ecx, max_delay; 191 192 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); 193 hw_res->num_closid = edx.split.cos_max + 1; 194 max_delay = eax.split.max_delay + 1; 195 r->membw.max_bw = MAX_MBA_BW; 196 r->membw.arch_needs_linear = true; 197 if (ecx & MBA_IS_LINEAR) { 198 r->membw.delay_linear = true; 199 r->membw.min_bw = MAX_MBA_BW - max_delay; 200 r->membw.bw_gran = MAX_MBA_BW - max_delay; 201 } else { 202 if (!rdt_get_mb_table(r)) 203 return false; 204 r->membw.arch_needs_linear = false; 205 } 206 207 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) 208 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; 209 else 210 r->membw.throttle_mode = THREAD_THROTTLE_MAX; 211 212 r->alloc_capable = true; 213 214 return true; 215 } 216 217 static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r) 218 { 219 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 220 u32 eax, ebx, ecx, edx, subleaf; 221 222 /* 223 * Query CPUID_Fn80000020_EDX_x01 for MBA and 224 * CPUID_Fn80000020_EDX_x02 for SMBA 225 */ 226 subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1; 227 228 cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); 229 hw_res->num_closid = edx + 1; 230 r->membw.max_bw = 1 << eax; 231 232 /* AMD does not use delay */ 233 r->membw.delay_linear = false; 234 r->membw.arch_needs_linear = false; 235 236 /* 237 * AMD does not use memory delay throttle model to control 238 * the allocation like Intel does. 239 */ 240 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; 241 r->membw.min_bw = 0; 242 r->membw.bw_gran = 1; 243 244 r->alloc_capable = true; 245 246 return true; 247 } 248 249 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 250 { 251 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 252 union cpuid_0x10_1_eax eax; 253 union cpuid_0x10_x_ecx ecx; 254 union cpuid_0x10_x_edx edx; 255 u32 ebx, default_ctrl; 256 257 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); 258 hw_res->num_closid = edx.split.cos_max + 1; 259 r->cache.cbm_len = eax.split.cbm_len + 1; 260 default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; 261 r->cache.shareable_bits = ebx & default_ctrl; 262 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 263 r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; 264 r->alloc_capable = true; 265 } 266 267 static void rdt_get_cdp_config(int level) 268 { 269 /* 270 * By default, CDP is disabled. CDP can be enabled by mount parameter 271 * "cdp" during resctrl file system mount time. 272 */ 273 rdt_resources_all[level].cdp_enabled = false; 274 rdt_resources_all[level].r_resctrl.cdp_capable = true; 275 } 276 277 static void rdt_set_io_alloc_capable(struct rdt_resource *r) 278 { 279 r->cache.io_alloc_capable = true; 280 } 281 282 static void rdt_get_cdp_l3_config(void) 283 { 284 rdt_get_cdp_config(RDT_RESOURCE_L3); 285 } 286 287 static void rdt_get_cdp_l2_config(void) 288 { 289 rdt_get_cdp_config(RDT_RESOURCE_L2); 290 } 291 292 static void mba_wrmsr_amd(struct msr_param *m) 293 { 294 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 295 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 296 unsigned int i; 297 298 for (i = m->low; i < m->high; i++) 299 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 300 } 301 302 /* 303 * Map the memory b/w percentage value to delay values 304 * that can be written to QOS_MSRs. 305 * There are currently no SKUs which support non linear delay values. 306 */ 307 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) 308 { 309 if (r->membw.delay_linear) 310 return MAX_MBA_BW - bw; 311 312 pr_warn_once("Non Linear delay-bw map not supported but queried\n"); 313 return MAX_MBA_BW; 314 } 315 316 static void mba_wrmsr_intel(struct msr_param *m) 317 { 318 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 319 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 320 unsigned int i; 321 322 /* Write the delay values for mba. */ 323 for (i = m->low; i < m->high; i++) 324 wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); 325 } 326 327 static void cat_wrmsr(struct msr_param *m) 328 { 329 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 330 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 331 unsigned int i; 332 333 for (i = m->low; i < m->high; i++) 334 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 335 } 336 337 u32 resctrl_arch_get_num_closid(struct rdt_resource *r) 338 { 339 return resctrl_to_arch_res(r)->num_closid; 340 } 341 342 void rdt_ctrl_update(void *arg) 343 { 344 struct rdt_hw_resource *hw_res; 345 struct msr_param *m = arg; 346 347 hw_res = resctrl_to_arch_res(m->res); 348 hw_res->msr_update(m); 349 } 350 351 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc) 352 { 353 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 354 int i; 355 356 /* 357 * Initialize the Control MSRs to having no control. 358 * For Cache Allocation: Set all bits in cbm 359 * For Memory Allocation: Set b/w requested to 100% 360 */ 361 for (i = 0; i < hw_res->num_closid; i++, dc++) 362 *dc = resctrl_get_default_ctrl(r); 363 } 364 365 static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom) 366 { 367 kfree(hw_dom->ctrl_val); 368 kfree(hw_dom); 369 } 370 371 static void mon_domain_free(struct rdt_hw_l3_mon_domain *hw_dom) 372 { 373 int idx; 374 375 for_each_mbm_idx(idx) 376 kfree(hw_dom->arch_mbm_states[idx]); 377 kfree(hw_dom); 378 } 379 380 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d) 381 { 382 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); 383 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 384 struct msr_param m; 385 u32 *dc; 386 387 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), 388 GFP_KERNEL); 389 if (!dc) 390 return -ENOMEM; 391 392 hw_dom->ctrl_val = dc; 393 setup_default_ctrlval(r, dc); 394 395 m.res = r; 396 m.dom = d; 397 m.low = 0; 398 m.high = hw_res->num_closid; 399 hw_res->msr_update(&m); 400 return 0; 401 } 402 403 /** 404 * arch_domain_mbm_alloc() - Allocate arch private storage for the MBM counters 405 * @num_rmid: The size of the MBM counter array 406 * @hw_dom: The domain that owns the allocated arrays 407 */ 408 static int arch_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_l3_mon_domain *hw_dom) 409 { 410 size_t tsize = sizeof(*hw_dom->arch_mbm_states[0]); 411 enum resctrl_event_id eventid; 412 int idx; 413 414 for_each_mbm_event_id(eventid) { 415 if (!resctrl_is_mon_event_enabled(eventid)) 416 continue; 417 idx = MBM_STATE_IDX(eventid); 418 hw_dom->arch_mbm_states[idx] = kcalloc(num_rmid, tsize, GFP_KERNEL); 419 if (!hw_dom->arch_mbm_states[idx]) 420 goto cleanup; 421 } 422 423 return 0; 424 cleanup: 425 for_each_mbm_idx(idx) { 426 kfree(hw_dom->arch_mbm_states[idx]); 427 hw_dom->arch_mbm_states[idx] = NULL; 428 } 429 430 return -ENOMEM; 431 } 432 433 static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope) 434 { 435 switch (scope) { 436 case RESCTRL_L2_CACHE: 437 case RESCTRL_L3_CACHE: 438 return get_cpu_cacheinfo_id(cpu, scope); 439 case RESCTRL_L3_NODE: 440 return cpu_to_node(cpu); 441 default: 442 break; 443 } 444 445 return -EINVAL; 446 } 447 448 static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r) 449 { 450 int id = get_domain_id_from_scope(cpu, r->ctrl_scope); 451 struct rdt_hw_ctrl_domain *hw_dom; 452 struct list_head *add_pos = NULL; 453 struct rdt_domain_hdr *hdr; 454 struct rdt_ctrl_domain *d; 455 int err; 456 457 lockdep_assert_held(&domain_list_lock); 458 459 if (id < 0) { 460 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", 461 cpu, r->ctrl_scope, r->name); 462 return; 463 } 464 465 hdr = resctrl_find_domain(&r->ctrl_domains, id, &add_pos); 466 if (hdr) { 467 if (!domain_header_is_valid(hdr, RESCTRL_CTRL_DOMAIN, r->rid)) 468 return; 469 d = container_of(hdr, struct rdt_ctrl_domain, hdr); 470 471 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 472 if (r->cache.arch_has_per_cpu_cfg) 473 rdt_domain_reconfigure_cdp(r); 474 return; 475 } 476 477 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 478 if (!hw_dom) 479 return; 480 481 d = &hw_dom->d_resctrl; 482 d->hdr.id = id; 483 d->hdr.type = RESCTRL_CTRL_DOMAIN; 484 d->hdr.rid = r->rid; 485 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 486 487 rdt_domain_reconfigure_cdp(r); 488 489 if (domain_setup_ctrlval(r, d)) { 490 ctrl_domain_free(hw_dom); 491 return; 492 } 493 494 list_add_tail_rcu(&d->hdr.list, add_pos); 495 496 err = resctrl_online_ctrl_domain(r, d); 497 if (err) { 498 list_del_rcu(&d->hdr.list); 499 synchronize_rcu(); 500 ctrl_domain_free(hw_dom); 501 } 502 } 503 504 static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, struct list_head *add_pos) 505 { 506 struct rdt_hw_l3_mon_domain *hw_dom; 507 struct rdt_l3_mon_domain *d; 508 struct cacheinfo *ci; 509 int err; 510 511 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 512 if (!hw_dom) 513 return; 514 515 d = &hw_dom->d_resctrl; 516 d->hdr.id = id; 517 d->hdr.type = RESCTRL_MON_DOMAIN; 518 d->hdr.rid = RDT_RESOURCE_L3; 519 ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); 520 if (!ci) { 521 pr_warn_once("Can't find L3 cache for CPU:%d resource %s\n", cpu, r->name); 522 mon_domain_free(hw_dom); 523 return; 524 } 525 d->ci_id = ci->id; 526 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 527 528 arch_mon_domain_online(r, d); 529 530 if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { 531 mon_domain_free(hw_dom); 532 return; 533 } 534 535 list_add_tail_rcu(&d->hdr.list, add_pos); 536 537 err = resctrl_online_mon_domain(r, &d->hdr); 538 if (err) { 539 list_del_rcu(&d->hdr.list); 540 synchronize_rcu(); 541 mon_domain_free(hw_dom); 542 } 543 } 544 545 static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) 546 { 547 int id = get_domain_id_from_scope(cpu, r->mon_scope); 548 struct list_head *add_pos = NULL; 549 struct rdt_domain_hdr *hdr; 550 551 lockdep_assert_held(&domain_list_lock); 552 553 if (id < 0) { 554 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n", 555 cpu, r->mon_scope, r->name); 556 return; 557 } 558 559 hdr = resctrl_find_domain(&r->mon_domains, id, &add_pos); 560 if (hdr) 561 cpumask_set_cpu(cpu, &hdr->cpu_mask); 562 563 switch (r->rid) { 564 case RDT_RESOURCE_L3: 565 /* Update the mbm_assign_mode state for the CPU if supported */ 566 if (r->mon.mbm_cntr_assignable) 567 resctrl_arch_mbm_cntr_assign_set_one(r); 568 if (!hdr) 569 l3_mon_domain_setup(cpu, id, r, add_pos); 570 break; 571 default: 572 pr_warn_once("Unknown resource rid=%d\n", r->rid); 573 break; 574 } 575 } 576 577 static void domain_add_cpu(int cpu, struct rdt_resource *r) 578 { 579 if (r->alloc_capable) 580 domain_add_cpu_ctrl(cpu, r); 581 if (r->mon_capable) 582 domain_add_cpu_mon(cpu, r); 583 } 584 585 static void domain_remove_cpu_ctrl(int cpu, struct rdt_resource *r) 586 { 587 int id = get_domain_id_from_scope(cpu, r->ctrl_scope); 588 struct rdt_hw_ctrl_domain *hw_dom; 589 struct rdt_domain_hdr *hdr; 590 struct rdt_ctrl_domain *d; 591 592 lockdep_assert_held(&domain_list_lock); 593 594 if (id < 0) { 595 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", 596 cpu, r->ctrl_scope, r->name); 597 return; 598 } 599 600 hdr = resctrl_find_domain(&r->ctrl_domains, id, NULL); 601 if (!hdr) { 602 pr_warn("Can't find control domain for id=%d for CPU %d for resource %s\n", 603 id, cpu, r->name); 604 return; 605 } 606 607 cpumask_clear_cpu(cpu, &hdr->cpu_mask); 608 if (!cpumask_empty(&hdr->cpu_mask)) 609 return; 610 611 if (!domain_header_is_valid(hdr, RESCTRL_CTRL_DOMAIN, r->rid)) 612 return; 613 614 d = container_of(hdr, struct rdt_ctrl_domain, hdr); 615 hw_dom = resctrl_to_arch_ctrl_dom(d); 616 617 resctrl_offline_ctrl_domain(r, d); 618 list_del_rcu(&hdr->list); 619 synchronize_rcu(); 620 621 /* 622 * rdt_ctrl_domain "d" is going to be freed below, so clear 623 * its pointer from pseudo_lock_region struct. 624 */ 625 if (d->plr) 626 d->plr->d = NULL; 627 ctrl_domain_free(hw_dom); 628 } 629 630 static void domain_remove_cpu_mon(int cpu, struct rdt_resource *r) 631 { 632 int id = get_domain_id_from_scope(cpu, r->mon_scope); 633 struct rdt_domain_hdr *hdr; 634 635 lockdep_assert_held(&domain_list_lock); 636 637 if (id < 0) { 638 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n", 639 cpu, r->mon_scope, r->name); 640 return; 641 } 642 643 hdr = resctrl_find_domain(&r->mon_domains, id, NULL); 644 if (!hdr) { 645 pr_warn("Can't find monitor domain for id=%d for CPU %d for resource %s\n", 646 id, cpu, r->name); 647 return; 648 } 649 650 cpumask_clear_cpu(cpu, &hdr->cpu_mask); 651 if (!cpumask_empty(&hdr->cpu_mask)) 652 return; 653 654 switch (r->rid) { 655 case RDT_RESOURCE_L3: { 656 struct rdt_hw_l3_mon_domain *hw_dom; 657 struct rdt_l3_mon_domain *d; 658 659 if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)) 660 return; 661 662 d = container_of(hdr, struct rdt_l3_mon_domain, hdr); 663 hw_dom = resctrl_to_arch_mon_dom(d); 664 resctrl_offline_mon_domain(r, hdr); 665 list_del_rcu(&hdr->list); 666 synchronize_rcu(); 667 mon_domain_free(hw_dom); 668 break; 669 } 670 default: 671 pr_warn_once("Unknown resource rid=%d\n", r->rid); 672 break; 673 } 674 } 675 676 static void domain_remove_cpu(int cpu, struct rdt_resource *r) 677 { 678 if (r->alloc_capable) 679 domain_remove_cpu_ctrl(cpu, r); 680 if (r->mon_capable) 681 domain_remove_cpu_mon(cpu, r); 682 } 683 684 static void clear_closid_rmid(int cpu) 685 { 686 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); 687 688 state->default_closid = RESCTRL_RESERVED_CLOSID; 689 state->default_rmid = RESCTRL_RESERVED_RMID; 690 state->cur_closid = RESCTRL_RESERVED_CLOSID; 691 state->cur_rmid = RESCTRL_RESERVED_RMID; 692 wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID, 693 RESCTRL_RESERVED_CLOSID); 694 } 695 696 static int resctrl_arch_online_cpu(unsigned int cpu) 697 { 698 struct rdt_resource *r; 699 700 mutex_lock(&domain_list_lock); 701 for_each_capable_rdt_resource(r) 702 domain_add_cpu(cpu, r); 703 mutex_unlock(&domain_list_lock); 704 705 clear_closid_rmid(cpu); 706 resctrl_online_cpu(cpu); 707 708 return 0; 709 } 710 711 static int resctrl_arch_offline_cpu(unsigned int cpu) 712 { 713 struct rdt_resource *r; 714 715 resctrl_offline_cpu(cpu); 716 717 mutex_lock(&domain_list_lock); 718 for_each_capable_rdt_resource(r) 719 domain_remove_cpu(cpu, r); 720 mutex_unlock(&domain_list_lock); 721 722 clear_closid_rmid(cpu); 723 724 return 0; 725 } 726 727 enum { 728 RDT_FLAG_CMT, 729 RDT_FLAG_MBM_TOTAL, 730 RDT_FLAG_MBM_LOCAL, 731 RDT_FLAG_L3_CAT, 732 RDT_FLAG_L3_CDP, 733 RDT_FLAG_L2_CAT, 734 RDT_FLAG_L2_CDP, 735 RDT_FLAG_MBA, 736 RDT_FLAG_SMBA, 737 RDT_FLAG_BMEC, 738 RDT_FLAG_ABMC, 739 RDT_FLAG_SDCIAE, 740 }; 741 742 #define RDT_OPT(idx, n, f) \ 743 [idx] = { \ 744 .name = n, \ 745 .flag = f \ 746 } 747 748 struct rdt_options { 749 char *name; 750 int flag; 751 bool force_off, force_on; 752 }; 753 754 static struct rdt_options rdt_options[] __ro_after_init = { 755 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), 756 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), 757 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), 758 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), 759 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), 760 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), 761 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), 762 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), 763 RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), 764 RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), 765 RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC), 766 RDT_OPT(RDT_FLAG_SDCIAE, "sdciae", X86_FEATURE_SDCIAE), 767 }; 768 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) 769 770 static int __init set_rdt_options(char *str) 771 { 772 struct rdt_options *o; 773 bool force_off; 774 char *tok; 775 776 if (*str == '=') 777 str++; 778 while ((tok = strsep(&str, ",")) != NULL) { 779 force_off = *tok == '!'; 780 if (force_off) 781 tok++; 782 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 783 if (strcmp(tok, o->name) == 0) { 784 if (force_off) 785 o->force_off = true; 786 else 787 o->force_on = true; 788 break; 789 } 790 } 791 } 792 return 1; 793 } 794 __setup("rdt", set_rdt_options); 795 796 bool rdt_cpu_has(int flag) 797 { 798 bool ret = boot_cpu_has(flag); 799 struct rdt_options *o; 800 801 if (!ret) 802 return ret; 803 804 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 805 if (flag == o->flag) { 806 if (o->force_off) 807 ret = false; 808 if (o->force_on) 809 ret = true; 810 break; 811 } 812 } 813 return ret; 814 } 815 816 bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) 817 { 818 if (!rdt_cpu_has(X86_FEATURE_BMEC)) 819 return false; 820 821 switch (evt) { 822 case QOS_L3_MBM_TOTAL_EVENT_ID: 823 return rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL); 824 case QOS_L3_MBM_LOCAL_EVENT_ID: 825 return rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL); 826 default: 827 return false; 828 } 829 } 830 831 static __init bool get_mem_config(void) 832 { 833 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA]; 834 835 if (!rdt_cpu_has(X86_FEATURE_MBA)) 836 return false; 837 838 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 839 return __get_mem_config_intel(&hw_res->r_resctrl); 840 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 841 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 842 843 return false; 844 } 845 846 static __init bool get_slow_mem_config(void) 847 { 848 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA]; 849 850 if (!rdt_cpu_has(X86_FEATURE_SMBA)) 851 return false; 852 853 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 854 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 855 856 return false; 857 } 858 859 static __init bool get_rdt_alloc_resources(void) 860 { 861 struct rdt_resource *r; 862 bool ret = false; 863 864 if (rdt_alloc_capable) 865 return true; 866 867 if (!boot_cpu_has(X86_FEATURE_RDT_A)) 868 return false; 869 870 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { 871 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 872 rdt_get_cache_alloc_cfg(1, r); 873 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 874 rdt_get_cdp_l3_config(); 875 if (rdt_cpu_has(X86_FEATURE_SDCIAE)) 876 rdt_set_io_alloc_capable(r); 877 ret = true; 878 } 879 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { 880 /* CPUID 0x10.2 fields are same format at 0x10.1 */ 881 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl; 882 rdt_get_cache_alloc_cfg(2, r); 883 if (rdt_cpu_has(X86_FEATURE_CDP_L2)) 884 rdt_get_cdp_l2_config(); 885 ret = true; 886 } 887 888 if (get_mem_config()) 889 ret = true; 890 891 if (get_slow_mem_config()) 892 ret = true; 893 894 return ret; 895 } 896 897 static __init bool get_rdt_mon_resources(void) 898 { 899 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 900 bool ret = false; 901 902 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { 903 resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID); 904 ret = true; 905 } 906 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { 907 resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID); 908 ret = true; 909 } 910 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { 911 resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID); 912 ret = true; 913 } 914 if (rdt_cpu_has(X86_FEATURE_ABMC)) 915 ret = true; 916 917 if (!ret) 918 return false; 919 920 return !rdt_get_mon_l3_config(r); 921 } 922 923 static __init void __check_quirks_intel(void) 924 { 925 switch (boot_cpu_data.x86_vfm) { 926 case INTEL_HASWELL_X: 927 if (!rdt_options[RDT_FLAG_L3_CAT].force_off) 928 cache_alloc_hsw_probe(); 929 break; 930 case INTEL_SKYLAKE_X: 931 if (boot_cpu_data.x86_stepping <= 4) 932 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); 933 else 934 set_rdt_options("!l3cat"); 935 fallthrough; 936 case INTEL_BROADWELL_X: 937 intel_rdt_mbm_apply_quirk(); 938 break; 939 } 940 } 941 942 static __init void check_quirks(void) 943 { 944 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 945 __check_quirks_intel(); 946 } 947 948 static __init bool get_rdt_resources(void) 949 { 950 rdt_alloc_capable = get_rdt_alloc_resources(); 951 rdt_mon_capable = get_rdt_mon_resources(); 952 953 return (rdt_mon_capable || rdt_alloc_capable); 954 } 955 956 static __init void rdt_init_res_defs_intel(void) 957 { 958 struct rdt_hw_resource *hw_res; 959 struct rdt_resource *r; 960 961 for_each_rdt_resource(r) { 962 hw_res = resctrl_to_arch_res(r); 963 964 if (r->rid == RDT_RESOURCE_L3 || 965 r->rid == RDT_RESOURCE_L2) { 966 r->cache.arch_has_per_cpu_cfg = false; 967 r->cache.min_cbm_bits = 1; 968 } else if (r->rid == RDT_RESOURCE_MBA) { 969 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; 970 hw_res->msr_update = mba_wrmsr_intel; 971 } 972 } 973 } 974 975 static __init void rdt_init_res_defs_amd(void) 976 { 977 struct rdt_hw_resource *hw_res; 978 struct rdt_resource *r; 979 980 for_each_rdt_resource(r) { 981 hw_res = resctrl_to_arch_res(r); 982 983 if (r->rid == RDT_RESOURCE_L3 || 984 r->rid == RDT_RESOURCE_L2) { 985 r->cache.arch_has_sparse_bitmasks = true; 986 r->cache.arch_has_per_cpu_cfg = true; 987 r->cache.min_cbm_bits = 0; 988 } else if (r->rid == RDT_RESOURCE_MBA) { 989 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; 990 hw_res->msr_update = mba_wrmsr_amd; 991 } else if (r->rid == RDT_RESOURCE_SMBA) { 992 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; 993 hw_res->msr_update = mba_wrmsr_amd; 994 } 995 } 996 } 997 998 static __init void rdt_init_res_defs(void) 999 { 1000 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1001 rdt_init_res_defs_intel(); 1002 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1003 rdt_init_res_defs_amd(); 1004 } 1005 1006 static enum cpuhp_state rdt_online; 1007 1008 /* Runs once on the BSP during boot. */ 1009 void resctrl_cpu_detect(struct cpuinfo_x86 *c) 1010 { 1011 if (!cpu_has(c, X86_FEATURE_CQM_LLC) && !cpu_has(c, X86_FEATURE_ABMC)) { 1012 c->x86_cache_max_rmid = -1; 1013 c->x86_cache_occ_scale = -1; 1014 c->x86_cache_mbm_width_offset = -1; 1015 return; 1016 } 1017 1018 /* will be overridden if occupancy monitoring exists */ 1019 c->x86_cache_max_rmid = cpuid_ebx(0xf); 1020 1021 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 1022 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 1023 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL) || 1024 cpu_has(c, X86_FEATURE_ABMC)) { 1025 u32 eax, ebx, ecx, edx; 1026 1027 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 1028 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 1029 1030 c->x86_cache_max_rmid = ecx; 1031 c->x86_cache_occ_scale = ebx; 1032 c->x86_cache_mbm_width_offset = eax & 0xff; 1033 1034 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset) 1035 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; 1036 } 1037 } 1038 1039 static int __init resctrl_arch_late_init(void) 1040 { 1041 struct rdt_resource *r; 1042 int state, ret, i; 1043 1044 /* for_each_rdt_resource() requires all rid to be initialised. */ 1045 for (i = 0; i < RDT_NUM_RESOURCES; i++) 1046 rdt_resources_all[i].r_resctrl.rid = i; 1047 1048 /* 1049 * Initialize functions(or definitions) that are different 1050 * between vendors here. 1051 */ 1052 rdt_init_res_defs(); 1053 1054 check_quirks(); 1055 1056 if (!get_rdt_resources()) 1057 return -ENODEV; 1058 1059 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 1060 "x86/resctrl/cat:online:", 1061 resctrl_arch_online_cpu, 1062 resctrl_arch_offline_cpu); 1063 if (state < 0) 1064 return state; 1065 1066 ret = resctrl_init(); 1067 if (ret) { 1068 cpuhp_remove_state(state); 1069 return ret; 1070 } 1071 rdt_online = state; 1072 1073 for_each_alloc_capable_rdt_resource(r) 1074 pr_info("%s allocation detected\n", r->name); 1075 1076 for_each_mon_capable_rdt_resource(r) 1077 pr_info("%s monitoring detected\n", r->name); 1078 1079 return 0; 1080 } 1081 1082 late_initcall(resctrl_arch_late_init); 1083 1084 static void __exit resctrl_arch_exit(void) 1085 { 1086 cpuhp_remove_state(rdt_online); 1087 1088 resctrl_exit(); 1089 } 1090 1091 __exitcall(resctrl_arch_exit); 1092