1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Resource Director Technology(RDT) 4 * - Cache Allocation code. 5 * 6 * Copyright (C) 2016 Intel Corporation 7 * 8 * Authors: 9 * Fenghua Yu <fenghua.yu@intel.com> 10 * Tony Luck <tony.luck@intel.com> 11 * Vikas Shivappa <vikas.shivappa@intel.com> 12 * 13 * More information about RDT be found in the Intel (R) x86 Architecture 14 * Software Developer Manual June 2016, volume 3, section 17.17. 15 */ 16 17 #define pr_fmt(fmt) "resctrl: " fmt 18 19 #include <linux/cpu.h> 20 #include <linux/slab.h> 21 #include <linux/err.h> 22 #include <linux/cpuhotplug.h> 23 24 #include <asm/cpu_device_id.h> 25 #include <asm/msr.h> 26 #include <asm/resctrl.h> 27 #include "internal.h" 28 29 /* 30 * rdt_domain structures are kfree()d when their last CPU goes offline, 31 * and allocated when the first CPU in a new domain comes online. 32 * The rdt_resource's domain list is updated when this happens. Readers of 33 * the domain list must either take cpus_read_lock(), or rely on an RCU 34 * read-side critical section, to avoid observing concurrent modification. 35 * All writers take this mutex: 36 */ 37 static DEFINE_MUTEX(domain_list_lock); 38 39 /* 40 * The cached resctrl_pqr_state is strictly per CPU and can never be 41 * updated from a remote CPU. Functions which modify the state 42 * are called with interrupts disabled and no preemption, which 43 * is sufficient for the protection. 44 */ 45 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); 46 47 /* 48 * Global boolean for rdt_alloc which is true if any 49 * resource allocation is enabled. 50 */ 51 bool rdt_alloc_capable; 52 53 static void mba_wrmsr_intel(struct msr_param *m); 54 static void cat_wrmsr(struct msr_param *m); 55 static void mba_wrmsr_amd(struct msr_param *m); 56 57 #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains) 58 #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) 59 60 struct rdt_hw_resource rdt_resources_all[RDT_NUM_RESOURCES] = { 61 [RDT_RESOURCE_L3] = 62 { 63 .r_resctrl = { 64 .name = "L3", 65 .ctrl_scope = RESCTRL_L3_CACHE, 66 .mon_scope = RESCTRL_L3_CACHE, 67 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3), 68 .mon_domains = mon_domain_init(RDT_RESOURCE_L3), 69 .schema_fmt = RESCTRL_SCHEMA_BITMAP, 70 }, 71 .msr_base = MSR_IA32_L3_CBM_BASE, 72 .msr_update = cat_wrmsr, 73 }, 74 [RDT_RESOURCE_L2] = 75 { 76 .r_resctrl = { 77 .name = "L2", 78 .ctrl_scope = RESCTRL_L2_CACHE, 79 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2), 80 .schema_fmt = RESCTRL_SCHEMA_BITMAP, 81 }, 82 .msr_base = MSR_IA32_L2_CBM_BASE, 83 .msr_update = cat_wrmsr, 84 }, 85 [RDT_RESOURCE_MBA] = 86 { 87 .r_resctrl = { 88 .name = "MB", 89 .ctrl_scope = RESCTRL_L3_CACHE, 90 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA), 91 .schema_fmt = RESCTRL_SCHEMA_RANGE, 92 }, 93 }, 94 [RDT_RESOURCE_SMBA] = 95 { 96 .r_resctrl = { 97 .name = "SMBA", 98 .ctrl_scope = RESCTRL_L3_CACHE, 99 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA), 100 .schema_fmt = RESCTRL_SCHEMA_RANGE, 101 }, 102 }, 103 }; 104 105 u32 resctrl_arch_system_num_rmid_idx(void) 106 { 107 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 108 109 /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */ 110 return r->mon.num_rmid; 111 } 112 113 struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) 114 { 115 if (l >= RDT_NUM_RESOURCES) 116 return NULL; 117 118 return &rdt_resources_all[l].r_resctrl; 119 } 120 121 /* 122 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs 123 * as they do not have CPUID enumeration support for Cache allocation. 124 * The check for Vendor/Family/Model is not enough to guarantee that 125 * the MSRs won't #GP fault because only the following SKUs support 126 * CAT: 127 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz 128 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz 129 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz 130 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz 131 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz 132 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz 133 * 134 * Probe by trying to write the first of the L3 cache mask registers 135 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length 136 * is always 20 on hsw server parts. The minimum cache bitmask length 137 * allowed for HSW server is always 2 bits. Hardcode all of them. 138 */ 139 static inline void cache_alloc_hsw_probe(void) 140 { 141 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; 142 struct rdt_resource *r = &hw_res->r_resctrl; 143 u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0; 144 145 if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) 146 return; 147 148 rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0); 149 150 /* If all the bits were set in MSR, return success */ 151 if (l3_cbm_0 != max_cbm) 152 return; 153 154 hw_res->num_closid = 4; 155 r->cache.cbm_len = 20; 156 r->cache.shareable_bits = 0xc0000; 157 r->cache.min_cbm_bits = 2; 158 r->cache.arch_has_sparse_bitmasks = false; 159 r->alloc_capable = true; 160 161 rdt_alloc_capable = true; 162 } 163 164 /* 165 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values 166 * exposed to user interface and the h/w understandable delay values. 167 * 168 * The non-linear delay values have the granularity of power of two 169 * and also the h/w does not guarantee a curve for configured delay 170 * values vs. actual b/w enforced. 171 * Hence we need a mapping that is pre calibrated so the user can 172 * express the memory b/w as a percentage value. 173 */ 174 static inline bool rdt_get_mb_table(struct rdt_resource *r) 175 { 176 /* 177 * There are no Intel SKUs as of now to support non-linear delay. 178 */ 179 pr_info("MBA b/w map not implemented for cpu:%d, model:%d", 180 boot_cpu_data.x86, boot_cpu_data.x86_model); 181 182 return false; 183 } 184 185 static __init bool __get_mem_config_intel(struct rdt_resource *r) 186 { 187 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 188 union cpuid_0x10_3_eax eax; 189 union cpuid_0x10_x_edx edx; 190 u32 ebx, ecx, max_delay; 191 192 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); 193 hw_res->num_closid = edx.split.cos_max + 1; 194 max_delay = eax.split.max_delay + 1; 195 r->membw.max_bw = MAX_MBA_BW; 196 r->membw.arch_needs_linear = true; 197 if (ecx & MBA_IS_LINEAR) { 198 r->membw.delay_linear = true; 199 r->membw.min_bw = MAX_MBA_BW - max_delay; 200 r->membw.bw_gran = MAX_MBA_BW - max_delay; 201 } else { 202 if (!rdt_get_mb_table(r)) 203 return false; 204 r->membw.arch_needs_linear = false; 205 } 206 207 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) 208 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; 209 else 210 r->membw.throttle_mode = THREAD_THROTTLE_MAX; 211 212 r->alloc_capable = true; 213 214 return true; 215 } 216 217 static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r) 218 { 219 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 220 u32 eax, ebx, ecx, edx, subleaf; 221 222 /* 223 * Query CPUID_Fn80000020_EDX_x01 for MBA and 224 * CPUID_Fn80000020_EDX_x02 for SMBA 225 */ 226 subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1; 227 228 cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); 229 hw_res->num_closid = edx + 1; 230 r->membw.max_bw = 1 << eax; 231 232 /* AMD does not use delay */ 233 r->membw.delay_linear = false; 234 r->membw.arch_needs_linear = false; 235 236 /* 237 * AMD does not use memory delay throttle model to control 238 * the allocation like Intel does. 239 */ 240 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; 241 r->membw.min_bw = 0; 242 r->membw.bw_gran = 1; 243 244 r->alloc_capable = true; 245 246 return true; 247 } 248 249 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 250 { 251 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 252 union cpuid_0x10_1_eax eax; 253 union cpuid_0x10_x_ecx ecx; 254 union cpuid_0x10_x_edx edx; 255 u32 ebx, default_ctrl; 256 257 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); 258 hw_res->num_closid = edx.split.cos_max + 1; 259 r->cache.cbm_len = eax.split.cbm_len + 1; 260 default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; 261 r->cache.shareable_bits = ebx & default_ctrl; 262 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 263 r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; 264 r->alloc_capable = true; 265 } 266 267 static void rdt_get_cdp_config(int level) 268 { 269 /* 270 * By default, CDP is disabled. CDP can be enabled by mount parameter 271 * "cdp" during resctrl file system mount time. 272 */ 273 rdt_resources_all[level].cdp_enabled = false; 274 rdt_resources_all[level].r_resctrl.cdp_capable = true; 275 } 276 277 static void rdt_set_io_alloc_capable(struct rdt_resource *r) 278 { 279 r->cache.io_alloc_capable = true; 280 } 281 282 static void rdt_get_cdp_l3_config(void) 283 { 284 rdt_get_cdp_config(RDT_RESOURCE_L3); 285 } 286 287 static void rdt_get_cdp_l2_config(void) 288 { 289 rdt_get_cdp_config(RDT_RESOURCE_L2); 290 } 291 292 static void mba_wrmsr_amd(struct msr_param *m) 293 { 294 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 295 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 296 unsigned int i; 297 298 for (i = m->low; i < m->high; i++) 299 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 300 } 301 302 /* 303 * Map the memory b/w percentage value to delay values 304 * that can be written to QOS_MSRs. 305 * There are currently no SKUs which support non linear delay values. 306 */ 307 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) 308 { 309 if (r->membw.delay_linear) 310 return MAX_MBA_BW - bw; 311 312 pr_warn_once("Non Linear delay-bw map not supported but queried\n"); 313 return MAX_MBA_BW; 314 } 315 316 static void mba_wrmsr_intel(struct msr_param *m) 317 { 318 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 319 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 320 unsigned int i; 321 322 /* Write the delay values for mba. */ 323 for (i = m->low; i < m->high; i++) 324 wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); 325 } 326 327 static void cat_wrmsr(struct msr_param *m) 328 { 329 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); 330 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 331 unsigned int i; 332 333 for (i = m->low; i < m->high; i++) 334 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 335 } 336 337 u32 resctrl_arch_get_num_closid(struct rdt_resource *r) 338 { 339 return resctrl_to_arch_res(r)->num_closid; 340 } 341 342 void rdt_ctrl_update(void *arg) 343 { 344 struct rdt_hw_resource *hw_res; 345 struct msr_param *m = arg; 346 347 hw_res = resctrl_to_arch_res(m->res); 348 hw_res->msr_update(m); 349 } 350 351 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc) 352 { 353 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 354 int i; 355 356 /* 357 * Initialize the Control MSRs to having no control. 358 * For Cache Allocation: Set all bits in cbm 359 * For Memory Allocation: Set b/w requested to 100% 360 */ 361 for (i = 0; i < hw_res->num_closid; i++, dc++) 362 *dc = resctrl_get_default_ctrl(r); 363 } 364 365 static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom) 366 { 367 kfree(hw_dom->ctrl_val); 368 kfree(hw_dom); 369 } 370 371 static void l3_mon_domain_free(struct rdt_hw_l3_mon_domain *hw_dom) 372 { 373 int idx; 374 375 for_each_mbm_idx(idx) 376 kfree(hw_dom->arch_mbm_states[idx]); 377 kfree(hw_dom); 378 } 379 380 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d) 381 { 382 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); 383 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 384 struct msr_param m; 385 u32 *dc; 386 387 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), 388 GFP_KERNEL); 389 if (!dc) 390 return -ENOMEM; 391 392 hw_dom->ctrl_val = dc; 393 setup_default_ctrlval(r, dc); 394 395 m.res = r; 396 m.dom = d; 397 m.low = 0; 398 m.high = hw_res->num_closid; 399 hw_res->msr_update(&m); 400 return 0; 401 } 402 403 /** 404 * l3_mon_domain_mbm_alloc() - Allocate arch private storage for the MBM counters 405 * @num_rmid: The size of the MBM counter array 406 * @hw_dom: The domain that owns the allocated arrays 407 * 408 * Return: 0 for success, or -ENOMEM. 409 */ 410 static int l3_mon_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_l3_mon_domain *hw_dom) 411 { 412 size_t tsize = sizeof(*hw_dom->arch_mbm_states[0]); 413 enum resctrl_event_id eventid; 414 int idx; 415 416 for_each_mbm_event_id(eventid) { 417 if (!resctrl_is_mon_event_enabled(eventid)) 418 continue; 419 idx = MBM_STATE_IDX(eventid); 420 hw_dom->arch_mbm_states[idx] = kcalloc(num_rmid, tsize, GFP_KERNEL); 421 if (!hw_dom->arch_mbm_states[idx]) 422 goto cleanup; 423 } 424 425 return 0; 426 cleanup: 427 for_each_mbm_idx(idx) { 428 kfree(hw_dom->arch_mbm_states[idx]); 429 hw_dom->arch_mbm_states[idx] = NULL; 430 } 431 432 return -ENOMEM; 433 } 434 435 static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope) 436 { 437 switch (scope) { 438 case RESCTRL_L2_CACHE: 439 case RESCTRL_L3_CACHE: 440 return get_cpu_cacheinfo_id(cpu, scope); 441 case RESCTRL_L3_NODE: 442 return cpu_to_node(cpu); 443 default: 444 break; 445 } 446 447 return -EINVAL; 448 } 449 450 static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r) 451 { 452 int id = get_domain_id_from_scope(cpu, r->ctrl_scope); 453 struct rdt_hw_ctrl_domain *hw_dom; 454 struct list_head *add_pos = NULL; 455 struct rdt_domain_hdr *hdr; 456 struct rdt_ctrl_domain *d; 457 int err; 458 459 lockdep_assert_held(&domain_list_lock); 460 461 if (id < 0) { 462 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", 463 cpu, r->ctrl_scope, r->name); 464 return; 465 } 466 467 hdr = resctrl_find_domain(&r->ctrl_domains, id, &add_pos); 468 if (hdr) { 469 if (!domain_header_is_valid(hdr, RESCTRL_CTRL_DOMAIN, r->rid)) 470 return; 471 d = container_of(hdr, struct rdt_ctrl_domain, hdr); 472 473 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 474 if (r->cache.arch_has_per_cpu_cfg) 475 rdt_domain_reconfigure_cdp(r); 476 return; 477 } 478 479 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 480 if (!hw_dom) 481 return; 482 483 d = &hw_dom->d_resctrl; 484 d->hdr.id = id; 485 d->hdr.type = RESCTRL_CTRL_DOMAIN; 486 d->hdr.rid = r->rid; 487 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 488 489 rdt_domain_reconfigure_cdp(r); 490 491 if (domain_setup_ctrlval(r, d)) { 492 ctrl_domain_free(hw_dom); 493 return; 494 } 495 496 list_add_tail_rcu(&d->hdr.list, add_pos); 497 498 err = resctrl_online_ctrl_domain(r, d); 499 if (err) { 500 list_del_rcu(&d->hdr.list); 501 synchronize_rcu(); 502 ctrl_domain_free(hw_dom); 503 } 504 } 505 506 static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, struct list_head *add_pos) 507 { 508 struct rdt_hw_l3_mon_domain *hw_dom; 509 struct rdt_l3_mon_domain *d; 510 struct cacheinfo *ci; 511 int err; 512 513 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 514 if (!hw_dom) 515 return; 516 517 d = &hw_dom->d_resctrl; 518 d->hdr.id = id; 519 d->hdr.type = RESCTRL_MON_DOMAIN; 520 d->hdr.rid = RDT_RESOURCE_L3; 521 ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); 522 if (!ci) { 523 pr_warn_once("Can't find L3 cache for CPU:%d resource %s\n", cpu, r->name); 524 l3_mon_domain_free(hw_dom); 525 return; 526 } 527 d->ci_id = ci->id; 528 cpumask_set_cpu(cpu, &d->hdr.cpu_mask); 529 530 arch_mon_domain_online(r, d); 531 532 if (l3_mon_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { 533 l3_mon_domain_free(hw_dom); 534 return; 535 } 536 537 list_add_tail_rcu(&d->hdr.list, add_pos); 538 539 err = resctrl_online_mon_domain(r, &d->hdr); 540 if (err) { 541 list_del_rcu(&d->hdr.list); 542 synchronize_rcu(); 543 l3_mon_domain_free(hw_dom); 544 } 545 } 546 547 static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) 548 { 549 int id = get_domain_id_from_scope(cpu, r->mon_scope); 550 struct list_head *add_pos = NULL; 551 struct rdt_domain_hdr *hdr; 552 553 lockdep_assert_held(&domain_list_lock); 554 555 if (id < 0) { 556 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n", 557 cpu, r->mon_scope, r->name); 558 return; 559 } 560 561 hdr = resctrl_find_domain(&r->mon_domains, id, &add_pos); 562 if (hdr) 563 cpumask_set_cpu(cpu, &hdr->cpu_mask); 564 565 switch (r->rid) { 566 case RDT_RESOURCE_L3: 567 /* Update the mbm_assign_mode state for the CPU if supported */ 568 if (r->mon.mbm_cntr_assignable) 569 resctrl_arch_mbm_cntr_assign_set_one(r); 570 if (!hdr) 571 l3_mon_domain_setup(cpu, id, r, add_pos); 572 break; 573 default: 574 pr_warn_once("Unknown resource rid=%d\n", r->rid); 575 break; 576 } 577 } 578 579 static void domain_add_cpu(int cpu, struct rdt_resource *r) 580 { 581 if (r->alloc_capable) 582 domain_add_cpu_ctrl(cpu, r); 583 if (r->mon_capable) 584 domain_add_cpu_mon(cpu, r); 585 } 586 587 static void domain_remove_cpu_ctrl(int cpu, struct rdt_resource *r) 588 { 589 int id = get_domain_id_from_scope(cpu, r->ctrl_scope); 590 struct rdt_hw_ctrl_domain *hw_dom; 591 struct rdt_domain_hdr *hdr; 592 struct rdt_ctrl_domain *d; 593 594 lockdep_assert_held(&domain_list_lock); 595 596 if (id < 0) { 597 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", 598 cpu, r->ctrl_scope, r->name); 599 return; 600 } 601 602 hdr = resctrl_find_domain(&r->ctrl_domains, id, NULL); 603 if (!hdr) { 604 pr_warn("Can't find control domain for id=%d for CPU %d for resource %s\n", 605 id, cpu, r->name); 606 return; 607 } 608 609 cpumask_clear_cpu(cpu, &hdr->cpu_mask); 610 if (!cpumask_empty(&hdr->cpu_mask)) 611 return; 612 613 if (!domain_header_is_valid(hdr, RESCTRL_CTRL_DOMAIN, r->rid)) 614 return; 615 616 d = container_of(hdr, struct rdt_ctrl_domain, hdr); 617 hw_dom = resctrl_to_arch_ctrl_dom(d); 618 619 resctrl_offline_ctrl_domain(r, d); 620 list_del_rcu(&hdr->list); 621 synchronize_rcu(); 622 623 /* 624 * rdt_ctrl_domain "d" is going to be freed below, so clear 625 * its pointer from pseudo_lock_region struct. 626 */ 627 if (d->plr) 628 d->plr->d = NULL; 629 ctrl_domain_free(hw_dom); 630 } 631 632 static void domain_remove_cpu_mon(int cpu, struct rdt_resource *r) 633 { 634 int id = get_domain_id_from_scope(cpu, r->mon_scope); 635 struct rdt_domain_hdr *hdr; 636 637 lockdep_assert_held(&domain_list_lock); 638 639 if (id < 0) { 640 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n", 641 cpu, r->mon_scope, r->name); 642 return; 643 } 644 645 hdr = resctrl_find_domain(&r->mon_domains, id, NULL); 646 if (!hdr) { 647 pr_warn("Can't find monitor domain for id=%d for CPU %d for resource %s\n", 648 id, cpu, r->name); 649 return; 650 } 651 652 cpumask_clear_cpu(cpu, &hdr->cpu_mask); 653 if (!cpumask_empty(&hdr->cpu_mask)) 654 return; 655 656 switch (r->rid) { 657 case RDT_RESOURCE_L3: { 658 struct rdt_hw_l3_mon_domain *hw_dom; 659 struct rdt_l3_mon_domain *d; 660 661 if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)) 662 return; 663 664 d = container_of(hdr, struct rdt_l3_mon_domain, hdr); 665 hw_dom = resctrl_to_arch_mon_dom(d); 666 resctrl_offline_mon_domain(r, hdr); 667 list_del_rcu(&hdr->list); 668 synchronize_rcu(); 669 l3_mon_domain_free(hw_dom); 670 break; 671 } 672 default: 673 pr_warn_once("Unknown resource rid=%d\n", r->rid); 674 break; 675 } 676 } 677 678 static void domain_remove_cpu(int cpu, struct rdt_resource *r) 679 { 680 if (r->alloc_capable) 681 domain_remove_cpu_ctrl(cpu, r); 682 if (r->mon_capable) 683 domain_remove_cpu_mon(cpu, r); 684 } 685 686 static void clear_closid_rmid(int cpu) 687 { 688 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); 689 690 state->default_closid = RESCTRL_RESERVED_CLOSID; 691 state->default_rmid = RESCTRL_RESERVED_RMID; 692 state->cur_closid = RESCTRL_RESERVED_CLOSID; 693 state->cur_rmid = RESCTRL_RESERVED_RMID; 694 wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID, 695 RESCTRL_RESERVED_CLOSID); 696 } 697 698 static int resctrl_arch_online_cpu(unsigned int cpu) 699 { 700 struct rdt_resource *r; 701 702 mutex_lock(&domain_list_lock); 703 for_each_capable_rdt_resource(r) 704 domain_add_cpu(cpu, r); 705 mutex_unlock(&domain_list_lock); 706 707 clear_closid_rmid(cpu); 708 resctrl_online_cpu(cpu); 709 710 return 0; 711 } 712 713 static int resctrl_arch_offline_cpu(unsigned int cpu) 714 { 715 struct rdt_resource *r; 716 717 resctrl_offline_cpu(cpu); 718 719 mutex_lock(&domain_list_lock); 720 for_each_capable_rdt_resource(r) 721 domain_remove_cpu(cpu, r); 722 mutex_unlock(&domain_list_lock); 723 724 clear_closid_rmid(cpu); 725 726 return 0; 727 } 728 729 void resctrl_arch_pre_mount(void) 730 { 731 } 732 733 enum { 734 RDT_FLAG_CMT, 735 RDT_FLAG_MBM_TOTAL, 736 RDT_FLAG_MBM_LOCAL, 737 RDT_FLAG_L3_CAT, 738 RDT_FLAG_L3_CDP, 739 RDT_FLAG_L2_CAT, 740 RDT_FLAG_L2_CDP, 741 RDT_FLAG_MBA, 742 RDT_FLAG_SMBA, 743 RDT_FLAG_BMEC, 744 RDT_FLAG_ABMC, 745 RDT_FLAG_SDCIAE, 746 }; 747 748 #define RDT_OPT(idx, n, f) \ 749 [idx] = { \ 750 .name = n, \ 751 .flag = f \ 752 } 753 754 struct rdt_options { 755 char *name; 756 int flag; 757 bool force_off, force_on; 758 }; 759 760 static struct rdt_options rdt_options[] __ro_after_init = { 761 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), 762 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), 763 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), 764 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), 765 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), 766 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), 767 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), 768 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), 769 RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), 770 RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), 771 RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC), 772 RDT_OPT(RDT_FLAG_SDCIAE, "sdciae", X86_FEATURE_SDCIAE), 773 }; 774 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) 775 776 static int __init set_rdt_options(char *str) 777 { 778 struct rdt_options *o; 779 bool force_off; 780 char *tok; 781 782 if (*str == '=') 783 str++; 784 while ((tok = strsep(&str, ",")) != NULL) { 785 force_off = *tok == '!'; 786 if (force_off) 787 tok++; 788 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 789 if (strcmp(tok, o->name) == 0) { 790 if (force_off) 791 o->force_off = true; 792 else 793 o->force_on = true; 794 break; 795 } 796 } 797 } 798 return 1; 799 } 800 __setup("rdt", set_rdt_options); 801 802 bool rdt_cpu_has(int flag) 803 { 804 bool ret = boot_cpu_has(flag); 805 struct rdt_options *o; 806 807 if (!ret) 808 return ret; 809 810 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 811 if (flag == o->flag) { 812 if (o->force_off) 813 ret = false; 814 if (o->force_on) 815 ret = true; 816 break; 817 } 818 } 819 return ret; 820 } 821 822 bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) 823 { 824 if (!rdt_cpu_has(X86_FEATURE_BMEC)) 825 return false; 826 827 switch (evt) { 828 case QOS_L3_MBM_TOTAL_EVENT_ID: 829 return rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL); 830 case QOS_L3_MBM_LOCAL_EVENT_ID: 831 return rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL); 832 default: 833 return false; 834 } 835 } 836 837 static __init bool get_mem_config(void) 838 { 839 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA]; 840 841 if (!rdt_cpu_has(X86_FEATURE_MBA)) 842 return false; 843 844 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 845 return __get_mem_config_intel(&hw_res->r_resctrl); 846 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 847 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 848 849 return false; 850 } 851 852 static __init bool get_slow_mem_config(void) 853 { 854 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA]; 855 856 if (!rdt_cpu_has(X86_FEATURE_SMBA)) 857 return false; 858 859 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 860 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 861 862 return false; 863 } 864 865 static __init bool get_rdt_alloc_resources(void) 866 { 867 struct rdt_resource *r; 868 bool ret = false; 869 870 if (rdt_alloc_capable) 871 return true; 872 873 if (!boot_cpu_has(X86_FEATURE_RDT_A)) 874 return false; 875 876 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { 877 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 878 rdt_get_cache_alloc_cfg(1, r); 879 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 880 rdt_get_cdp_l3_config(); 881 if (rdt_cpu_has(X86_FEATURE_SDCIAE)) 882 rdt_set_io_alloc_capable(r); 883 ret = true; 884 } 885 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { 886 /* CPUID 0x10.2 fields are same format at 0x10.1 */ 887 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl; 888 rdt_get_cache_alloc_cfg(2, r); 889 if (rdt_cpu_has(X86_FEATURE_CDP_L2)) 890 rdt_get_cdp_l2_config(); 891 ret = true; 892 } 893 894 if (get_mem_config()) 895 ret = true; 896 897 if (get_slow_mem_config()) 898 ret = true; 899 900 return ret; 901 } 902 903 static __init bool get_rdt_mon_resources(void) 904 { 905 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 906 bool ret = false; 907 908 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { 909 resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0); 910 ret = true; 911 } 912 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { 913 resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID, false, 0); 914 ret = true; 915 } 916 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { 917 resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID, false, 0); 918 ret = true; 919 } 920 if (rdt_cpu_has(X86_FEATURE_ABMC)) 921 ret = true; 922 923 if (!ret) 924 return false; 925 926 return !rdt_get_l3_mon_config(r); 927 } 928 929 static __init void __check_quirks_intel(void) 930 { 931 switch (boot_cpu_data.x86_vfm) { 932 case INTEL_HASWELL_X: 933 if (!rdt_options[RDT_FLAG_L3_CAT].force_off) 934 cache_alloc_hsw_probe(); 935 break; 936 case INTEL_SKYLAKE_X: 937 if (boot_cpu_data.x86_stepping <= 4) 938 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); 939 else 940 set_rdt_options("!l3cat"); 941 fallthrough; 942 case INTEL_BROADWELL_X: 943 intel_rdt_mbm_apply_quirk(); 944 break; 945 } 946 } 947 948 static __init void check_quirks(void) 949 { 950 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 951 __check_quirks_intel(); 952 } 953 954 static __init bool get_rdt_resources(void) 955 { 956 rdt_alloc_capable = get_rdt_alloc_resources(); 957 rdt_mon_capable = get_rdt_mon_resources(); 958 959 return (rdt_mon_capable || rdt_alloc_capable); 960 } 961 962 static __init void rdt_init_res_defs_intel(void) 963 { 964 struct rdt_hw_resource *hw_res; 965 struct rdt_resource *r; 966 967 for_each_rdt_resource(r) { 968 hw_res = resctrl_to_arch_res(r); 969 970 if (r->rid == RDT_RESOURCE_L3 || 971 r->rid == RDT_RESOURCE_L2) { 972 r->cache.arch_has_per_cpu_cfg = false; 973 r->cache.min_cbm_bits = 1; 974 } else if (r->rid == RDT_RESOURCE_MBA) { 975 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; 976 hw_res->msr_update = mba_wrmsr_intel; 977 } 978 } 979 } 980 981 static __init void rdt_init_res_defs_amd(void) 982 { 983 struct rdt_hw_resource *hw_res; 984 struct rdt_resource *r; 985 986 for_each_rdt_resource(r) { 987 hw_res = resctrl_to_arch_res(r); 988 989 if (r->rid == RDT_RESOURCE_L3 || 990 r->rid == RDT_RESOURCE_L2) { 991 r->cache.arch_has_sparse_bitmasks = true; 992 r->cache.arch_has_per_cpu_cfg = true; 993 r->cache.min_cbm_bits = 0; 994 } else if (r->rid == RDT_RESOURCE_MBA) { 995 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; 996 hw_res->msr_update = mba_wrmsr_amd; 997 } else if (r->rid == RDT_RESOURCE_SMBA) { 998 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; 999 hw_res->msr_update = mba_wrmsr_amd; 1000 } 1001 } 1002 } 1003 1004 static __init void rdt_init_res_defs(void) 1005 { 1006 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1007 rdt_init_res_defs_intel(); 1008 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1009 rdt_init_res_defs_amd(); 1010 } 1011 1012 static enum cpuhp_state rdt_online; 1013 1014 /* Runs once on the BSP during boot. */ 1015 void resctrl_cpu_detect(struct cpuinfo_x86 *c) 1016 { 1017 if (!cpu_has(c, X86_FEATURE_CQM_LLC) && !cpu_has(c, X86_FEATURE_ABMC)) { 1018 c->x86_cache_max_rmid = -1; 1019 c->x86_cache_occ_scale = -1; 1020 c->x86_cache_mbm_width_offset = -1; 1021 return; 1022 } 1023 1024 /* will be overridden if occupancy monitoring exists */ 1025 c->x86_cache_max_rmid = cpuid_ebx(0xf); 1026 1027 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 1028 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 1029 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL) || 1030 cpu_has(c, X86_FEATURE_ABMC)) { 1031 u32 eax, ebx, ecx, edx; 1032 1033 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 1034 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 1035 1036 c->x86_cache_max_rmid = ecx; 1037 c->x86_cache_occ_scale = ebx; 1038 c->x86_cache_mbm_width_offset = eax & 0xff; 1039 1040 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset) 1041 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; 1042 } 1043 } 1044 1045 static int __init resctrl_arch_late_init(void) 1046 { 1047 struct rdt_resource *r; 1048 int state, ret, i; 1049 1050 /* for_each_rdt_resource() requires all rid to be initialised. */ 1051 for (i = 0; i < RDT_NUM_RESOURCES; i++) 1052 rdt_resources_all[i].r_resctrl.rid = i; 1053 1054 /* 1055 * Initialize functions(or definitions) that are different 1056 * between vendors here. 1057 */ 1058 rdt_init_res_defs(); 1059 1060 check_quirks(); 1061 1062 if (!get_rdt_resources()) 1063 return -ENODEV; 1064 1065 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 1066 "x86/resctrl/cat:online:", 1067 resctrl_arch_online_cpu, 1068 resctrl_arch_offline_cpu); 1069 if (state < 0) 1070 return state; 1071 1072 ret = resctrl_init(); 1073 if (ret) { 1074 cpuhp_remove_state(state); 1075 return ret; 1076 } 1077 rdt_online = state; 1078 1079 for_each_alloc_capable_rdt_resource(r) 1080 pr_info("%s allocation detected\n", r->name); 1081 1082 for_each_mon_capable_rdt_resource(r) 1083 pr_info("%s monitoring detected\n", r->name); 1084 1085 return 0; 1086 } 1087 1088 late_initcall(resctrl_arch_late_init); 1089 1090 static void __exit resctrl_arch_exit(void) 1091 { 1092 cpuhp_remove_state(rdt_online); 1093 1094 resctrl_exit(); 1095 } 1096 1097 __exitcall(resctrl_arch_exit); 1098