1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 4 * because MTRRs can span up to 40 bits (36bits on most modern x86) 5 */ 6 7 #include <linux/export.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/mm.h> 11 #include <linux/cc_platform.h> 12 #include <asm/processor-flags.h> 13 #include <asm/cacheinfo.h> 14 #include <asm/cpufeature.h> 15 #include <asm/hypervisor.h> 16 #include <asm/mshyperv.h> 17 #include <asm/tlbflush.h> 18 #include <asm/mtrr.h> 19 #include <asm/msr.h> 20 #include <asm/memtype.h> 21 22 #include "mtrr.h" 23 24 struct fixed_range_block { 25 int base_msr; /* start address of an MTRR block */ 26 int ranges; /* number of MTRRs in this block */ 27 }; 28 29 static struct fixed_range_block fixed_range_blocks[] = { 30 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 31 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 32 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 33 {} 34 }; 35 36 struct cache_map { 37 u64 start; 38 u64 end; 39 u64 flags; 40 u64 type:8; 41 u64 fixed:1; 42 }; 43 44 bool mtrr_debug; 45 46 static int __init mtrr_param_setup(char *str) 47 { 48 int rc = 0; 49 50 if (!str) 51 return -EINVAL; 52 if (!strcmp(str, "debug")) 53 mtrr_debug = true; 54 else 55 rc = -EINVAL; 56 57 return rc; 58 } 59 early_param("mtrr", mtrr_param_setup); 60 61 /* 62 * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where 63 * no 2 adjacent ranges have the same cache mode (those would be merged). 64 * The number is based on the worst case: 65 * - no two adjacent fixed MTRRs share the same cache mode 66 * - one variable MTRR is spanning a huge area with mode WB 67 * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2 68 * additional ranges each (result like "ababababa...aba" with a = WB, b = UC), 69 * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries 70 * - a TOP_MEM2 area (even with overlapping an UC MTRR can't add 2 range entries 71 * to the possible maximum, as it always starts at 4GB, thus it can't be in 72 * the middle of that MTRR, unless that MTRR starts at 0, which would remove 73 * the initial "a" from the "abababa" pattern above) 74 * The map won't contain ranges with no matching MTRR (those fall back to the 75 * default cache mode). 76 */ 77 #define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) 78 79 static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; 80 static struct cache_map *cache_map __refdata = init_cache_map; 81 static unsigned int cache_map_size = CACHE_MAP_MAX; 82 static unsigned int cache_map_n; 83 static unsigned int cache_map_fixed; 84 85 static unsigned long smp_changes_mask; 86 static int mtrr_state_set; 87 u64 mtrr_tom2; 88 89 struct mtrr_state_type mtrr_state; 90 EXPORT_SYMBOL_GPL(mtrr_state); 91 92 /* Reserved bits in the high portion of the MTRRphysBaseN MSR. */ 93 u32 phys_hi_rsvd; 94 95 /* 96 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 97 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 98 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 99 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 100 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to 101 * 0 for operation." 102 */ 103 static inline void k8_check_syscfg_dram_mod_en(void) 104 { 105 u32 lo, hi; 106 107 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 108 (boot_cpu_data.x86 >= 0x0f))) 109 return; 110 111 rdmsr(MSR_AMD64_SYSCFG, lo, hi); 112 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { 113 pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 114 " not cleared by BIOS, clearing this bit\n", 115 smp_processor_id()); 116 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 117 mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi); 118 } 119 } 120 121 /* Get the size of contiguous MTRR range */ 122 static u64 get_mtrr_size(u64 mask) 123 { 124 u64 size; 125 126 mask |= (u64)phys_hi_rsvd << 32; 127 size = -mask; 128 129 return size; 130 } 131 132 static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) 133 { 134 struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg; 135 136 if (!(mtrr->mask_lo & MTRR_PHYSMASK_V)) 137 return MTRR_TYPE_INVALID; 138 139 *start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); 140 *size = get_mtrr_size((((u64)mtrr->mask_hi) << 32) + 141 (mtrr->mask_lo & PAGE_MASK)); 142 143 return mtrr->base_lo & MTRR_PHYSBASE_TYPE; 144 } 145 146 static u8 get_effective_type(u8 type1, u8 type2) 147 { 148 if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) 149 return MTRR_TYPE_UNCACHABLE; 150 151 if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) || 152 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK)) 153 return MTRR_TYPE_WRTHROUGH; 154 155 if (type1 != type2) 156 return MTRR_TYPE_UNCACHABLE; 157 158 return type1; 159 } 160 161 static void rm_map_entry_at(int idx) 162 { 163 cache_map_n--; 164 if (cache_map_n > idx) { 165 memmove(cache_map + idx, cache_map + idx + 1, 166 sizeof(*cache_map) * (cache_map_n - idx)); 167 } 168 } 169 170 /* 171 * Add an entry into cache_map at a specific index. Merges adjacent entries if 172 * appropriate. Return the number of merges for correcting the scan index 173 * (this is needed as merging will reduce the number of entries, which will 174 * result in skipping entries in future iterations if the scan index isn't 175 * corrected). 176 * Note that the corrected index can never go below -1 (resulting in being 0 in 177 * the next scan iteration), as "2" is returned only if the current index is 178 * larger than zero. 179 */ 180 static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) 181 { 182 bool merge_prev = false, merge_next = false; 183 184 if (start >= end) 185 return 0; 186 187 if (idx > 0) { 188 struct cache_map *prev = cache_map + idx - 1; 189 190 if (!prev->fixed && start == prev->end && type == prev->type) 191 merge_prev = true; 192 } 193 194 if (idx < cache_map_n) { 195 struct cache_map *next = cache_map + idx; 196 197 if (!next->fixed && end == next->start && type == next->type) 198 merge_next = true; 199 } 200 201 if (merge_prev && merge_next) { 202 cache_map[idx - 1].end = cache_map[idx].end; 203 rm_map_entry_at(idx); 204 return 2; 205 } 206 if (merge_prev) { 207 cache_map[idx - 1].end = end; 208 return 1; 209 } 210 if (merge_next) { 211 cache_map[idx].start = start; 212 return 1; 213 } 214 215 /* Sanity check: the array should NEVER be too small! */ 216 if (cache_map_n == cache_map_size) { 217 WARN(1, "MTRR cache mode memory map exhausted!\n"); 218 cache_map_n = cache_map_fixed; 219 return 0; 220 } 221 222 if (cache_map_n > idx) { 223 memmove(cache_map + idx + 1, cache_map + idx, 224 sizeof(*cache_map) * (cache_map_n - idx)); 225 } 226 227 cache_map[idx].start = start; 228 cache_map[idx].end = end; 229 cache_map[idx].type = type; 230 cache_map[idx].fixed = 0; 231 cache_map_n++; 232 233 return 0; 234 } 235 236 /* Clear a part of an entry. Return 1 if start of entry is still valid. */ 237 static int clr_map_range_at(u64 start, u64 end, int idx) 238 { 239 int ret = start != cache_map[idx].start; 240 u64 tmp; 241 242 if (start == cache_map[idx].start && end == cache_map[idx].end) { 243 rm_map_entry_at(idx); 244 } else if (start == cache_map[idx].start) { 245 cache_map[idx].start = end; 246 } else if (end == cache_map[idx].end) { 247 cache_map[idx].end = start; 248 } else { 249 tmp = cache_map[idx].end; 250 cache_map[idx].end = start; 251 add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); 252 } 253 254 return ret; 255 } 256 257 /* 258 * Add MTRR to the map. The current map is scanned and each part of the MTRR 259 * either overlapping with an existing entry or with a hole in the map is 260 * handled separately. 261 */ 262 static void add_map_entry(u64 start, u64 end, u8 type) 263 { 264 u8 new_type, old_type; 265 u64 tmp; 266 int i; 267 268 for (i = 0; i < cache_map_n && start < end; i++) { 269 if (start >= cache_map[i].end) 270 continue; 271 272 if (start < cache_map[i].start) { 273 /* Region start has no overlap. */ 274 tmp = min(end, cache_map[i].start); 275 i -= add_map_entry_at(start, tmp, type, i); 276 start = tmp; 277 continue; 278 } 279 280 new_type = get_effective_type(type, cache_map[i].type); 281 old_type = cache_map[i].type; 282 283 if (cache_map[i].fixed || new_type == old_type) { 284 /* Cut off start of new entry. */ 285 start = cache_map[i].end; 286 continue; 287 } 288 289 /* Handle only overlapping part of region. */ 290 tmp = min(end, cache_map[i].end); 291 i += clr_map_range_at(start, tmp, i); 292 i -= add_map_entry_at(start, tmp, new_type, i); 293 start = tmp; 294 } 295 296 /* Add rest of region after last map entry (rest might be empty). */ 297 add_map_entry_at(start, end, type, i); 298 } 299 300 /* Add variable MTRRs to cache map. */ 301 static void map_add_var(void) 302 { 303 u64 start, size; 304 unsigned int i; 305 u8 type; 306 307 /* 308 * Add AMD TOP_MEM2 area. Can't be added in mtrr_build_map(), as it 309 * needs to be added again when rebuilding the map due to potentially 310 * having moved as a result of variable MTRRs for memory below 4GB. 311 */ 312 if (mtrr_tom2) { 313 add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK); 314 cache_map[cache_map_n - 1].fixed = 1; 315 } 316 317 for (i = 0; i < num_var_ranges; i++) { 318 type = get_var_mtrr_state(i, &start, &size); 319 if (type != MTRR_TYPE_INVALID) 320 add_map_entry(start, start + size, type); 321 } 322 } 323 324 /* 325 * Rebuild map by replacing variable entries. Needs to be called when MTRR 326 * registers are being changed after boot, as such changes could include 327 * removals of registers, which are complicated to handle without rebuild of 328 * the map. 329 */ 330 void generic_rebuild_map(void) 331 { 332 if (mtrr_if != &generic_mtrr_ops) 333 return; 334 335 cache_map_n = cache_map_fixed; 336 337 map_add_var(); 338 } 339 340 static unsigned int __init get_cache_map_size(void) 341 { 342 return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0); 343 } 344 345 /* Build the cache_map containing the cache modes per memory range. */ 346 void __init mtrr_build_map(void) 347 { 348 u64 start, end, size; 349 unsigned int i; 350 u8 type; 351 352 /* Add fixed MTRRs, optimize for adjacent entries with same type. */ 353 if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { 354 /* 355 * Start with 64k size fixed entries, preset 1st one (hence the 356 * loop below is starting with index 1). 357 */ 358 start = 0; 359 end = size = 0x10000; 360 type = mtrr_state.fixed_ranges[0]; 361 362 for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) { 363 /* 8 64k entries, then 16 16k ones, rest 4k. */ 364 if (i == 8 || i == 24) 365 size >>= 2; 366 367 if (mtrr_state.fixed_ranges[i] != type) { 368 add_map_entry(start, end, type); 369 start = end; 370 type = mtrr_state.fixed_ranges[i]; 371 } 372 end += size; 373 } 374 add_map_entry(start, end, type); 375 } 376 377 /* Mark fixed, they take precedence. */ 378 for (i = 0; i < cache_map_n; i++) 379 cache_map[i].fixed = 1; 380 cache_map_fixed = cache_map_n; 381 382 map_add_var(); 383 384 pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n", 385 cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, 386 get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0)); 387 388 if (mtrr_debug) { 389 for (i = 0; i < cache_map_n; i++) { 390 pr_info("%3u: %016llx-%016llx %s\n", i, 391 cache_map[i].start, cache_map[i].end - 1, 392 mtrr_attrib_to_str(cache_map[i].type)); 393 } 394 } 395 } 396 397 /* Copy the cache_map from __initdata memory to dynamically allocated one. */ 398 void __init mtrr_copy_map(void) 399 { 400 unsigned int new_size = get_cache_map_size(); 401 402 if (!mtrr_state.enabled || !new_size) { 403 cache_map = NULL; 404 return; 405 } 406 407 mutex_lock(&mtrr_mutex); 408 409 cache_map = kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL); 410 if (cache_map) { 411 memmove(cache_map, init_cache_map, 412 cache_map_n * sizeof(*cache_map)); 413 cache_map_size = new_size; 414 } else { 415 mtrr_state.enabled = 0; 416 pr_err("MTRRs disabled due to allocation failure for lookup map.\n"); 417 } 418 419 mutex_unlock(&mtrr_mutex); 420 } 421 422 /** 423 * mtrr_overwrite_state - set static MTRR state 424 * 425 * Used to set MTRR state via different means (e.g. with data obtained from 426 * a hypervisor). 427 * Is allowed only for special cases when running virtualized. Must be called 428 * from the x86_init.hyper.init_platform() hook. It can be called only once. 429 * The MTRR state can't be changed afterwards. To ensure that, X86_FEATURE_MTRR 430 * is cleared. 431 */ 432 void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, 433 mtrr_type def_type) 434 { 435 unsigned int i; 436 437 /* Only allowed to be called once before mtrr_bp_init(). */ 438 if (WARN_ON_ONCE(mtrr_state_set)) 439 return; 440 441 /* Only allowed when running virtualized. */ 442 if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 443 return; 444 445 /* 446 * Only allowed for special virtualization cases: 447 * - when running as Hyper-V, SEV-SNP guest using vTOM 448 * - when running as Xen PV guest 449 * - when running as SEV-SNP or TDX guest to avoid unnecessary 450 * VMM communication/Virtualization exceptions (#VC, #VE) 451 */ 452 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && 453 !hv_is_isolation_supported() && 454 !cpu_feature_enabled(X86_FEATURE_XENPV) && 455 !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) 456 return; 457 458 /* Disable MTRR in order to disable MTRR modifications. */ 459 setup_clear_cpu_cap(X86_FEATURE_MTRR); 460 461 if (var) { 462 if (num_var > MTRR_MAX_VAR_RANGES) { 463 pr_warn("Trying to overwrite MTRR state with %u variable entries\n", 464 num_var); 465 num_var = MTRR_MAX_VAR_RANGES; 466 } 467 for (i = 0; i < num_var; i++) 468 mtrr_state.var_ranges[i] = var[i]; 469 num_var_ranges = num_var; 470 } 471 472 mtrr_state.def_type = def_type; 473 mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED; 474 475 mtrr_state_set = 1; 476 } 477 478 static u8 type_merge(u8 type, u8 new_type, u8 *uniform) 479 { 480 u8 effective_type; 481 482 if (type == MTRR_TYPE_INVALID) 483 return new_type; 484 485 effective_type = get_effective_type(type, new_type); 486 if (type != effective_type) 487 *uniform = 0; 488 489 return effective_type; 490 } 491 492 /** 493 * mtrr_type_lookup - look up memory type in MTRR 494 * 495 * Return Values: 496 * MTRR_TYPE_(type) - The effective MTRR type for the region 497 * MTRR_TYPE_INVALID - MTRR is disabled 498 * 499 * Output Argument: 500 * uniform - Set to 1 when the returned MTRR type is valid for the whole 501 * region, set to 0 else. 502 */ 503 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 504 { 505 u8 type = MTRR_TYPE_INVALID; 506 unsigned int i; 507 508 if (!mtrr_state_set) { 509 /* Uniformity is unknown. */ 510 *uniform = 0; 511 return MTRR_TYPE_UNCACHABLE; 512 } 513 514 *uniform = 1; 515 516 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) 517 return MTRR_TYPE_UNCACHABLE; 518 519 for (i = 0; i < cache_map_n && start < end; i++) { 520 /* Region after current map entry? -> continue with next one. */ 521 if (start >= cache_map[i].end) 522 continue; 523 524 /* Start of region not covered by current map entry? */ 525 if (start < cache_map[i].start) { 526 /* At least some part of region has default type. */ 527 type = type_merge(type, mtrr_state.def_type, uniform); 528 /* End of region not covered, too? -> lookup done. */ 529 if (end <= cache_map[i].start) 530 return type; 531 } 532 533 /* At least part of region covered by map entry. */ 534 type = type_merge(type, cache_map[i].type, uniform); 535 536 start = cache_map[i].end; 537 } 538 539 /* End of region past last entry in map? -> use default type. */ 540 if (start < end) 541 type = type_merge(type, mtrr_state.def_type, uniform); 542 543 return type; 544 } 545 546 /* Get the MSR pair relating to a var range */ 547 static void 548 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 549 { 550 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 551 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 552 } 553 554 /* Fill the MSR pair relating to a var range */ 555 void fill_mtrr_var_range(unsigned int index, 556 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 557 { 558 struct mtrr_var_range *vr; 559 560 vr = mtrr_state.var_ranges; 561 562 vr[index].base_lo = base_lo; 563 vr[index].base_hi = base_hi; 564 vr[index].mask_lo = mask_lo; 565 vr[index].mask_hi = mask_hi; 566 } 567 568 static void get_fixed_ranges(mtrr_type *frs) 569 { 570 unsigned int *p = (unsigned int *)frs; 571 int i; 572 573 k8_check_syscfg_dram_mod_en(); 574 575 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); 576 577 for (i = 0; i < 2; i++) 578 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); 579 for (i = 0; i < 8; i++) 580 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); 581 } 582 583 void mtrr_save_fixed_ranges(void *info) 584 { 585 if (boot_cpu_has(X86_FEATURE_MTRR)) 586 get_fixed_ranges(mtrr_state.fixed_ranges); 587 } 588 589 static unsigned __initdata last_fixed_start; 590 static unsigned __initdata last_fixed_end; 591 static mtrr_type __initdata last_fixed_type; 592 593 static void __init print_fixed_last(void) 594 { 595 if (!last_fixed_end) 596 return; 597 598 pr_info(" %05X-%05X %s\n", last_fixed_start, 599 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 600 601 last_fixed_end = 0; 602 } 603 604 static void __init update_fixed_last(unsigned base, unsigned end, 605 mtrr_type type) 606 { 607 last_fixed_start = base; 608 last_fixed_end = end; 609 last_fixed_type = type; 610 } 611 612 static void __init 613 print_fixed(unsigned base, unsigned step, const mtrr_type *types) 614 { 615 unsigned i; 616 617 for (i = 0; i < 8; ++i, ++types, base += step) { 618 if (last_fixed_end == 0) { 619 update_fixed_last(base, base + step, *types); 620 continue; 621 } 622 if (last_fixed_end == base && last_fixed_type == *types) { 623 last_fixed_end = base + step; 624 continue; 625 } 626 /* new segments: gap or different type */ 627 print_fixed_last(); 628 update_fixed_last(base, base + step, *types); 629 } 630 } 631 632 static void __init print_mtrr_state(void) 633 { 634 unsigned int i; 635 int high_width; 636 637 pr_info("MTRR default type: %s\n", 638 mtrr_attrib_to_str(mtrr_state.def_type)); 639 if (mtrr_state.have_fixed) { 640 pr_info("MTRR fixed ranges %sabled:\n", 641 ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && 642 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? 643 "en" : "dis"); 644 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 645 for (i = 0; i < 2; ++i) 646 print_fixed(0x80000 + i * 0x20000, 0x04000, 647 mtrr_state.fixed_ranges + (i + 1) * 8); 648 for (i = 0; i < 8; ++i) 649 print_fixed(0xC0000 + i * 0x08000, 0x01000, 650 mtrr_state.fixed_ranges + (i + 3) * 8); 651 652 /* tail */ 653 print_fixed_last(); 654 } 655 pr_info("MTRR variable ranges %sabled:\n", 656 mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); 657 high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; 658 659 for (i = 0; i < num_var_ranges; ++i) { 660 if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) 661 pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 662 i, 663 high_width, 664 mtrr_state.var_ranges[i].base_hi, 665 mtrr_state.var_ranges[i].base_lo >> 12, 666 high_width, 667 mtrr_state.var_ranges[i].mask_hi, 668 mtrr_state.var_ranges[i].mask_lo >> 12, 669 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 670 MTRR_PHYSBASE_TYPE)); 671 else 672 pr_info(" %u disabled\n", i); 673 } 674 if (mtrr_tom2) 675 pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 676 } 677 678 /* Grab all of the MTRR state for this CPU into *state */ 679 bool __init get_mtrr_state(void) 680 { 681 struct mtrr_var_range *vrs; 682 unsigned lo, dummy; 683 unsigned int i; 684 685 vrs = mtrr_state.var_ranges; 686 687 rdmsr(MSR_MTRRcap, lo, dummy); 688 mtrr_state.have_fixed = lo & MTRR_CAP_FIX; 689 690 for (i = 0; i < num_var_ranges; i++) 691 get_mtrr_var_range(i, &vrs[i]); 692 if (mtrr_state.have_fixed) 693 get_fixed_ranges(mtrr_state.fixed_ranges); 694 695 rdmsr(MSR_MTRRdefType, lo, dummy); 696 mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE; 697 mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT; 698 699 if (amd_special_default_mtrr()) { 700 unsigned low, high; 701 702 /* TOP_MEM2 */ 703 rdmsr(MSR_K8_TOP_MEM2, low, high); 704 mtrr_tom2 = high; 705 mtrr_tom2 <<= 32; 706 mtrr_tom2 |= low; 707 mtrr_tom2 &= 0xffffff800000ULL; 708 } 709 710 if (mtrr_debug) 711 print_mtrr_state(); 712 713 mtrr_state_set = 1; 714 715 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED); 716 } 717 718 /* Some BIOS's are messed up and don't set all MTRRs the same! */ 719 void __init mtrr_state_warn(void) 720 { 721 unsigned long mask = smp_changes_mask; 722 723 if (!mask) 724 return; 725 if (mask & MTRR_CHANGE_MASK_FIXED) 726 pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 727 if (mask & MTRR_CHANGE_MASK_VARIABLE) 728 pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 729 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 730 pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 731 732 pr_info("mtrr: probably your BIOS does not setup all CPUs.\n"); 733 pr_info("mtrr: corrected configuration.\n"); 734 } 735 736 /* 737 * Doesn't attempt to pass an error out to MTRR users 738 * because it's quite complicated in some cases and probably not 739 * worth it because the best error handling is to ignore it. 740 */ 741 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 742 { 743 if (wrmsr_safe(msr, a, b) < 0) { 744 pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 745 smp_processor_id(), msr, a, b); 746 } 747 } 748 749 /** 750 * set_fixed_range - checks & updates a fixed-range MTRR if it 751 * differs from the value it should have 752 * @msr: MSR address of the MTTR which should be checked and updated 753 * @changed: pointer which indicates whether the MTRR needed to be changed 754 * @msrwords: pointer to the MSR values which the MSR should have 755 */ 756 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 757 { 758 unsigned lo, hi; 759 760 rdmsr(msr, lo, hi); 761 762 if (lo != msrwords[0] || hi != msrwords[1]) { 763 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 764 *changed = true; 765 } 766 } 767 768 /** 769 * generic_get_free_region - Get a free MTRR. 770 * @base: The starting (base) address of the region. 771 * @size: The size (in bytes) of the region. 772 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 773 * 774 * Returns: The index of the region on success, else negative on error. 775 */ 776 int 777 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 778 { 779 unsigned long lbase, lsize; 780 mtrr_type ltype; 781 int i, max; 782 783 max = num_var_ranges; 784 if (replace_reg >= 0 && replace_reg < max) 785 return replace_reg; 786 787 for (i = 0; i < max; ++i) { 788 mtrr_if->get(i, &lbase, &lsize, <ype); 789 if (lsize == 0) 790 return i; 791 } 792 793 return -ENOSPC; 794 } 795 796 static void generic_get_mtrr(unsigned int reg, unsigned long *base, 797 unsigned long *size, mtrr_type *type) 798 { 799 u32 mask_lo, mask_hi, base_lo, base_hi; 800 unsigned int hi; 801 u64 tmp, mask; 802 803 /* 804 * get_mtrr doesn't need to update mtrr_state, also it could be called 805 * from any cpu, so try to print it out directly. 806 */ 807 get_cpu(); 808 809 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); 810 811 if (!(mask_lo & MTRR_PHYSMASK_V)) { 812 /* Invalid (i.e. free) range */ 813 *base = 0; 814 *size = 0; 815 *type = 0; 816 goto out_put_cpu; 817 } 818 819 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); 820 821 /* Work out the shifted address mask: */ 822 tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK); 823 mask = (u64)phys_hi_rsvd << 32 | tmp; 824 825 /* Expand tmp with high bits to all 1s: */ 826 hi = fls64(tmp); 827 if (hi > 0) { 828 tmp |= ~((1ULL<<(hi - 1)) - 1); 829 830 if (tmp != mask) { 831 pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 832 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 833 mask = tmp; 834 } 835 } 836 837 /* 838 * This works correctly if size is a power of two, i.e. a 839 * contiguous range: 840 */ 841 *size = -mask >> PAGE_SHIFT; 842 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; 843 *type = base_lo & MTRR_PHYSBASE_TYPE; 844 845 out_put_cpu: 846 put_cpu(); 847 } 848 849 /** 850 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 851 * differ from the saved set 852 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 853 */ 854 static int set_fixed_ranges(mtrr_type *frs) 855 { 856 unsigned long long *saved = (unsigned long long *)frs; 857 bool changed = false; 858 int block = -1, range; 859 860 k8_check_syscfg_dram_mod_en(); 861 862 while (fixed_range_blocks[++block].ranges) { 863 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 864 set_fixed_range(fixed_range_blocks[block].base_msr + range, 865 &changed, (unsigned int *)saved++); 866 } 867 868 return changed; 869 } 870 871 /* 872 * Set the MSR pair relating to a var range. 873 * Returns true if changes are made. 874 */ 875 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 876 { 877 unsigned int lo, hi; 878 bool changed = false; 879 880 rdmsr(MTRRphysBase_MSR(index), lo, hi); 881 if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (lo & ~MTRR_PHYSBASE_RSVD) 882 || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { 883 884 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 885 changed = true; 886 } 887 888 rdmsr(MTRRphysMask_MSR(index), lo, hi); 889 890 if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (lo & ~MTRR_PHYSMASK_RSVD) 891 || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { 892 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 893 changed = true; 894 } 895 return changed; 896 } 897 898 static u32 deftype_lo, deftype_hi; 899 900 /** 901 * set_mtrr_state - Set the MTRR state for this CPU. 902 * 903 * NOTE: The CPU must already be in a safe state for MTRR changes, including 904 * measures that only a single CPU can be active in set_mtrr_state() in 905 * order to not be subject to races for usage of deftype_lo. This is 906 * accomplished by taking cache_disable_lock. 907 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 908 */ 909 static unsigned long set_mtrr_state(void) 910 { 911 unsigned long change_mask = 0; 912 unsigned int i; 913 914 for (i = 0; i < num_var_ranges; i++) { 915 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 916 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 917 } 918 919 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 920 change_mask |= MTRR_CHANGE_MASK_FIXED; 921 922 /* 923 * Set_mtrr_restore restores the old value of MTRRdefType, 924 * so to set it we fiddle with the saved value: 925 */ 926 if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type || 927 ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != mtrr_state.enabled) { 928 929 deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) | 930 mtrr_state.def_type | 931 (mtrr_state.enabled << MTRR_STATE_SHIFT); 932 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 933 } 934 935 return change_mask; 936 } 937 938 void mtrr_disable(void) 939 { 940 /* Save MTRR state */ 941 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 942 943 /* Disable MTRRs, and set the default type to uncached */ 944 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_hi); 945 } 946 947 void mtrr_enable(void) 948 { 949 /* Intel (P6) standard MTRRs */ 950 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 951 } 952 953 void mtrr_generic_set_state(void) 954 { 955 unsigned long mask, count; 956 957 /* Actually set the state */ 958 mask = set_mtrr_state(); 959 960 /* Use the atomic bitops to update the global mask */ 961 for (count = 0; count < sizeof(mask) * 8; ++count) { 962 if (mask & 0x01) 963 set_bit(count, &smp_changes_mask); 964 mask >>= 1; 965 } 966 } 967 968 /** 969 * generic_set_mtrr - set variable MTRR register on the local CPU. 970 * 971 * @reg: The register to set. 972 * @base: The base address of the region. 973 * @size: The size of the region. If this is 0 the region is disabled. 974 * @type: The type of the region. 975 * 976 * Returns nothing. 977 */ 978 static void generic_set_mtrr(unsigned int reg, unsigned long base, 979 unsigned long size, mtrr_type type) 980 { 981 unsigned long flags; 982 struct mtrr_var_range *vr; 983 984 vr = &mtrr_state.var_ranges[reg]; 985 986 local_irq_save(flags); 987 cache_disable(); 988 989 if (size == 0) { 990 /* 991 * The invalid bit is kept in the mask, so we simply 992 * clear the relevant mask register to disable a range. 993 */ 994 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 995 memset(vr, 0, sizeof(struct mtrr_var_range)); 996 } else { 997 vr->base_lo = base << PAGE_SHIFT | type; 998 vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 999 vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V; 1000 vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 1001 1002 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 1003 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 1004 } 1005 1006 cache_enable(); 1007 local_irq_restore(flags); 1008 } 1009 1010 int generic_validate_add_page(unsigned long base, unsigned long size, 1011 unsigned int type) 1012 { 1013 unsigned long lbase, last; 1014 1015 /* 1016 * For Intel PPro stepping <= 7 1017 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 1018 */ 1019 if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86 == 6 && 1020 boot_cpu_data.x86_model == 1 && 1021 boot_cpu_data.x86_stepping <= 7) { 1022 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 1023 pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 1024 return -EINVAL; 1025 } 1026 if (!(base + size < 0x70000 || base > 0x7003F) && 1027 (type == MTRR_TYPE_WRCOMB 1028 || type == MTRR_TYPE_WRBACK)) { 1029 pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 1030 return -EINVAL; 1031 } 1032 } 1033 1034 /* 1035 * Check upper bits of base and last are equal and lower bits are 0 1036 * for base and 1 for last 1037 */ 1038 last = base + size - 1; 1039 for (lbase = base; !(lbase & 1) && (last & 1); 1040 lbase = lbase >> 1, last = last >> 1) 1041 ; 1042 if (lbase != last) { 1043 pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 1044 return -EINVAL; 1045 } 1046 return 0; 1047 } 1048 1049 static int generic_have_wrcomb(void) 1050 { 1051 unsigned long config, dummy; 1052 rdmsr(MSR_MTRRcap, config, dummy); 1053 return config & MTRR_CAP_WC; 1054 } 1055 1056 int positive_have_wrcomb(void) 1057 { 1058 return 1; 1059 } 1060 1061 /* 1062 * Generic structure... 1063 */ 1064 const struct mtrr_ops generic_mtrr_ops = { 1065 .get = generic_get_mtrr, 1066 .get_free_region = generic_get_free_region, 1067 .set = generic_set_mtrr, 1068 .validate_add_page = generic_validate_add_page, 1069 .have_wrcomb = generic_have_wrcomb, 1070 }; 1071