1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 4 * because MTRRs can span up to 40 bits (36bits on most modern x86) 5 */ 6 7 #include <linux/export.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/mm.h> 11 #include <linux/cc_platform.h> 12 #include <linux/string_choices.h> 13 #include <asm/processor-flags.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpufeature.h> 16 #include <asm/cpu_device_id.h> 17 #include <asm/hypervisor.h> 18 #include <asm/mshyperv.h> 19 #include <asm/tlbflush.h> 20 #include <asm/mtrr.h> 21 #include <asm/msr.h> 22 #include <asm/memtype.h> 23 24 #include "mtrr.h" 25 26 struct fixed_range_block { 27 int base_msr; /* start address of an MTRR block */ 28 int ranges; /* number of MTRRs in this block */ 29 }; 30 31 static struct fixed_range_block fixed_range_blocks[] = { 32 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 33 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 34 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 35 {} 36 }; 37 38 struct cache_map { 39 u64 start; 40 u64 end; 41 u64 flags; 42 u64 type:8; 43 u64 fixed:1; 44 }; 45 46 bool mtrr_debug; 47 48 static int __init mtrr_param_setup(char *str) 49 { 50 int rc = 0; 51 52 if (!str) 53 return -EINVAL; 54 if (!strcmp(str, "debug")) 55 mtrr_debug = true; 56 else 57 rc = -EINVAL; 58 59 return rc; 60 } 61 early_param("mtrr", mtrr_param_setup); 62 63 /* 64 * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where 65 * no 2 adjacent ranges have the same cache mode (those would be merged). 66 * The number is based on the worst case: 67 * - no two adjacent fixed MTRRs share the same cache mode 68 * - one variable MTRR is spanning a huge area with mode WB 69 * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2 70 * additional ranges each (result like "ababababa...aba" with a = WB, b = UC), 71 * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries 72 * - a TOP_MEM2 area (even with overlapping an UC MTRR can't add 2 range entries 73 * to the possible maximum, as it always starts at 4GB, thus it can't be in 74 * the middle of that MTRR, unless that MTRR starts at 0, which would remove 75 * the initial "a" from the "abababa" pattern above) 76 * The map won't contain ranges with no matching MTRR (those fall back to the 77 * default cache mode). 78 */ 79 #define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) 80 81 static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; 82 static struct cache_map *cache_map __refdata = init_cache_map; 83 static unsigned int cache_map_size = CACHE_MAP_MAX; 84 static unsigned int cache_map_n; 85 static unsigned int cache_map_fixed; 86 87 static unsigned long smp_changes_mask; 88 static int mtrr_state_set; 89 u64 mtrr_tom2; 90 91 struct mtrr_state_type mtrr_state; 92 93 /* Reserved bits in the high portion of the MTRRphysBaseN MSR. */ 94 u32 phys_hi_rsvd; 95 96 /* 97 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 98 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 99 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 100 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 101 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to 102 * 0 for operation." 103 */ 104 static inline void k8_check_syscfg_dram_mod_en(void) 105 { 106 struct msr val; 107 108 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 109 (boot_cpu_data.x86 >= 0x0f))) 110 return; 111 112 if (cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 113 return; 114 115 rdmsrq(MSR_AMD64_SYSCFG, val.q); 116 if (val.l & K8_MTRRFIXRANGE_DRAM_MODIFY) { 117 pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 118 " not cleared by BIOS, clearing this bit\n", 119 smp_processor_id()); 120 val.l &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 121 mtrr_wrmsr(MSR_AMD64_SYSCFG, val.l, val.h); 122 } 123 } 124 125 /* Get the size of contiguous MTRR range */ 126 static u64 get_mtrr_size(u64 mask) 127 { 128 u64 size; 129 130 mask |= (u64)phys_hi_rsvd << 32; 131 size = -mask; 132 133 return size; 134 } 135 136 static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) 137 { 138 struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg; 139 140 if (!(mtrr->mask_lo & MTRR_PHYSMASK_V)) 141 return MTRR_TYPE_INVALID; 142 143 *start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); 144 *size = get_mtrr_size((((u64)mtrr->mask_hi) << 32) + 145 (mtrr->mask_lo & PAGE_MASK)); 146 147 return mtrr->base_lo & MTRR_PHYSBASE_TYPE; 148 } 149 150 static u8 get_effective_type(u8 type1, u8 type2) 151 { 152 if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) 153 return MTRR_TYPE_UNCACHABLE; 154 155 if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) || 156 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK)) 157 return MTRR_TYPE_WRTHROUGH; 158 159 if (type1 != type2) 160 return MTRR_TYPE_UNCACHABLE; 161 162 return type1; 163 } 164 165 static void rm_map_entry_at(int idx) 166 { 167 cache_map_n--; 168 if (cache_map_n > idx) { 169 memmove(cache_map + idx, cache_map + idx + 1, 170 sizeof(*cache_map) * (cache_map_n - idx)); 171 } 172 } 173 174 /* 175 * Add an entry into cache_map at a specific index. Merges adjacent entries if 176 * appropriate. Return the number of merges for correcting the scan index 177 * (this is needed as merging will reduce the number of entries, which will 178 * result in skipping entries in future iterations if the scan index isn't 179 * corrected). 180 * Note that the corrected index can never go below -1 (resulting in being 0 in 181 * the next scan iteration), as "2" is returned only if the current index is 182 * larger than zero. 183 */ 184 static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) 185 { 186 bool merge_prev = false, merge_next = false; 187 188 if (start >= end) 189 return 0; 190 191 if (idx > 0) { 192 struct cache_map *prev = cache_map + idx - 1; 193 194 if (!prev->fixed && start == prev->end && type == prev->type) 195 merge_prev = true; 196 } 197 198 if (idx < cache_map_n) { 199 struct cache_map *next = cache_map + idx; 200 201 if (!next->fixed && end == next->start && type == next->type) 202 merge_next = true; 203 } 204 205 if (merge_prev && merge_next) { 206 cache_map[idx - 1].end = cache_map[idx].end; 207 rm_map_entry_at(idx); 208 return 2; 209 } 210 if (merge_prev) { 211 cache_map[idx - 1].end = end; 212 return 1; 213 } 214 if (merge_next) { 215 cache_map[idx].start = start; 216 return 1; 217 } 218 219 /* Sanity check: the array should NEVER be too small! */ 220 if (cache_map_n == cache_map_size) { 221 WARN(1, "MTRR cache mode memory map exhausted!\n"); 222 cache_map_n = cache_map_fixed; 223 return 0; 224 } 225 226 if (cache_map_n > idx) { 227 memmove(cache_map + idx + 1, cache_map + idx, 228 sizeof(*cache_map) * (cache_map_n - idx)); 229 } 230 231 cache_map[idx].start = start; 232 cache_map[idx].end = end; 233 cache_map[idx].type = type; 234 cache_map[idx].fixed = 0; 235 cache_map_n++; 236 237 return 0; 238 } 239 240 /* Clear a part of an entry. Return 1 if start of entry is still valid. */ 241 static int clr_map_range_at(u64 start, u64 end, int idx) 242 { 243 int ret = start != cache_map[idx].start; 244 u64 tmp; 245 246 if (start == cache_map[idx].start && end == cache_map[idx].end) { 247 rm_map_entry_at(idx); 248 } else if (start == cache_map[idx].start) { 249 cache_map[idx].start = end; 250 } else if (end == cache_map[idx].end) { 251 cache_map[idx].end = start; 252 } else { 253 tmp = cache_map[idx].end; 254 cache_map[idx].end = start; 255 add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); 256 } 257 258 return ret; 259 } 260 261 /* 262 * Add MTRR to the map. The current map is scanned and each part of the MTRR 263 * either overlapping with an existing entry or with a hole in the map is 264 * handled separately. 265 */ 266 static void add_map_entry(u64 start, u64 end, u8 type) 267 { 268 u8 new_type, old_type; 269 u64 tmp; 270 int i; 271 272 for (i = 0; i < cache_map_n && start < end; i++) { 273 if (start >= cache_map[i].end) 274 continue; 275 276 if (start < cache_map[i].start) { 277 /* Region start has no overlap. */ 278 tmp = min(end, cache_map[i].start); 279 i -= add_map_entry_at(start, tmp, type, i); 280 start = tmp; 281 continue; 282 } 283 284 new_type = get_effective_type(type, cache_map[i].type); 285 old_type = cache_map[i].type; 286 287 if (cache_map[i].fixed || new_type == old_type) { 288 /* Cut off start of new entry. */ 289 start = cache_map[i].end; 290 continue; 291 } 292 293 /* Handle only overlapping part of region. */ 294 tmp = min(end, cache_map[i].end); 295 i += clr_map_range_at(start, tmp, i); 296 i -= add_map_entry_at(start, tmp, new_type, i); 297 start = tmp; 298 } 299 300 /* Add rest of region after last map entry (rest might be empty). */ 301 add_map_entry_at(start, end, type, i); 302 } 303 304 /* Add variable MTRRs to cache map. */ 305 static void map_add_var(void) 306 { 307 u64 start, size; 308 unsigned int i; 309 u8 type; 310 311 /* 312 * Add AMD TOP_MEM2 area. Can't be added in mtrr_build_map(), as it 313 * needs to be added again when rebuilding the map due to potentially 314 * having moved as a result of variable MTRRs for memory below 4GB. 315 */ 316 if (mtrr_tom2) { 317 add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK); 318 cache_map[cache_map_n - 1].fixed = 1; 319 } 320 321 for (i = 0; i < num_var_ranges; i++) { 322 type = get_var_mtrr_state(i, &start, &size); 323 if (type != MTRR_TYPE_INVALID) 324 add_map_entry(start, start + size, type); 325 } 326 } 327 328 /* 329 * Rebuild map by replacing variable entries. Needs to be called when MTRR 330 * registers are being changed after boot, as such changes could include 331 * removals of registers, which are complicated to handle without rebuild of 332 * the map. 333 */ 334 void generic_rebuild_map(void) 335 { 336 if (mtrr_if != &generic_mtrr_ops) 337 return; 338 339 cache_map_n = cache_map_fixed; 340 341 map_add_var(); 342 } 343 344 static unsigned int __init get_cache_map_size(void) 345 { 346 return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0); 347 } 348 349 /* Build the cache_map containing the cache modes per memory range. */ 350 void __init mtrr_build_map(void) 351 { 352 u64 start, end, size; 353 unsigned int i; 354 u8 type; 355 356 /* Add fixed MTRRs, optimize for adjacent entries with same type. */ 357 if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { 358 /* 359 * Start with 64k size fixed entries, preset 1st one (hence the 360 * loop below is starting with index 1). 361 */ 362 start = 0; 363 end = size = 0x10000; 364 type = mtrr_state.fixed_ranges[0]; 365 366 for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) { 367 /* 8 64k entries, then 16 16k ones, rest 4k. */ 368 if (i == 8 || i == 24) 369 size >>= 2; 370 371 if (mtrr_state.fixed_ranges[i] != type) { 372 add_map_entry(start, end, type); 373 start = end; 374 type = mtrr_state.fixed_ranges[i]; 375 } 376 end += size; 377 } 378 add_map_entry(start, end, type); 379 } 380 381 /* Mark fixed, they take precedence. */ 382 for (i = 0; i < cache_map_n; i++) 383 cache_map[i].fixed = 1; 384 cache_map_fixed = cache_map_n; 385 386 map_add_var(); 387 388 pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n", 389 cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, 390 get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0)); 391 392 if (mtrr_debug) { 393 for (i = 0; i < cache_map_n; i++) { 394 pr_info("%3u: %016llx-%016llx %s\n", i, 395 cache_map[i].start, cache_map[i].end - 1, 396 mtrr_attrib_to_str(cache_map[i].type)); 397 } 398 } 399 } 400 401 /* Copy the cache_map from __initdata memory to dynamically allocated one. */ 402 void __init mtrr_copy_map(void) 403 { 404 unsigned int new_size = get_cache_map_size(); 405 406 if (!mtrr_state.enabled || !new_size) { 407 cache_map = NULL; 408 return; 409 } 410 411 mutex_lock(&mtrr_mutex); 412 413 cache_map = kzalloc_objs(*cache_map, new_size); 414 if (cache_map) { 415 memmove(cache_map, init_cache_map, 416 cache_map_n * sizeof(*cache_map)); 417 cache_map_size = new_size; 418 } else { 419 mtrr_state.enabled = 0; 420 pr_err("MTRRs disabled due to allocation failure for lookup map.\n"); 421 } 422 423 mutex_unlock(&mtrr_mutex); 424 } 425 426 /** 427 * guest_force_mtrr_state - set static MTRR state for a guest 428 * 429 * Used to set MTRR state via different means (e.g. with data obtained from 430 * a hypervisor). 431 * Is allowed only for special cases when running virtualized. Must be called 432 * from the x86_init.hyper.init_platform() hook. It can be called only once. 433 * The MTRR state can't be changed afterwards. To ensure that, X86_FEATURE_MTRR 434 * is cleared. 435 * 436 * @var: MTRR variable range array to use 437 * @num_var: length of the @var array 438 * @def_type: default caching type 439 */ 440 void guest_force_mtrr_state(struct mtrr_var_range *var, unsigned int num_var, 441 mtrr_type def_type) 442 { 443 unsigned int i; 444 445 /* Only allowed to be called once before mtrr_bp_init(). */ 446 if (WARN_ON_ONCE(mtrr_state_set)) 447 return; 448 449 /* Only allowed when running virtualized. */ 450 if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 451 return; 452 453 /* 454 * Only allowed for special virtualization cases: 455 * - when running as Hyper-V, SEV-SNP guest using vTOM 456 * - when running as Xen PV guest 457 * - when running as SEV-SNP or TDX guest to avoid unnecessary 458 * VMM communication/Virtualization exceptions (#VC, #VE) 459 */ 460 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && 461 !hv_is_isolation_supported() && 462 !cpu_feature_enabled(X86_FEATURE_XENPV) && 463 !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) 464 return; 465 466 /* Disable MTRR in order to disable MTRR modifications. */ 467 setup_clear_cpu_cap(X86_FEATURE_MTRR); 468 469 if (var) { 470 if (num_var > MTRR_MAX_VAR_RANGES) { 471 pr_warn("Trying to overwrite MTRR state with %u variable entries\n", 472 num_var); 473 num_var = MTRR_MAX_VAR_RANGES; 474 } 475 for (i = 0; i < num_var; i++) 476 mtrr_state.var_ranges[i] = var[i]; 477 num_var_ranges = num_var; 478 } 479 480 mtrr_state.def_type = def_type; 481 mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED; 482 483 mtrr_state_set = 1; 484 } 485 486 static u8 type_merge(u8 type, u8 new_type, u8 *uniform) 487 { 488 u8 effective_type; 489 490 if (type == MTRR_TYPE_INVALID) 491 return new_type; 492 493 effective_type = get_effective_type(type, new_type); 494 if (type != effective_type) 495 *uniform = 0; 496 497 return effective_type; 498 } 499 500 /** 501 * mtrr_type_lookup - look up memory type in MTRR 502 * 503 * @start: Begin of the physical address range 504 * @end: End of the physical address range 505 * @uniform: output argument: 506 * - 1: the returned MTRR type is valid for the whole region 507 * - 0: otherwise 508 * 509 * Return Values: 510 * MTRR_TYPE_(type) - The effective MTRR type for the region 511 * MTRR_TYPE_INVALID - MTRR is disabled 512 */ 513 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 514 { 515 u8 type = MTRR_TYPE_INVALID; 516 unsigned int i; 517 518 if (!mtrr_state_set) { 519 /* Uniformity is unknown. */ 520 *uniform = 0; 521 return MTRR_TYPE_UNCACHABLE; 522 } 523 524 *uniform = 1; 525 526 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) 527 return MTRR_TYPE_UNCACHABLE; 528 529 for (i = 0; i < cache_map_n && start < end; i++) { 530 /* Region after current map entry? -> continue with next one. */ 531 if (start >= cache_map[i].end) 532 continue; 533 534 /* Start of region not covered by current map entry? */ 535 if (start < cache_map[i].start) { 536 /* At least some part of region has default type. */ 537 type = type_merge(type, mtrr_state.def_type, uniform); 538 /* End of region not covered, too? -> lookup done. */ 539 if (end <= cache_map[i].start) 540 return type; 541 } 542 543 /* At least part of region covered by map entry. */ 544 type = type_merge(type, cache_map[i].type, uniform); 545 546 start = cache_map[i].end; 547 } 548 549 /* End of region past last entry in map? -> use default type. */ 550 if (start < end) 551 type = type_merge(type, mtrr_state.def_type, uniform); 552 553 return type; 554 } 555 556 /* Get the MSR pair relating to a var range */ 557 static void 558 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 559 { 560 struct msr val; 561 562 rdmsrq(MTRRphysBase_MSR(index), val.q); 563 vr->base_lo = val.l; 564 vr->base_hi = val.h; 565 rdmsrq(MTRRphysMask_MSR(index), val.q); 566 vr->mask_lo = val.l; 567 vr->mask_hi = val.h; 568 } 569 570 /* Fill the MSR pair relating to a var range */ 571 void fill_mtrr_var_range(unsigned int index, 572 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 573 { 574 struct mtrr_var_range *vr; 575 576 vr = mtrr_state.var_ranges; 577 578 vr[index].base_lo = base_lo; 579 vr[index].base_hi = base_hi; 580 vr[index].mask_lo = mask_lo; 581 vr[index].mask_hi = mask_hi; 582 } 583 584 static void get_fixed_ranges(mtrr_type *frs) 585 { 586 u64 *p = (u64 *)frs; 587 int i; 588 589 k8_check_syscfg_dram_mod_en(); 590 591 rdmsrq(MSR_MTRRfix64K_00000, p[0]); 592 593 for (i = 0; i < 2; i++) 594 rdmsrq(MSR_MTRRfix16K_80000 + i, p[1 + i]); 595 for (i = 0; i < 8; i++) 596 rdmsrq(MSR_MTRRfix4K_C0000 + i, p[3 + i]); 597 } 598 599 void mtrr_save_fixed_ranges(void *info) 600 { 601 if (mtrr_state.have_fixed) 602 get_fixed_ranges(mtrr_state.fixed_ranges); 603 } 604 605 static unsigned __initdata last_fixed_start; 606 static unsigned __initdata last_fixed_end; 607 static mtrr_type __initdata last_fixed_type; 608 609 static void __init print_fixed_last(void) 610 { 611 if (!last_fixed_end) 612 return; 613 614 pr_info(" %05X-%05X %s\n", last_fixed_start, 615 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 616 617 last_fixed_end = 0; 618 } 619 620 static void __init update_fixed_last(unsigned base, unsigned end, 621 mtrr_type type) 622 { 623 last_fixed_start = base; 624 last_fixed_end = end; 625 last_fixed_type = type; 626 } 627 628 static void __init 629 print_fixed(unsigned base, unsigned step, const mtrr_type *types) 630 { 631 unsigned i; 632 633 for (i = 0; i < 8; ++i, ++types, base += step) { 634 if (last_fixed_end == 0) { 635 update_fixed_last(base, base + step, *types); 636 continue; 637 } 638 if (last_fixed_end == base && last_fixed_type == *types) { 639 last_fixed_end = base + step; 640 continue; 641 } 642 /* new segments: gap or different type */ 643 print_fixed_last(); 644 update_fixed_last(base, base + step, *types); 645 } 646 } 647 648 static void __init print_mtrr_state(void) 649 { 650 unsigned int i; 651 int high_width; 652 653 pr_info("MTRR default type: %s\n", 654 mtrr_attrib_to_str(mtrr_state.def_type)); 655 if (mtrr_state.have_fixed) { 656 pr_info("MTRR fixed ranges %s:\n", 657 str_enabled_disabled( 658 (mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && 659 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED))); 660 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 661 for (i = 0; i < 2; ++i) 662 print_fixed(0x80000 + i * 0x20000, 0x04000, 663 mtrr_state.fixed_ranges + (i + 1) * 8); 664 for (i = 0; i < 8; ++i) 665 print_fixed(0xC0000 + i * 0x08000, 0x01000, 666 mtrr_state.fixed_ranges + (i + 3) * 8); 667 668 /* tail */ 669 print_fixed_last(); 670 } 671 pr_info("MTRR variable ranges %s:\n", 672 str_enabled_disabled(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)); 673 high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; 674 675 for (i = 0; i < num_var_ranges; ++i) { 676 if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) 677 pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 678 i, 679 high_width, 680 mtrr_state.var_ranges[i].base_hi, 681 mtrr_state.var_ranges[i].base_lo >> 12, 682 high_width, 683 mtrr_state.var_ranges[i].mask_hi, 684 mtrr_state.var_ranges[i].mask_lo >> 12, 685 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 686 MTRR_PHYSBASE_TYPE)); 687 else 688 pr_info(" %u disabled\n", i); 689 } 690 if (mtrr_tom2) 691 pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 692 } 693 694 /* Grab all of the MTRR state for this CPU into *state */ 695 bool __init get_mtrr_state(void) 696 { 697 struct mtrr_var_range *vrs; 698 unsigned int i; 699 u64 q; 700 701 vrs = mtrr_state.var_ranges; 702 703 rdmsrq(MSR_MTRRcap, q); 704 mtrr_state.have_fixed = q & MTRR_CAP_FIX; 705 706 for (i = 0; i < num_var_ranges; i++) 707 get_mtrr_var_range(i, &vrs[i]); 708 if (mtrr_state.have_fixed) 709 get_fixed_ranges(mtrr_state.fixed_ranges); 710 711 rdmsrq(MSR_MTRRdefType, q); 712 mtrr_state.def_type = q & MTRR_DEF_TYPE_TYPE; 713 mtrr_state.enabled = (q & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT; 714 715 if (amd_special_default_mtrr()) { 716 /* TOP_MEM2 */ 717 rdmsrq(MSR_K8_TOP_MEM2, mtrr_tom2); 718 mtrr_tom2 &= 0xffffff800000ULL; 719 } 720 721 if (mtrr_debug) 722 print_mtrr_state(); 723 724 mtrr_state_set = 1; 725 726 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED); 727 } 728 729 /* Some BIOS's are messed up and don't set all MTRRs the same! */ 730 void __init mtrr_state_warn(void) 731 { 732 unsigned long mask = smp_changes_mask; 733 734 if (!mask) 735 return; 736 if (mask & MTRR_CHANGE_MASK_FIXED) 737 pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 738 if (mask & MTRR_CHANGE_MASK_VARIABLE) 739 pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 740 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 741 pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 742 743 pr_info("mtrr: probably your BIOS does not setup all CPUs.\n"); 744 pr_info("mtrr: corrected configuration.\n"); 745 } 746 747 /* 748 * Doesn't attempt to pass an error out to MTRR users 749 * because it's quite complicated in some cases and probably not 750 * worth it because the best error handling is to ignore it. 751 */ 752 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 753 { 754 struct msr val = { .l = a, .h = b }; 755 756 if (wrmsrq_safe(msr, val.q) < 0) { 757 pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 758 smp_processor_id(), msr, a, b); 759 } 760 } 761 762 /** 763 * set_fixed_range - checks & updates a fixed-range MTRR if it 764 * differs from the value it should have 765 * @msr: MSR address of the MTTR which should be checked and updated 766 * @changed: pointer which indicates whether the MTRR needed to be changed 767 * @msrwords: pointer to the MSR values which the MSR should have 768 */ 769 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 770 { 771 struct msr val; 772 773 rdmsrq(msr, val.q); 774 775 if (val.l != msrwords[0] || val.h != msrwords[1]) { 776 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 777 *changed = true; 778 } 779 } 780 781 /** 782 * generic_get_free_region - Get a free MTRR. 783 * @base: The starting (base) address of the region. 784 * @size: The size (in bytes) of the region. 785 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 786 * 787 * Returns: The index of the region on success, else negative on error. 788 */ 789 int 790 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 791 { 792 unsigned long lbase, lsize; 793 mtrr_type ltype; 794 int i, max; 795 796 max = num_var_ranges; 797 if (replace_reg >= 0 && replace_reg < max) 798 return replace_reg; 799 800 for (i = 0; i < max; ++i) { 801 mtrr_if->get(i, &lbase, &lsize, <ype); 802 if (lsize == 0) 803 return i; 804 } 805 806 return -ENOSPC; 807 } 808 809 static void generic_get_mtrr(unsigned int reg, unsigned long *base, 810 unsigned long *size, mtrr_type *type) 811 { 812 u64 tmp, mask, base_msr; 813 unsigned int hi; 814 815 /* 816 * get_mtrr doesn't need to update mtrr_state, also it could be called 817 * from any cpu, so try to print it out directly. 818 */ 819 get_cpu(); 820 821 rdmsrq(MTRRphysMask_MSR(reg), mask); 822 823 if (!(mask & MTRR_PHYSMASK_V)) { 824 /* Invalid (i.e. free) range */ 825 *base = 0; 826 *size = 0; 827 *type = 0; 828 goto out_put_cpu; 829 } 830 831 rdmsrq(MTRRphysBase_MSR(reg), base_msr); 832 833 /* Work out the shifted address mask: */ 834 tmp = mask & PAGE_MASK; 835 mask = (u64)phys_hi_rsvd << 32 | tmp; 836 837 /* Expand tmp with high bits to all 1s: */ 838 hi = fls64(tmp); 839 if (hi > 0) { 840 tmp |= ~((1ULL<<(hi - 1)) - 1); 841 842 if (tmp != mask) { 843 pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 844 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 845 mask = tmp; 846 } 847 } 848 849 /* 850 * This works correctly if size is a power of two, i.e. a 851 * contiguous range: 852 */ 853 *size = -mask >> PAGE_SHIFT; 854 *base = base_msr >> PAGE_SHIFT; 855 *type = base_msr & MTRR_PHYSBASE_TYPE; 856 857 out_put_cpu: 858 put_cpu(); 859 } 860 861 /** 862 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 863 * differ from the saved set 864 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 865 */ 866 static int set_fixed_ranges(mtrr_type *frs) 867 { 868 unsigned long long *saved = (unsigned long long *)frs; 869 bool changed = false; 870 int block = -1, range; 871 872 k8_check_syscfg_dram_mod_en(); 873 874 while (fixed_range_blocks[++block].ranges) { 875 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 876 set_fixed_range(fixed_range_blocks[block].base_msr + range, 877 &changed, (unsigned int *)saved++); 878 } 879 880 return changed; 881 } 882 883 /* 884 * Set the MSR pair relating to a var range. 885 * Returns true if changes are made. 886 */ 887 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 888 { 889 bool changed = false; 890 struct msr val; 891 892 rdmsrq(MTRRphysBase_MSR(index), val.q); 893 if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (val.l & ~MTRR_PHYSBASE_RSVD) 894 || (vr->base_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) { 895 896 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 897 changed = true; 898 } 899 900 rdmsrq(MTRRphysMask_MSR(index), val.q); 901 902 if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (val.l & ~MTRR_PHYSMASK_RSVD) 903 || (vr->mask_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) { 904 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 905 changed = true; 906 } 907 return changed; 908 } 909 910 static u32 deftype_lo, deftype_hi; 911 912 /** 913 * set_mtrr_state - Set the MTRR state for this CPU. 914 * 915 * NOTE: The CPU must already be in a safe state for MTRR changes, including 916 * measures that only a single CPU can be active in set_mtrr_state() in 917 * order to not be subject to races for usage of deftype_lo. This is 918 * accomplished by taking cache_disable_lock. 919 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 920 */ 921 static unsigned long set_mtrr_state(void) 922 { 923 unsigned long change_mask = 0; 924 unsigned int i; 925 926 for (i = 0; i < num_var_ranges; i++) { 927 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 928 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 929 } 930 931 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 932 change_mask |= MTRR_CHANGE_MASK_FIXED; 933 934 /* 935 * Set_mtrr_restore restores the old value of MTRRdefType, 936 * so to set it we fiddle with the saved value: 937 */ 938 if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type || 939 ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != mtrr_state.enabled) { 940 941 deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) | 942 mtrr_state.def_type | 943 (mtrr_state.enabled << MTRR_STATE_SHIFT); 944 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 945 } 946 947 return change_mask; 948 } 949 950 void mtrr_disable(void) 951 { 952 struct msr val; 953 954 /* Save MTRR state */ 955 rdmsrq(MSR_MTRRdefType, val.q); 956 deftype_lo = val.l; 957 deftype_hi = val.h; 958 959 /* Disable MTRRs, and set the default type to uncached */ 960 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_hi); 961 } 962 963 void mtrr_enable(void) 964 { 965 /* Intel (P6) standard MTRRs */ 966 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 967 } 968 969 void mtrr_generic_set_state(void) 970 { 971 unsigned long mask, count; 972 973 /* Actually set the state */ 974 mask = set_mtrr_state(); 975 976 /* Use the atomic bitops to update the global mask */ 977 for (count = 0; count < sizeof(mask) * 8; ++count) { 978 if (mask & 0x01) 979 set_bit(count, &smp_changes_mask); 980 mask >>= 1; 981 } 982 } 983 984 /** 985 * generic_set_mtrr - set variable MTRR register on the local CPU. 986 * 987 * @reg: The register to set. 988 * @base: The base address of the region. 989 * @size: The size of the region. If this is 0 the region is disabled. 990 * @type: The type of the region. 991 * 992 * Returns nothing. 993 */ 994 static void generic_set_mtrr(unsigned int reg, unsigned long base, 995 unsigned long size, mtrr_type type) 996 { 997 unsigned long flags; 998 struct mtrr_var_range *vr; 999 1000 vr = &mtrr_state.var_ranges[reg]; 1001 1002 local_irq_save(flags); 1003 cache_disable(); 1004 1005 if (size == 0) { 1006 /* 1007 * The invalid bit is kept in the mask, so we simply 1008 * clear the relevant mask register to disable a range. 1009 */ 1010 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 1011 memset(vr, 0, sizeof(struct mtrr_var_range)); 1012 } else { 1013 vr->base_lo = base << PAGE_SHIFT | type; 1014 vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 1015 vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V; 1016 vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 1017 1018 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 1019 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 1020 } 1021 1022 cache_enable(); 1023 local_irq_restore(flags); 1024 } 1025 1026 int generic_validate_add_page(unsigned long base, unsigned long size, 1027 unsigned int type) 1028 { 1029 unsigned long lbase, last; 1030 1031 /* 1032 * For Intel PPro stepping <= 7 1033 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 1034 */ 1035 if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && 1036 boot_cpu_data.x86_stepping <= 7) { 1037 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 1038 pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 1039 return -EINVAL; 1040 } 1041 if (!(base + size < 0x70000 || base > 0x7003F) && 1042 (type == MTRR_TYPE_WRCOMB 1043 || type == MTRR_TYPE_WRBACK)) { 1044 pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 1045 return -EINVAL; 1046 } 1047 } 1048 1049 /* 1050 * Check upper bits of base and last are equal and lower bits are 0 1051 * for base and 1 for last 1052 */ 1053 last = base + size - 1; 1054 for (lbase = base; !(lbase & 1) && (last & 1); 1055 lbase = lbase >> 1, last = last >> 1) 1056 ; 1057 if (lbase != last) { 1058 pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 1059 return -EINVAL; 1060 } 1061 return 0; 1062 } 1063 1064 static int generic_have_wrcomb(void) 1065 { 1066 u64 config; 1067 1068 rdmsrq(MSR_MTRRcap, config); 1069 return config & MTRR_CAP_WC; 1070 } 1071 1072 int positive_have_wrcomb(void) 1073 { 1074 return 1; 1075 } 1076 1077 /* 1078 * Generic structure... 1079 */ 1080 const struct mtrr_ops generic_mtrr_ops = { 1081 .get = generic_get_mtrr, 1082 .get_free_region = generic_get_free_region, 1083 .set = generic_set_mtrr, 1084 .validate_add_page = generic_validate_add_page, 1085 .have_wrcomb = generic_have_wrcomb, 1086 }; 1087