1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/i8253.h> 20 #include <linux/random.h> 21 #include <asm/processor.h> 22 #include <asm/hypervisor.h> 23 #include <asm/hyperv-tlfs.h> 24 #include <asm/mshyperv.h> 25 #include <asm/desc.h> 26 #include <asm/idtentry.h> 27 #include <asm/irq_regs.h> 28 #include <asm/i8259.h> 29 #include <asm/apic.h> 30 #include <asm/timer.h> 31 #include <asm/reboot.h> 32 #include <asm/nmi.h> 33 #include <clocksource/hyperv_timer.h> 34 #include <asm/numa.h> 35 #include <asm/svm.h> 36 37 /* Is Linux running as the root partition? */ 38 bool hv_root_partition; 39 /* Is Linux running on nested Microsoft Hypervisor */ 40 bool hv_nested; 41 struct ms_hyperv_info ms_hyperv; 42 43 /* Used in modules via hv_do_hypercall(): see arch/x86/include/asm/mshyperv.h */ 44 bool hyperv_paravisor_present __ro_after_init; 45 EXPORT_SYMBOL_GPL(hyperv_paravisor_present); 46 47 #if IS_ENABLED(CONFIG_HYPERV) 48 static inline unsigned int hv_get_nested_reg(unsigned int reg) 49 { 50 if (hv_is_sint_reg(reg)) 51 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0; 52 53 switch (reg) { 54 case HV_REGISTER_SIMP: 55 return HV_REGISTER_NESTED_SIMP; 56 case HV_REGISTER_SIEFP: 57 return HV_REGISTER_NESTED_SIEFP; 58 case HV_REGISTER_SVERSION: 59 return HV_REGISTER_NESTED_SVERSION; 60 case HV_REGISTER_SCONTROL: 61 return HV_REGISTER_NESTED_SCONTROL; 62 case HV_REGISTER_EOM: 63 return HV_REGISTER_NESTED_EOM; 64 default: 65 return reg; 66 } 67 } 68 69 u64 hv_get_non_nested_register(unsigned int reg) 70 { 71 u64 value; 72 73 if (hv_is_synic_reg(reg) && ms_hyperv.paravisor_present) 74 hv_ivm_msr_read(reg, &value); 75 else 76 rdmsrl(reg, value); 77 return value; 78 } 79 EXPORT_SYMBOL_GPL(hv_get_non_nested_register); 80 81 void hv_set_non_nested_register(unsigned int reg, u64 value) 82 { 83 if (hv_is_synic_reg(reg) && ms_hyperv.paravisor_present) { 84 hv_ivm_msr_write(reg, value); 85 86 /* Write proxy bit via wrmsl instruction */ 87 if (hv_is_sint_reg(reg)) 88 wrmsrl(reg, value | 1 << 20); 89 } else { 90 wrmsrl(reg, value); 91 } 92 } 93 EXPORT_SYMBOL_GPL(hv_set_non_nested_register); 94 95 u64 hv_get_register(unsigned int reg) 96 { 97 if (hv_nested) 98 reg = hv_get_nested_reg(reg); 99 100 return hv_get_non_nested_register(reg); 101 } 102 EXPORT_SYMBOL_GPL(hv_get_register); 103 104 void hv_set_register(unsigned int reg, u64 value) 105 { 106 if (hv_nested) 107 reg = hv_get_nested_reg(reg); 108 109 hv_set_non_nested_register(reg, value); 110 } 111 EXPORT_SYMBOL_GPL(hv_set_register); 112 113 static void (*vmbus_handler)(void); 114 static void (*hv_stimer0_handler)(void); 115 static void (*hv_kexec_handler)(void); 116 static void (*hv_crash_handler)(struct pt_regs *regs); 117 118 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 119 { 120 struct pt_regs *old_regs = set_irq_regs(regs); 121 122 inc_irq_stat(irq_hv_callback_count); 123 if (vmbus_handler) 124 vmbus_handler(); 125 126 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 127 apic_eoi(); 128 129 set_irq_regs(old_regs); 130 } 131 132 void hv_setup_vmbus_handler(void (*handler)(void)) 133 { 134 vmbus_handler = handler; 135 } 136 137 void hv_remove_vmbus_handler(void) 138 { 139 /* We have no way to deallocate the interrupt gate */ 140 vmbus_handler = NULL; 141 } 142 143 /* 144 * Routines to do per-architecture handling of stimer0 145 * interrupts when in Direct Mode 146 */ 147 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 148 { 149 struct pt_regs *old_regs = set_irq_regs(regs); 150 151 inc_irq_stat(hyperv_stimer0_count); 152 if (hv_stimer0_handler) 153 hv_stimer0_handler(); 154 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 155 apic_eoi(); 156 157 set_irq_regs(old_regs); 158 } 159 160 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 161 void hv_setup_stimer0_handler(void (*handler)(void)) 162 { 163 hv_stimer0_handler = handler; 164 } 165 166 void hv_remove_stimer0_handler(void) 167 { 168 /* We have no way to deallocate the interrupt gate */ 169 hv_stimer0_handler = NULL; 170 } 171 172 void hv_setup_kexec_handler(void (*handler)(void)) 173 { 174 hv_kexec_handler = handler; 175 } 176 177 void hv_remove_kexec_handler(void) 178 { 179 hv_kexec_handler = NULL; 180 } 181 182 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 183 { 184 hv_crash_handler = handler; 185 } 186 187 void hv_remove_crash_handler(void) 188 { 189 hv_crash_handler = NULL; 190 } 191 192 #ifdef CONFIG_KEXEC_CORE 193 static void hv_machine_shutdown(void) 194 { 195 if (kexec_in_progress && hv_kexec_handler) 196 hv_kexec_handler(); 197 198 /* 199 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 200 * corrupts the old VP Assist Pages and can crash the kexec kernel. 201 */ 202 if (kexec_in_progress && hyperv_init_cpuhp > 0) 203 cpuhp_remove_state(hyperv_init_cpuhp); 204 205 /* The function calls stop_other_cpus(). */ 206 native_machine_shutdown(); 207 208 /* Disable the hypercall page when there is only 1 active CPU. */ 209 if (kexec_in_progress) 210 hyperv_cleanup(); 211 } 212 213 static void hv_machine_crash_shutdown(struct pt_regs *regs) 214 { 215 if (hv_crash_handler) 216 hv_crash_handler(regs); 217 218 /* The function calls crash_smp_send_stop(). */ 219 native_machine_crash_shutdown(regs); 220 221 /* Disable the hypercall page when there is only 1 active CPU. */ 222 hyperv_cleanup(); 223 } 224 #endif /* CONFIG_KEXEC_CORE */ 225 #endif /* CONFIG_HYPERV */ 226 227 static uint32_t __init ms_hyperv_platform(void) 228 { 229 u32 eax; 230 u32 hyp_signature[3]; 231 232 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 233 return 0; 234 235 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 236 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 237 238 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 239 memcmp("Microsoft Hv", hyp_signature, 12)) 240 return 0; 241 242 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 243 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 244 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 245 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 246 return 0; 247 } 248 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 249 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 250 return 0; 251 } 252 253 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 254 } 255 256 #ifdef CONFIG_X86_LOCAL_APIC 257 /* 258 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 259 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 260 * unknown NMI on the first CPU which gets it. 261 */ 262 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 263 { 264 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 265 unsigned int old_cpu, this_cpu; 266 267 if (!unknown_nmi_panic) 268 return NMI_DONE; 269 270 old_cpu = -1; 271 this_cpu = raw_smp_processor_id(); 272 if (!atomic_try_cmpxchg(&nmi_cpu, &old_cpu, this_cpu)) 273 return NMI_HANDLED; 274 275 return NMI_DONE; 276 } 277 #endif 278 279 static unsigned long hv_get_tsc_khz(void) 280 { 281 unsigned long freq; 282 283 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 284 285 return freq / 1000; 286 } 287 288 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 289 static void __init hv_smp_prepare_boot_cpu(void) 290 { 291 native_smp_prepare_boot_cpu(); 292 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 293 hv_init_spinlocks(); 294 #endif 295 } 296 297 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 298 { 299 #ifdef CONFIG_X86_64 300 int i; 301 int ret; 302 #endif 303 304 native_smp_prepare_cpus(max_cpus); 305 306 /* 307 * Override wakeup_secondary_cpu_64 callback for SEV-SNP 308 * enlightened guest. 309 */ 310 if (!ms_hyperv.paravisor_present && hv_isolation_type_snp()) { 311 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap; 312 return; 313 } 314 315 #ifdef CONFIG_X86_64 316 for_each_present_cpu(i) { 317 if (i == 0) 318 continue; 319 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 320 BUG_ON(ret); 321 } 322 323 for_each_present_cpu(i) { 324 if (i == 0) 325 continue; 326 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 327 BUG_ON(ret); 328 } 329 #endif 330 } 331 #endif 332 333 /* 334 * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the 335 * HW_REDUCED flag: refer to acpi_tb_create_local_fadt(). Consequently ttyS0 336 * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns 337 * NULL for ttyS0. This happens because mp_config_acpi_legacy_irqs() sees a 338 * nr_legacy_irqs() of 0, so it doesn't initialize the array 'mp_irqs[]', and 339 * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs 340 * from the array and hence doesn't create the necessary irq description info. 341 * 342 * Clone arch/x86/kernel/acpi/boot.c: acpi_generic_reduced_hw_init() here, 343 * except don't change 'legacy_pic', which keeps its default value 344 * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero 345 * nr_legacy_irqs() and eventually serial console interrupts works properly. 346 */ 347 static void __init reduced_hw_init(void) 348 { 349 x86_init.timers.timer_init = x86_init_noop; 350 x86_init.irqs.pre_vector_init = x86_init_noop; 351 } 352 353 static void __init ms_hyperv_init_platform(void) 354 { 355 int hv_max_functions_eax; 356 int hv_host_info_eax; 357 int hv_host_info_ebx; 358 int hv_host_info_ecx; 359 int hv_host_info_edx; 360 361 #ifdef CONFIG_PARAVIRT 362 pv_info.name = "Hyper-V"; 363 #endif 364 365 /* 366 * Extract the features and hints 367 */ 368 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 369 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 370 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 371 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 372 373 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 374 375 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n", 376 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, 377 ms_hyperv.misc_features); 378 379 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 380 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 381 382 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 383 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 384 385 /* 386 * Check CPU management privilege. 387 * 388 * To mirror what Windows does we should extract CPU management 389 * features and use the ReservedIdentityBit to detect if Linux is the 390 * root partition. But that requires negotiating CPU management 391 * interface (a process to be finalized). For now, use the privilege 392 * flag as the indicator for running as root. 393 * 394 * Hyper-V should never specify running as root and as a Confidential 395 * VM. But to protect against a compromised/malicious Hyper-V trying 396 * to exploit root behavior to expose Confidential VM memory, ignore 397 * the root partition setting if also a Confidential VM. 398 */ 399 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) && 400 !(ms_hyperv.priv_high & HV_ISOLATION)) { 401 hv_root_partition = true; 402 pr_info("Hyper-V: running as root partition\n"); 403 } 404 405 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 406 hv_nested = true; 407 pr_info("Hyper-V: running on a nested hypervisor\n"); 408 } 409 410 /* 411 * Extract host information. 412 */ 413 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) { 414 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION); 415 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION); 416 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION); 417 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION); 418 419 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n", 420 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF, 421 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF, 422 hv_host_info_ecx, hv_host_info_edx >> 24); 423 } 424 425 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 426 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 427 x86_platform.calibrate_tsc = hv_get_tsc_khz; 428 x86_platform.calibrate_cpu = hv_get_tsc_khz; 429 } 430 431 if (ms_hyperv.priv_high & HV_ISOLATION) { 432 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 433 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 434 435 if (ms_hyperv.shared_gpa_boundary_active) 436 ms_hyperv.shared_gpa_boundary = 437 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 438 439 hyperv_paravisor_present = !!ms_hyperv.paravisor_present; 440 441 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 442 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 443 444 445 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) { 446 static_branch_enable(&isolation_type_snp); 447 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) { 448 static_branch_enable(&isolation_type_tdx); 449 450 /* A TDX VM must use x2APIC and doesn't use lazy EOI. */ 451 ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED; 452 453 if (!ms_hyperv.paravisor_present) { 454 /* To be supported: more work is required. */ 455 ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE; 456 457 /* HV_REGISTER_CRASH_CTL is unsupported. */ 458 ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE; 459 460 /* Don't trust Hyper-V's TLB-flushing hypercalls. */ 461 ms_hyperv.hints &= ~HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED; 462 463 x86_init.acpi.reduced_hw_early_init = reduced_hw_init; 464 } 465 } 466 } 467 468 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 469 ms_hyperv.nested_features = 470 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 471 pr_info("Hyper-V: Nested features: 0x%x\n", 472 ms_hyperv.nested_features); 473 } 474 475 #ifdef CONFIG_X86_LOCAL_APIC 476 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 477 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 478 /* 479 * Get the APIC frequency. 480 */ 481 u64 hv_lapic_frequency; 482 483 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 484 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 485 lapic_timer_period = hv_lapic_frequency; 486 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 487 lapic_timer_period); 488 } 489 490 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 491 "hv_nmi_unknown"); 492 #endif 493 494 #ifdef CONFIG_X86_IO_APIC 495 no_timer_check = 1; 496 #endif 497 498 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE) 499 machine_ops.shutdown = hv_machine_shutdown; 500 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 501 #endif 502 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 503 /* 504 * Writing to synthetic MSR 0x40000118 updates/changes the 505 * guest visible CPUIDs. Setting bit 0 of this MSR enables 506 * guests to report invariant TSC feature through CPUID 507 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 508 * early_init_intel() where this bit is examined. The 509 * setting of this MSR bit should happen before init_intel() 510 * is called. 511 */ 512 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 513 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 514 } 515 516 /* 517 * Generation 2 instances don't support reading the NMI status from 518 * 0x61 port. 519 */ 520 if (efi_enabled(EFI_BOOT)) 521 x86_platform.get_nmi_reason = hv_get_nmi_reason; 522 523 /* 524 * Hyper-V VMs have a PIT emulation quirk such that zeroing the 525 * counter register during PIT shutdown restarts the PIT. So it 526 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter 527 * to false tells pit_shutdown() not to zero the counter so that 528 * the PIT really is shutdown. Generation 2 VMs don't have a PIT, 529 * and setting this value has no effect. 530 */ 531 i8253_clear_counter_on_shutdown = false; 532 533 #if IS_ENABLED(CONFIG_HYPERV) 534 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) || 535 ms_hyperv.paravisor_present) 536 hv_vtom_init(); 537 /* 538 * Setup the hook to get control post apic initialization. 539 */ 540 x86_platform.apic_post_init = hyperv_init; 541 hyperv_setup_mmu_ops(); 542 543 /* Install system interrupt handler for hypervisor callback */ 544 sysvec_install(HYPERVISOR_CALLBACK_VECTOR, sysvec_hyperv_callback); 545 546 /* Install system interrupt handler for reenlightenment notifications */ 547 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 548 sysvec_install(HYPERV_REENLIGHTENMENT_VECTOR, sysvec_hyperv_reenlightenment); 549 } 550 551 /* Install system interrupt handler for stimer0 */ 552 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 553 sysvec_install(HYPERV_STIMER0_VECTOR, sysvec_hyperv_stimer0); 554 } 555 556 # ifdef CONFIG_SMP 557 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 558 if (hv_root_partition || 559 (!ms_hyperv.paravisor_present && hv_isolation_type_snp())) 560 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 561 # endif 562 563 /* 564 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 565 * set x2apic destination mode to physical mode when x2apic is available 566 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 567 * have 8-bit APIC id. 568 */ 569 # ifdef CONFIG_X86_X2APIC 570 if (x2apic_supported()) 571 x2apic_phys = 1; 572 # endif 573 574 /* Register Hyper-V specific clocksource */ 575 hv_init_clocksource(); 576 hv_vtl_init_platform(); 577 #endif 578 /* 579 * TSC should be marked as unstable only after Hyper-V 580 * clocksource has been initialized. This ensures that the 581 * stability of the sched_clock is not altered. 582 */ 583 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 584 mark_tsc_unstable("running on Hyper-V"); 585 586 hardlockup_detector_disable(); 587 } 588 589 static bool __init ms_hyperv_x2apic_available(void) 590 { 591 return x2apic_supported(); 592 } 593 594 /* 595 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 596 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 597 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 598 * 599 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 600 * (logically) generates MSIs directly to the system APIC irq domain. 601 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 602 * pci-hyperv host bridge. 603 * 604 * Note: for a Hyper-V root partition, this will always return false. 605 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by 606 * default, they are implemented as intercepts by the Windows Hyper-V stack. 607 * Even a nested root partition (L2 root) will not get them because the 608 * nested (L1) hypervisor filters them out. 609 */ 610 static bool __init ms_hyperv_msi_ext_dest_id(void) 611 { 612 u32 eax; 613 614 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 615 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 616 return false; 617 618 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 619 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 620 } 621 622 #ifdef CONFIG_AMD_MEM_ENCRYPT 623 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs) 624 { 625 /* RAX and CPL are already in the GHCB */ 626 ghcb_set_rcx(ghcb, regs->cx); 627 ghcb_set_rdx(ghcb, regs->dx); 628 ghcb_set_r8(ghcb, regs->r8); 629 } 630 631 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs) 632 { 633 /* No checking of the return state needed */ 634 return true; 635 } 636 #endif 637 638 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 639 .name = "Microsoft Hyper-V", 640 .detect = ms_hyperv_platform, 641 .type = X86_HYPER_MS_HYPERV, 642 .init.x2apic_available = ms_hyperv_x2apic_available, 643 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 644 .init.init_platform = ms_hyperv_init_platform, 645 #ifdef CONFIG_AMD_MEM_ENCRYPT 646 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare, 647 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish, 648 #endif 649 }; 650