1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/random.h> 20 #include <asm/processor.h> 21 #include <asm/hypervisor.h> 22 #include <asm/cpuid/api.h> 23 #include <hyperv/hvhdk.h> 24 #include <asm/mshyperv.h> 25 #include <asm/desc.h> 26 #include <asm/idtentry.h> 27 #include <asm/irq_regs.h> 28 #include <asm/i8259.h> 29 #include <asm/apic.h> 30 #include <asm/timer.h> 31 #include <asm/reboot.h> 32 #include <asm/msr.h> 33 #include <asm/nmi.h> 34 #include <clocksource/hyperv_timer.h> 35 #include <asm/numa.h> 36 #include <asm/svm.h> 37 38 /* Is Linux running on nested Microsoft Hypervisor */ 39 bool hv_nested; 40 struct ms_hyperv_info ms_hyperv; 41 42 #if IS_ENABLED(CONFIG_HYPERV) 43 /* 44 * When running with the paravisor, controls proxying the synthetic interrupts 45 * from the host 46 */ 47 static bool hv_para_sint_proxy; 48 49 static inline unsigned int hv_get_nested_msr(unsigned int reg) 50 { 51 if (hv_is_sint_msr(reg)) 52 return reg - HV_X64_MSR_SINT0 + HV_X64_MSR_NESTED_SINT0; 53 54 switch (reg) { 55 case HV_X64_MSR_SIMP: 56 return HV_X64_MSR_NESTED_SIMP; 57 case HV_X64_MSR_SIEFP: 58 return HV_X64_MSR_NESTED_SIEFP; 59 case HV_X64_MSR_SVERSION: 60 return HV_X64_MSR_NESTED_SVERSION; 61 case HV_X64_MSR_SCONTROL: 62 return HV_X64_MSR_NESTED_SCONTROL; 63 case HV_X64_MSR_EOM: 64 return HV_X64_MSR_NESTED_EOM; 65 default: 66 return reg; 67 } 68 } 69 70 u64 hv_get_non_nested_msr(unsigned int reg) 71 { 72 u64 value; 73 74 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) 75 hv_ivm_msr_read(reg, &value); 76 else 77 rdmsrq(reg, value); 78 return value; 79 } 80 EXPORT_SYMBOL_GPL(hv_get_non_nested_msr); 81 82 void hv_set_non_nested_msr(unsigned int reg, u64 value) 83 { 84 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) { 85 /* The hypervisor will get the intercept. */ 86 hv_ivm_msr_write(reg, value); 87 88 /* Using wrmsrq so the following goes to the paravisor. */ 89 if (hv_is_sint_msr(reg)) { 90 union hv_synic_sint sint = { .as_uint64 = value }; 91 92 sint.proxy = hv_para_sint_proxy; 93 native_wrmsrq(reg, sint.as_uint64); 94 } 95 } else { 96 native_wrmsrq(reg, value); 97 } 98 } 99 EXPORT_SYMBOL_GPL(hv_set_non_nested_msr); 100 101 /* 102 * Enable or disable proxying synthetic interrupts 103 * to the paravisor. 104 */ 105 void hv_para_set_sint_proxy(bool enable) 106 { 107 hv_para_sint_proxy = enable; 108 } 109 110 /* 111 * Get the SynIC register value from the paravisor. 112 */ 113 u64 hv_para_get_synic_register(unsigned int reg) 114 { 115 if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) 116 return ~0ULL; 117 return native_read_msr(reg); 118 } 119 120 /* 121 * Set the SynIC register value with the paravisor. 122 */ 123 void hv_para_set_synic_register(unsigned int reg, u64 val) 124 { 125 if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) 126 return; 127 native_write_msr(reg, val); 128 } 129 130 u64 hv_get_msr(unsigned int reg) 131 { 132 if (hv_nested) 133 reg = hv_get_nested_msr(reg); 134 135 return hv_get_non_nested_msr(reg); 136 } 137 EXPORT_SYMBOL_GPL(hv_get_msr); 138 139 void hv_set_msr(unsigned int reg, u64 value) 140 { 141 if (hv_nested) 142 reg = hv_get_nested_msr(reg); 143 144 hv_set_non_nested_msr(reg, value); 145 } 146 EXPORT_SYMBOL_GPL(hv_set_msr); 147 148 static void (*mshv_handler)(void); 149 static void (*vmbus_handler)(void); 150 static void (*hv_stimer0_handler)(void); 151 static void (*hv_kexec_handler)(void); 152 static void (*hv_crash_handler)(struct pt_regs *regs); 153 154 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 155 { 156 struct pt_regs *old_regs = set_irq_regs(regs); 157 158 inc_irq_stat(HYPERVISOR_CALLBACK); 159 if (mshv_handler) 160 mshv_handler(); 161 162 if (vmbus_handler) 163 vmbus_handler(); 164 165 add_interrupt_randomness(HYPERVISOR_CALLBACK_VECTOR); 166 167 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 168 apic_eoi(); 169 170 set_irq_regs(old_regs); 171 } 172 173 void hv_setup_mshv_handler(void (*handler)(void)) 174 { 175 mshv_handler = handler; 176 } 177 178 void hv_setup_vmbus_handler(void (*handler)(void)) 179 { 180 vmbus_handler = handler; 181 } 182 183 void hv_remove_vmbus_handler(void) 184 { 185 /* We have no way to deallocate the interrupt gate */ 186 vmbus_handler = NULL; 187 } 188 189 /* 190 * Routines to do per-architecture handling of stimer0 191 * interrupts when in Direct Mode 192 */ 193 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 194 { 195 struct pt_regs *old_regs = set_irq_regs(regs); 196 197 inc_irq_stat(HYPERV_STIMER0); 198 if (hv_stimer0_handler) 199 hv_stimer0_handler(); 200 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 201 apic_eoi(); 202 203 set_irq_regs(old_regs); 204 } 205 206 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 207 void hv_setup_stimer0_handler(void (*handler)(void)) 208 { 209 hv_stimer0_handler = handler; 210 } 211 212 void hv_remove_stimer0_handler(void) 213 { 214 /* We have no way to deallocate the interrupt gate */ 215 hv_stimer0_handler = NULL; 216 } 217 218 void hv_setup_kexec_handler(void (*handler)(void)) 219 { 220 hv_kexec_handler = handler; 221 } 222 223 void hv_remove_kexec_handler(void) 224 { 225 hv_kexec_handler = NULL; 226 } 227 228 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 229 { 230 hv_crash_handler = handler; 231 } 232 233 void hv_remove_crash_handler(void) 234 { 235 hv_crash_handler = NULL; 236 } 237 238 #ifdef CONFIG_KEXEC_CORE 239 static void hv_machine_shutdown(void) 240 { 241 if (kexec_in_progress) { 242 hv_stimer_global_cleanup(); 243 244 if (hv_kexec_handler) 245 hv_kexec_handler(); 246 } 247 248 /* 249 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 250 * corrupts the old VP Assist Pages and can crash the kexec kernel. 251 */ 252 if (kexec_in_progress) 253 cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE); 254 255 /* The function calls stop_other_cpus(). */ 256 native_machine_shutdown(); 257 258 /* Disable the hypercall page when there is only 1 active CPU. */ 259 if (kexec_in_progress) 260 hyperv_cleanup(); 261 } 262 #endif /* CONFIG_KEXEC_CORE */ 263 264 #ifdef CONFIG_CRASH_DUMP 265 static void hv_guest_crash_shutdown(struct pt_regs *regs) 266 { 267 if (hv_crash_handler) 268 hv_crash_handler(regs); 269 270 /* The function calls crash_smp_send_stop(). */ 271 native_machine_crash_shutdown(regs); 272 273 /* Disable the hypercall page when there is only 1 active CPU. */ 274 hyperv_cleanup(); 275 } 276 #endif /* CONFIG_CRASH_DUMP */ 277 278 static u64 hv_ref_counter_at_suspend; 279 static void (*old_save_sched_clock_state)(void); 280 static void (*old_restore_sched_clock_state)(void); 281 282 /* 283 * Hyper-V clock counter resets during hibernation. Save and restore clock 284 * offset during suspend/resume, while also considering the time passed 285 * before suspend. This is to make sure that sched_clock using hv tsc page 286 * based clocksource, proceeds from where it left off during suspend and 287 * it shows correct time for the timestamps of kernel messages after resume. 288 */ 289 static void save_hv_clock_tsc_state(void) 290 { 291 hv_ref_counter_at_suspend = hv_read_reference_counter(); 292 } 293 294 static void restore_hv_clock_tsc_state(void) 295 { 296 /* 297 * Adjust the offsets used by hv tsc clocksource to 298 * account for the time spent before hibernation. 299 * adjusted value = reference counter (time) at suspend 300 * - reference counter (time) now. 301 */ 302 hv_adj_sched_clock_offset(hv_ref_counter_at_suspend - hv_read_reference_counter()); 303 } 304 305 /* 306 * Functions to override save_sched_clock_state and restore_sched_clock_state 307 * functions of x86_platform. The Hyper-V clock counter is reset during 308 * suspend-resume and the offset used to measure time needs to be 309 * corrected, post resume. 310 */ 311 static void hv_save_sched_clock_state(void) 312 { 313 old_save_sched_clock_state(); 314 save_hv_clock_tsc_state(); 315 } 316 317 static void hv_restore_sched_clock_state(void) 318 { 319 restore_hv_clock_tsc_state(); 320 old_restore_sched_clock_state(); 321 } 322 323 static void __init x86_setup_ops_for_tsc_pg_clock(void) 324 { 325 if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE)) 326 return; 327 328 old_save_sched_clock_state = x86_platform.save_sched_clock_state; 329 x86_platform.save_sched_clock_state = hv_save_sched_clock_state; 330 331 old_restore_sched_clock_state = x86_platform.restore_sched_clock_state; 332 x86_platform.restore_sched_clock_state = hv_restore_sched_clock_state; 333 } 334 335 #ifdef CONFIG_X86_64 336 DEFINE_STATIC_CALL(hv_hypercall, hv_std_hypercall); 337 EXPORT_STATIC_CALL_TRAMP_GPL(hv_hypercall); 338 #define hypercall_update(hc) static_call_update(hv_hypercall, hc) 339 #endif 340 #endif /* CONFIG_HYPERV */ 341 342 #ifndef hypercall_update 343 #define hypercall_update(hc) (void)hc 344 #endif 345 346 static uint32_t __init ms_hyperv_platform(void) 347 { 348 u32 eax; 349 u32 hyp_signature[3]; 350 351 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 352 return 0; 353 354 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 355 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 356 357 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 358 memcmp("Microsoft Hv", hyp_signature, 12)) 359 return 0; 360 361 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 362 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 363 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 364 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 365 return 0; 366 } 367 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 368 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 369 return 0; 370 } 371 372 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 373 } 374 375 #ifdef CONFIG_X86_LOCAL_APIC 376 /* 377 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 378 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 379 * unknown NMI on the first CPU which gets it. 380 */ 381 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 382 { 383 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 384 unsigned int old_cpu, this_cpu; 385 386 if (!unknown_nmi_panic) 387 return NMI_DONE; 388 389 old_cpu = -1; 390 this_cpu = raw_smp_processor_id(); 391 if (!atomic_try_cmpxchg(&nmi_cpu, &old_cpu, this_cpu)) 392 return NMI_HANDLED; 393 394 return NMI_DONE; 395 } 396 #endif 397 398 static unsigned long hv_get_tsc_khz(void) 399 { 400 unsigned long freq; 401 402 rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq); 403 404 return freq / 1000; 405 } 406 407 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 408 static void __init hv_smp_prepare_boot_cpu(void) 409 { 410 native_smp_prepare_boot_cpu(); 411 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 412 hv_init_spinlocks(); 413 #endif 414 } 415 416 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 417 { 418 #ifdef CONFIG_X86_64 419 int i; 420 int ret; 421 #endif 422 423 native_smp_prepare_cpus(max_cpus); 424 425 /* 426 * Override wakeup_secondary_cpu_64 callback for SEV-SNP 427 * enlightened guest. 428 */ 429 if (!ms_hyperv.paravisor_present && hv_isolation_type_snp()) { 430 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap; 431 return; 432 } 433 434 #ifdef CONFIG_X86_64 435 /* If AP LPs exist, we are in a kexec'd kernel and VPs already exist */ 436 if (num_present_cpus() == 1 || hv_lp_exists(1)) 437 return; 438 439 for_each_present_cpu(i) { 440 if (i == 0) 441 continue; 442 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 443 BUG_ON(ret); 444 } 445 446 ret = hv_call_notify_all_processors_started(); 447 WARN_ON(ret); 448 449 for_each_present_cpu(i) { 450 if (i == 0) 451 continue; 452 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 453 BUG_ON(ret); 454 } 455 #endif 456 } 457 #endif 458 459 /* 460 * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the 461 * HW_REDUCED flag: refer to acpi_tb_create_local_fadt(). Consequently ttyS0 462 * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns 463 * NULL for ttyS0. This happens because mp_config_acpi_legacy_irqs() sees a 464 * nr_legacy_irqs() of 0, so it doesn't initialize the array 'mp_irqs[]', and 465 * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs 466 * from the array and hence doesn't create the necessary irq description info. 467 * 468 * Clone arch/x86/kernel/acpi/boot.c: acpi_generic_reduced_hw_init() here, 469 * except don't change 'legacy_pic', which keeps its default value 470 * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero 471 * nr_legacy_irqs() and eventually serial console interrupts works properly. 472 */ 473 static void __init reduced_hw_init(void) 474 { 475 x86_init.timers.timer_init = x86_init_noop; 476 x86_init.irqs.pre_vector_init = x86_init_noop; 477 } 478 479 int hv_get_hypervisor_version(union hv_hypervisor_version_info *info) 480 { 481 unsigned int hv_max_functions; 482 483 hv_max_functions = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 484 if (hv_max_functions < HYPERV_CPUID_VERSION) { 485 pr_err("%s: Could not detect Hyper-V version\n", __func__); 486 return -ENODEV; 487 } 488 489 cpuid(HYPERV_CPUID_VERSION, &info->eax, &info->ebx, &info->ecx, &info->edx); 490 491 return 0; 492 } 493 EXPORT_SYMBOL_GPL(hv_get_hypervisor_version); 494 495 /* 496 * Reserved vectors hard coded in the hypervisor. If used outside, the hypervisor 497 * will either crash or hang or attempt to break into debugger. 498 */ 499 static void hv_reserve_irq_vectors(void) 500 { 501 #define HYPERV_DBG_FASTFAIL_VECTOR 0x29 502 #define HYPERV_DBG_ASSERT_VECTOR 0x2C 503 #define HYPERV_DBG_SERVICE_VECTOR 0x2D 504 505 /* 506 * The hypervisor delivers these three to the NT HAL and refuses to 507 * map a device interrupt to any of them. 508 * 509 * The hypervisor will provide a hint in the future when these 510 * vectors become available to use. 511 */ 512 #define HAL_NT_APC_VECTOR 0x1F 513 #define HAL_NT_DPC_VECTOR 0x2F 514 #define HAL_NT_CLOCK_IPI_VECTOR 0xD2 515 516 if (cpu_feature_enabled(X86_FEATURE_FRED)) 517 return; 518 519 if (test_and_set_bit(HYPERV_DBG_ASSERT_VECTOR, system_vectors) || 520 test_and_set_bit(HYPERV_DBG_SERVICE_VECTOR, system_vectors) || 521 test_and_set_bit(HYPERV_DBG_FASTFAIL_VECTOR, system_vectors) || 522 test_and_set_bit(HAL_NT_APC_VECTOR, system_vectors) || 523 test_and_set_bit(HAL_NT_DPC_VECTOR, system_vectors) || 524 test_and_set_bit(HAL_NT_CLOCK_IPI_VECTOR, system_vectors)) 525 BUG(); 526 527 pr_info("Hyper-V: reserve vectors: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 528 HYPERV_DBG_ASSERT_VECTOR, HYPERV_DBG_SERVICE_VECTOR, 529 HYPERV_DBG_FASTFAIL_VECTOR, HAL_NT_APC_VECTOR, 530 HAL_NT_DPC_VECTOR, HAL_NT_CLOCK_IPI_VECTOR); 531 } 532 533 static void __init ms_hyperv_init_platform(void) 534 { 535 int hv_max_functions_eax, eax; 536 537 #ifdef CONFIG_PARAVIRT 538 pv_info.name = "Hyper-V"; 539 #endif 540 541 /* 542 * Extract the features and hints 543 */ 544 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 545 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 546 ms_hyperv.ext_features = cpuid_ecx(HYPERV_CPUID_FEATURES); 547 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 548 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 549 550 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 551 552 pr_info("Hyper-V: privilege flags low %#x, high %#x, ext %#x, hints %#x, misc %#x\n", 553 ms_hyperv.features, ms_hyperv.priv_high, 554 ms_hyperv.ext_features, ms_hyperv.hints, 555 ms_hyperv.misc_features); 556 557 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 558 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 559 560 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 561 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 562 563 hv_identify_partition_type(); 564 565 if (hv_root_partition()) 566 hv_reserve_irq_vectors(); 567 568 if (cc_platform_has(CC_ATTR_SNP_SECURE_AVIC)) 569 ms_hyperv.hints |= HV_DEPRECATING_AEOI_RECOMMENDED; 570 571 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 572 hv_nested = true; 573 pr_info("Hyper-V: running on a nested hypervisor\n"); 574 } 575 576 /* 577 * There is no check against the max function for HYPERV_CPUID_VIRT_STACK_* CPUID 578 * leaves as the hypervisor doesn't handle them. Even a nested root partition (L2 579 * root) will not get them because the nested (L1) hypervisor filters them out. 580 * These are handled through intercept processing by the Windows Hyper-V stack 581 * or the paravisor. 582 */ 583 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 584 ms_hyperv.confidential_vmbus_available = 585 eax & HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE; 586 ms_hyperv.msi_ext_dest_id = 587 eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 588 589 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 590 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 591 x86_platform.calibrate_tsc = hv_get_tsc_khz; 592 x86_platform.calibrate_cpu = hv_get_tsc_khz; 593 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 594 } 595 596 if (ms_hyperv.priv_high & HV_ISOLATION) { 597 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 598 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 599 600 if (ms_hyperv.shared_gpa_boundary_active) 601 ms_hyperv.shared_gpa_boundary = 602 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 603 604 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 605 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 606 607 608 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) { 609 static_branch_enable(&isolation_type_snp); 610 if (!ms_hyperv.paravisor_present) 611 hypercall_update(hv_snp_hypercall); 612 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) { 613 static_branch_enable(&isolation_type_tdx); 614 615 /* A TDX VM must use x2APIC and doesn't use lazy EOI. */ 616 ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED; 617 618 if (!ms_hyperv.paravisor_present) { 619 hypercall_update(hv_tdx_hypercall); 620 /* 621 * Mark the Hyper-V TSC page feature as disabled 622 * in a TDX VM without paravisor so that the 623 * Invariant TSC, which is a better clocksource 624 * anyway, is used instead. 625 */ 626 ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE; 627 628 /* 629 * The Invariant TSC is expected to be available 630 * in a TDX VM without paravisor, but if not, 631 * print a warning message. The slower Hyper-V MSR-based 632 * Ref Counter should end up being the clocksource. 633 */ 634 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 635 pr_warn("Hyper-V: Invariant TSC is unavailable\n"); 636 637 /* HV_MSR_CRASH_CTL is unsupported. */ 638 ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE; 639 640 /* Don't trust Hyper-V's TLB-flushing hypercalls. */ 641 ms_hyperv.hints &= ~HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED; 642 643 x86_init.acpi.reduced_hw_early_init = reduced_hw_init; 644 } 645 } 646 } 647 648 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 649 ms_hyperv.nested_features = 650 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 651 pr_info("Hyper-V: Nested features: 0x%x\n", 652 ms_hyperv.nested_features); 653 } 654 655 #ifdef CONFIG_X86_LOCAL_APIC 656 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 657 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 658 /* 659 * Get the APIC frequency. 660 */ 661 u64 hv_lapic_frequency; 662 663 rdmsrq(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 664 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 665 lapic_timer_period = hv_lapic_frequency; 666 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 667 lapic_timer_period); 668 } 669 670 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 671 "hv_nmi_unknown"); 672 #endif 673 674 #ifdef CONFIG_X86_IO_APIC 675 no_timer_check = 1; 676 #endif 677 678 #if IS_ENABLED(CONFIG_HYPERV) 679 if (hv_root_partition()) 680 machine_ops.power_off = hv_machine_power_off; 681 #if defined(CONFIG_KEXEC_CORE) 682 machine_ops.shutdown = hv_machine_shutdown; 683 #endif 684 #if defined(CONFIG_CRASH_DUMP) 685 if (!hv_root_partition()) 686 machine_ops.crash_shutdown = hv_guest_crash_shutdown; 687 #endif 688 #endif 689 /* 690 * HV_ACCESS_TSC_INVARIANT is always zero for the root partition. Root 691 * partition doesn't need to write to synthetic MSR to enable invariant 692 * TSC feature. It sees what the hardware provides. 693 */ 694 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 695 /* 696 * Writing to synthetic MSR 0x40000118 updates/changes the 697 * guest visible CPUIDs. Setting bit 0 of this MSR enables 698 * guests to report invariant TSC feature through CPUID 699 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 700 * early_init_intel() where this bit is examined. The 701 * setting of this MSR bit should happen before init_intel() 702 * is called. 703 */ 704 wrmsrq(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 705 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 706 } 707 708 /* 709 * Generation 2 instances don't support reading the NMI status from 710 * 0x61 port. 711 */ 712 if (efi_enabled(EFI_BOOT)) 713 x86_platform.get_nmi_reason = hv_get_nmi_reason; 714 715 #if IS_ENABLED(CONFIG_HYPERV) 716 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) || 717 ms_hyperv.paravisor_present) 718 hv_vtom_init(); 719 /* 720 * Setup the hook to get control post apic initialization. 721 */ 722 x86_platform.apic_post_init = hyperv_init; 723 hyperv_setup_mmu_ops(); 724 725 /* Install system interrupt handler for hypervisor callback */ 726 sysvec_install(HYPERVISOR_CALLBACK_VECTOR, sysvec_hyperv_callback); 727 728 /* Install system interrupt handler for reenlightenment notifications */ 729 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 730 sysvec_install(HYPERV_REENLIGHTENMENT_VECTOR, sysvec_hyperv_reenlightenment); 731 } 732 733 /* Install system interrupt handler for stimer0 */ 734 sysvec_install(HYPERV_STIMER0_VECTOR, sysvec_hyperv_stimer0); 735 736 # ifdef CONFIG_SMP 737 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 738 if (hv_root_partition() || 739 (!ms_hyperv.paravisor_present && hv_isolation_type_snp())) 740 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 741 # endif 742 743 /* 744 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 745 * set x2apic destination mode to physical mode when x2apic is available 746 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 747 * have 8-bit APIC id. 748 */ 749 # ifdef CONFIG_X86_X2APIC 750 if (x2apic_supported()) 751 x2apic_phys = 1; 752 # endif 753 754 /* Register Hyper-V specific clocksource */ 755 hv_init_clocksource(); 756 x86_setup_ops_for_tsc_pg_clock(); 757 hv_vtl_init_platform(); 758 #endif 759 /* 760 * TSC should be marked as unstable only after Hyper-V 761 * clocksource has been initialized. This ensures that the 762 * stability of the sched_clock is not altered. 763 * 764 * HV_ACCESS_TSC_INVARIANT is always zero for the root partition. No 765 * need to check for it. 766 */ 767 if (!hv_root_partition() && 768 !(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 769 mark_tsc_unstable("running on Hyper-V"); 770 771 hardlockup_detector_disable(); 772 } 773 774 static bool __init ms_hyperv_x2apic_available(void) 775 { 776 return x2apic_supported(); 777 } 778 779 /* 780 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 781 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 782 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 783 * 784 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 785 * (logically) generates MSIs directly to the system APIC irq domain. 786 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 787 * pci-hyperv host bridge. 788 * 789 * Note: for a Hyper-V root partition, this will always return false. 790 */ 791 static bool __init ms_hyperv_msi_ext_dest_id(void) 792 { 793 return ms_hyperv.msi_ext_dest_id; 794 } 795 796 #ifdef CONFIG_AMD_MEM_ENCRYPT 797 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs) 798 { 799 /* RAX and CPL are already in the GHCB */ 800 ghcb_set_rcx(ghcb, regs->cx); 801 ghcb_set_rdx(ghcb, regs->dx); 802 ghcb_set_r8(ghcb, regs->r8); 803 } 804 805 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs) 806 { 807 /* No checking of the return state needed */ 808 return true; 809 } 810 #endif 811 812 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 813 .name = "Microsoft Hyper-V", 814 .detect = ms_hyperv_platform, 815 .type = X86_HYPER_MS_HYPERV, 816 .init.x2apic_available = ms_hyperv_x2apic_available, 817 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 818 .init.init_platform = ms_hyperv_init_platform, 819 .init.guest_late_init = ms_hyperv_late_init, 820 #ifdef CONFIG_AMD_MEM_ENCRYPT 821 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare, 822 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish, 823 #endif 824 }; 825