1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/random.h> 20 #include <asm/processor.h> 21 #include <asm/hypervisor.h> 22 #include <hyperv/hvhdk.h> 23 #include <asm/mshyperv.h> 24 #include <asm/desc.h> 25 #include <asm/idtentry.h> 26 #include <asm/irq_regs.h> 27 #include <asm/i8259.h> 28 #include <asm/apic.h> 29 #include <asm/timer.h> 30 #include <asm/reboot.h> 31 #include <asm/nmi.h> 32 #include <clocksource/hyperv_timer.h> 33 #include <asm/numa.h> 34 #include <asm/svm.h> 35 36 /* Is Linux running on nested Microsoft Hypervisor */ 37 bool hv_nested; 38 struct ms_hyperv_info ms_hyperv; 39 40 /* Used in modules via hv_do_hypercall(): see arch/x86/include/asm/mshyperv.h */ 41 bool hyperv_paravisor_present __ro_after_init; 42 EXPORT_SYMBOL_GPL(hyperv_paravisor_present); 43 44 #if IS_ENABLED(CONFIG_HYPERV) 45 static inline unsigned int hv_get_nested_msr(unsigned int reg) 46 { 47 if (hv_is_sint_msr(reg)) 48 return reg - HV_X64_MSR_SINT0 + HV_X64_MSR_NESTED_SINT0; 49 50 switch (reg) { 51 case HV_X64_MSR_SIMP: 52 return HV_X64_MSR_NESTED_SIMP; 53 case HV_X64_MSR_SIEFP: 54 return HV_X64_MSR_NESTED_SIEFP; 55 case HV_X64_MSR_SVERSION: 56 return HV_X64_MSR_NESTED_SVERSION; 57 case HV_X64_MSR_SCONTROL: 58 return HV_X64_MSR_NESTED_SCONTROL; 59 case HV_X64_MSR_EOM: 60 return HV_X64_MSR_NESTED_EOM; 61 default: 62 return reg; 63 } 64 } 65 66 u64 hv_get_non_nested_msr(unsigned int reg) 67 { 68 u64 value; 69 70 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) 71 hv_ivm_msr_read(reg, &value); 72 else 73 rdmsrl(reg, value); 74 return value; 75 } 76 EXPORT_SYMBOL_GPL(hv_get_non_nested_msr); 77 78 void hv_set_non_nested_msr(unsigned int reg, u64 value) 79 { 80 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) { 81 hv_ivm_msr_write(reg, value); 82 83 /* Write proxy bit via wrmsl instruction */ 84 if (hv_is_sint_msr(reg)) 85 wrmsrl(reg, value | 1 << 20); 86 } else { 87 wrmsrl(reg, value); 88 } 89 } 90 EXPORT_SYMBOL_GPL(hv_set_non_nested_msr); 91 92 u64 hv_get_msr(unsigned int reg) 93 { 94 if (hv_nested) 95 reg = hv_get_nested_msr(reg); 96 97 return hv_get_non_nested_msr(reg); 98 } 99 EXPORT_SYMBOL_GPL(hv_get_msr); 100 101 void hv_set_msr(unsigned int reg, u64 value) 102 { 103 if (hv_nested) 104 reg = hv_get_nested_msr(reg); 105 106 hv_set_non_nested_msr(reg, value); 107 } 108 EXPORT_SYMBOL_GPL(hv_set_msr); 109 110 static void (*vmbus_handler)(void); 111 static void (*hv_stimer0_handler)(void); 112 static void (*hv_kexec_handler)(void); 113 static void (*hv_crash_handler)(struct pt_regs *regs); 114 115 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 116 { 117 struct pt_regs *old_regs = set_irq_regs(regs); 118 119 inc_irq_stat(irq_hv_callback_count); 120 if (vmbus_handler) 121 vmbus_handler(); 122 123 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 124 apic_eoi(); 125 126 set_irq_regs(old_regs); 127 } 128 129 void hv_setup_vmbus_handler(void (*handler)(void)) 130 { 131 vmbus_handler = handler; 132 } 133 134 void hv_remove_vmbus_handler(void) 135 { 136 /* We have no way to deallocate the interrupt gate */ 137 vmbus_handler = NULL; 138 } 139 140 /* 141 * Routines to do per-architecture handling of stimer0 142 * interrupts when in Direct Mode 143 */ 144 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 145 { 146 struct pt_regs *old_regs = set_irq_regs(regs); 147 148 inc_irq_stat(hyperv_stimer0_count); 149 if (hv_stimer0_handler) 150 hv_stimer0_handler(); 151 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 152 apic_eoi(); 153 154 set_irq_regs(old_regs); 155 } 156 157 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 158 void hv_setup_stimer0_handler(void (*handler)(void)) 159 { 160 hv_stimer0_handler = handler; 161 } 162 163 void hv_remove_stimer0_handler(void) 164 { 165 /* We have no way to deallocate the interrupt gate */ 166 hv_stimer0_handler = NULL; 167 } 168 169 void hv_setup_kexec_handler(void (*handler)(void)) 170 { 171 hv_kexec_handler = handler; 172 } 173 174 void hv_remove_kexec_handler(void) 175 { 176 hv_kexec_handler = NULL; 177 } 178 179 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 180 { 181 hv_crash_handler = handler; 182 } 183 184 void hv_remove_crash_handler(void) 185 { 186 hv_crash_handler = NULL; 187 } 188 189 #ifdef CONFIG_KEXEC_CORE 190 static void hv_machine_shutdown(void) 191 { 192 if (kexec_in_progress && hv_kexec_handler) 193 hv_kexec_handler(); 194 195 /* 196 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 197 * corrupts the old VP Assist Pages and can crash the kexec kernel. 198 */ 199 if (kexec_in_progress) 200 cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE); 201 202 /* The function calls stop_other_cpus(). */ 203 native_machine_shutdown(); 204 205 /* Disable the hypercall page when there is only 1 active CPU. */ 206 if (kexec_in_progress) 207 hyperv_cleanup(); 208 } 209 #endif /* CONFIG_KEXEC_CORE */ 210 211 #ifdef CONFIG_CRASH_DUMP 212 static void hv_machine_crash_shutdown(struct pt_regs *regs) 213 { 214 if (hv_crash_handler) 215 hv_crash_handler(regs); 216 217 /* The function calls crash_smp_send_stop(). */ 218 native_machine_crash_shutdown(regs); 219 220 /* Disable the hypercall page when there is only 1 active CPU. */ 221 hyperv_cleanup(); 222 } 223 #endif /* CONFIG_CRASH_DUMP */ 224 225 static u64 hv_ref_counter_at_suspend; 226 static void (*old_save_sched_clock_state)(void); 227 static void (*old_restore_sched_clock_state)(void); 228 229 /* 230 * Hyper-V clock counter resets during hibernation. Save and restore clock 231 * offset during suspend/resume, while also considering the time passed 232 * before suspend. This is to make sure that sched_clock using hv tsc page 233 * based clocksource, proceeds from where it left off during suspend and 234 * it shows correct time for the timestamps of kernel messages after resume. 235 */ 236 static void save_hv_clock_tsc_state(void) 237 { 238 hv_ref_counter_at_suspend = hv_read_reference_counter(); 239 } 240 241 static void restore_hv_clock_tsc_state(void) 242 { 243 /* 244 * Adjust the offsets used by hv tsc clocksource to 245 * account for the time spent before hibernation. 246 * adjusted value = reference counter (time) at suspend 247 * - reference counter (time) now. 248 */ 249 hv_adj_sched_clock_offset(hv_ref_counter_at_suspend - hv_read_reference_counter()); 250 } 251 252 /* 253 * Functions to override save_sched_clock_state and restore_sched_clock_state 254 * functions of x86_platform. The Hyper-V clock counter is reset during 255 * suspend-resume and the offset used to measure time needs to be 256 * corrected, post resume. 257 */ 258 static void hv_save_sched_clock_state(void) 259 { 260 old_save_sched_clock_state(); 261 save_hv_clock_tsc_state(); 262 } 263 264 static void hv_restore_sched_clock_state(void) 265 { 266 restore_hv_clock_tsc_state(); 267 old_restore_sched_clock_state(); 268 } 269 270 static void __init x86_setup_ops_for_tsc_pg_clock(void) 271 { 272 if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE)) 273 return; 274 275 old_save_sched_clock_state = x86_platform.save_sched_clock_state; 276 x86_platform.save_sched_clock_state = hv_save_sched_clock_state; 277 278 old_restore_sched_clock_state = x86_platform.restore_sched_clock_state; 279 x86_platform.restore_sched_clock_state = hv_restore_sched_clock_state; 280 } 281 #endif /* CONFIG_HYPERV */ 282 283 static uint32_t __init ms_hyperv_platform(void) 284 { 285 u32 eax; 286 u32 hyp_signature[3]; 287 288 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 289 return 0; 290 291 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 292 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 293 294 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 295 memcmp("Microsoft Hv", hyp_signature, 12)) 296 return 0; 297 298 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 299 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 300 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 301 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 302 return 0; 303 } 304 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 305 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 306 return 0; 307 } 308 309 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 310 } 311 312 #ifdef CONFIG_X86_LOCAL_APIC 313 /* 314 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 315 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 316 * unknown NMI on the first CPU which gets it. 317 */ 318 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 319 { 320 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 321 unsigned int old_cpu, this_cpu; 322 323 if (!unknown_nmi_panic) 324 return NMI_DONE; 325 326 old_cpu = -1; 327 this_cpu = raw_smp_processor_id(); 328 if (!atomic_try_cmpxchg(&nmi_cpu, &old_cpu, this_cpu)) 329 return NMI_HANDLED; 330 331 return NMI_DONE; 332 } 333 #endif 334 335 static unsigned long hv_get_tsc_khz(void) 336 { 337 unsigned long freq; 338 339 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 340 341 return freq / 1000; 342 } 343 344 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 345 static void __init hv_smp_prepare_boot_cpu(void) 346 { 347 native_smp_prepare_boot_cpu(); 348 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 349 hv_init_spinlocks(); 350 #endif 351 } 352 353 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 354 { 355 #ifdef CONFIG_X86_64 356 int i; 357 int ret; 358 #endif 359 360 native_smp_prepare_cpus(max_cpus); 361 362 /* 363 * Override wakeup_secondary_cpu_64 callback for SEV-SNP 364 * enlightened guest. 365 */ 366 if (!ms_hyperv.paravisor_present && hv_isolation_type_snp()) { 367 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap; 368 return; 369 } 370 371 #ifdef CONFIG_X86_64 372 for_each_present_cpu(i) { 373 if (i == 0) 374 continue; 375 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 376 BUG_ON(ret); 377 } 378 379 for_each_present_cpu(i) { 380 if (i == 0) 381 continue; 382 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 383 BUG_ON(ret); 384 } 385 #endif 386 } 387 #endif 388 389 /* 390 * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the 391 * HW_REDUCED flag: refer to acpi_tb_create_local_fadt(). Consequently ttyS0 392 * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns 393 * NULL for ttyS0. This happens because mp_config_acpi_legacy_irqs() sees a 394 * nr_legacy_irqs() of 0, so it doesn't initialize the array 'mp_irqs[]', and 395 * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs 396 * from the array and hence doesn't create the necessary irq description info. 397 * 398 * Clone arch/x86/kernel/acpi/boot.c: acpi_generic_reduced_hw_init() here, 399 * except don't change 'legacy_pic', which keeps its default value 400 * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero 401 * nr_legacy_irqs() and eventually serial console interrupts works properly. 402 */ 403 static void __init reduced_hw_init(void) 404 { 405 x86_init.timers.timer_init = x86_init_noop; 406 x86_init.irqs.pre_vector_init = x86_init_noop; 407 } 408 409 int hv_get_hypervisor_version(union hv_hypervisor_version_info *info) 410 { 411 unsigned int hv_max_functions; 412 413 hv_max_functions = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 414 if (hv_max_functions < HYPERV_CPUID_VERSION) { 415 pr_err("%s: Could not detect Hyper-V version\n", __func__); 416 return -ENODEV; 417 } 418 419 cpuid(HYPERV_CPUID_VERSION, &info->eax, &info->ebx, &info->ecx, &info->edx); 420 421 return 0; 422 } 423 EXPORT_SYMBOL_GPL(hv_get_hypervisor_version); 424 425 static void __init ms_hyperv_init_platform(void) 426 { 427 int hv_max_functions_eax; 428 429 #ifdef CONFIG_PARAVIRT 430 pv_info.name = "Hyper-V"; 431 #endif 432 433 /* 434 * Extract the features and hints 435 */ 436 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 437 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 438 ms_hyperv.ext_features = cpuid_ecx(HYPERV_CPUID_FEATURES); 439 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 440 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 441 442 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 443 444 pr_info("Hyper-V: privilege flags low %#x, high %#x, ext %#x, hints %#x, misc %#x\n", 445 ms_hyperv.features, ms_hyperv.priv_high, 446 ms_hyperv.ext_features, ms_hyperv.hints, 447 ms_hyperv.misc_features); 448 449 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 450 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 451 452 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 453 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 454 455 hv_identify_partition_type(); 456 457 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 458 hv_nested = true; 459 pr_info("Hyper-V: running on a nested hypervisor\n"); 460 } 461 462 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 463 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 464 x86_platform.calibrate_tsc = hv_get_tsc_khz; 465 x86_platform.calibrate_cpu = hv_get_tsc_khz; 466 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 467 } 468 469 if (ms_hyperv.priv_high & HV_ISOLATION) { 470 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 471 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 472 473 if (ms_hyperv.shared_gpa_boundary_active) 474 ms_hyperv.shared_gpa_boundary = 475 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 476 477 hyperv_paravisor_present = !!ms_hyperv.paravisor_present; 478 479 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 480 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 481 482 483 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) { 484 static_branch_enable(&isolation_type_snp); 485 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) { 486 static_branch_enable(&isolation_type_tdx); 487 488 /* A TDX VM must use x2APIC and doesn't use lazy EOI. */ 489 ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED; 490 491 if (!ms_hyperv.paravisor_present) { 492 /* 493 * Mark the Hyper-V TSC page feature as disabled 494 * in a TDX VM without paravisor so that the 495 * Invariant TSC, which is a better clocksource 496 * anyway, is used instead. 497 */ 498 ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE; 499 500 /* 501 * The Invariant TSC is expected to be available 502 * in a TDX VM without paravisor, but if not, 503 * print a warning message. The slower Hyper-V MSR-based 504 * Ref Counter should end up being the clocksource. 505 */ 506 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 507 pr_warn("Hyper-V: Invariant TSC is unavailable\n"); 508 509 /* HV_MSR_CRASH_CTL is unsupported. */ 510 ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE; 511 512 /* Don't trust Hyper-V's TLB-flushing hypercalls. */ 513 ms_hyperv.hints &= ~HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED; 514 515 x86_init.acpi.reduced_hw_early_init = reduced_hw_init; 516 } 517 } 518 } 519 520 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 521 ms_hyperv.nested_features = 522 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 523 pr_info("Hyper-V: Nested features: 0x%x\n", 524 ms_hyperv.nested_features); 525 } 526 527 #ifdef CONFIG_X86_LOCAL_APIC 528 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 529 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 530 /* 531 * Get the APIC frequency. 532 */ 533 u64 hv_lapic_frequency; 534 535 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 536 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 537 lapic_timer_period = hv_lapic_frequency; 538 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 539 lapic_timer_period); 540 } 541 542 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 543 "hv_nmi_unknown"); 544 #endif 545 546 #ifdef CONFIG_X86_IO_APIC 547 no_timer_check = 1; 548 #endif 549 550 #if IS_ENABLED(CONFIG_HYPERV) 551 #if defined(CONFIG_KEXEC_CORE) 552 machine_ops.shutdown = hv_machine_shutdown; 553 #endif 554 #if defined(CONFIG_CRASH_DUMP) 555 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 556 #endif 557 #endif 558 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 559 /* 560 * Writing to synthetic MSR 0x40000118 updates/changes the 561 * guest visible CPUIDs. Setting bit 0 of this MSR enables 562 * guests to report invariant TSC feature through CPUID 563 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 564 * early_init_intel() where this bit is examined. The 565 * setting of this MSR bit should happen before init_intel() 566 * is called. 567 */ 568 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 569 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 570 } 571 572 /* 573 * Generation 2 instances don't support reading the NMI status from 574 * 0x61 port. 575 */ 576 if (efi_enabled(EFI_BOOT)) 577 x86_platform.get_nmi_reason = hv_get_nmi_reason; 578 579 #if IS_ENABLED(CONFIG_HYPERV) 580 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) || 581 ms_hyperv.paravisor_present) 582 hv_vtom_init(); 583 /* 584 * Setup the hook to get control post apic initialization. 585 */ 586 x86_platform.apic_post_init = hyperv_init; 587 hyperv_setup_mmu_ops(); 588 589 /* Install system interrupt handler for hypervisor callback */ 590 sysvec_install(HYPERVISOR_CALLBACK_VECTOR, sysvec_hyperv_callback); 591 592 /* Install system interrupt handler for reenlightenment notifications */ 593 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 594 sysvec_install(HYPERV_REENLIGHTENMENT_VECTOR, sysvec_hyperv_reenlightenment); 595 } 596 597 /* Install system interrupt handler for stimer0 */ 598 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 599 sysvec_install(HYPERV_STIMER0_VECTOR, sysvec_hyperv_stimer0); 600 } 601 602 # ifdef CONFIG_SMP 603 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 604 if (hv_root_partition() || 605 (!ms_hyperv.paravisor_present && hv_isolation_type_snp())) 606 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 607 # endif 608 609 /* 610 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 611 * set x2apic destination mode to physical mode when x2apic is available 612 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 613 * have 8-bit APIC id. 614 */ 615 # ifdef CONFIG_X86_X2APIC 616 if (x2apic_supported()) 617 x2apic_phys = 1; 618 # endif 619 620 /* Register Hyper-V specific clocksource */ 621 hv_init_clocksource(); 622 x86_setup_ops_for_tsc_pg_clock(); 623 hv_vtl_init_platform(); 624 #endif 625 /* 626 * TSC should be marked as unstable only after Hyper-V 627 * clocksource has been initialized. This ensures that the 628 * stability of the sched_clock is not altered. 629 */ 630 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 631 mark_tsc_unstable("running on Hyper-V"); 632 633 hardlockup_detector_disable(); 634 } 635 636 static bool __init ms_hyperv_x2apic_available(void) 637 { 638 return x2apic_supported(); 639 } 640 641 /* 642 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 643 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 644 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 645 * 646 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 647 * (logically) generates MSIs directly to the system APIC irq domain. 648 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 649 * pci-hyperv host bridge. 650 * 651 * Note: for a Hyper-V root partition, this will always return false. 652 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by 653 * default, they are implemented as intercepts by the Windows Hyper-V stack. 654 * Even a nested root partition (L2 root) will not get them because the 655 * nested (L1) hypervisor filters them out. 656 */ 657 static bool __init ms_hyperv_msi_ext_dest_id(void) 658 { 659 u32 eax; 660 661 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 662 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 663 return false; 664 665 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 666 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 667 } 668 669 #ifdef CONFIG_AMD_MEM_ENCRYPT 670 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs) 671 { 672 /* RAX and CPL are already in the GHCB */ 673 ghcb_set_rcx(ghcb, regs->cx); 674 ghcb_set_rdx(ghcb, regs->dx); 675 ghcb_set_r8(ghcb, regs->r8); 676 } 677 678 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs) 679 { 680 /* No checking of the return state needed */ 681 return true; 682 } 683 #endif 684 685 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 686 .name = "Microsoft Hyper-V", 687 .detect = ms_hyperv_platform, 688 .type = X86_HYPER_MS_HYPERV, 689 .init.x2apic_available = ms_hyperv_x2apic_available, 690 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 691 .init.init_platform = ms_hyperv_init_platform, 692 .init.guest_late_init = ms_hyperv_late_init, 693 #ifdef CONFIG_AMD_MEM_ENCRYPT 694 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare, 695 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish, 696 #endif 697 }; 698