12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2bad5fa63SBorislav Petkov /*
36b44e72aSBorislav Petkov * CPU Microcode Update Driver for Linux
4bad5fa63SBorislav Petkov *
5cea58224SAndrew Morton * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
6bad5fa63SBorislav Petkov * 2006 Shaohua Li <shaohua.li@intel.com>
714cfbe55SBorislav Petkov * 2013-2016 Borislav Petkov <bp@alien8.de>
8bad5fa63SBorislav Petkov *
9fe055896SBorislav Petkov * X86 CPU microcode early update for Linux:
10fe055896SBorislav Petkov *
11fe055896SBorislav Petkov * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
12fe055896SBorislav Petkov * H Peter Anvin" <hpa@zytor.com>
13fe055896SBorislav Petkov * (C) 2015 Borislav Petkov <bp@alien8.de>
14fe055896SBorislav Petkov *
156b44e72aSBorislav Petkov * This driver allows to upgrade microcode on x86 processors.
16bad5fa63SBorislav Petkov */
17bad5fa63SBorislav Petkov
186b26e1bfSBorislav Petkov #define pr_fmt(fmt) "microcode: " fmt
19bad5fa63SBorislav Petkov
20bad5fa63SBorislav Petkov #include <linux/platform_device.h>
21a5321aecSAshok Raj #include <linux/stop_machine.h>
22fe055896SBorislav Petkov #include <linux/syscore_ops.h>
23bad5fa63SBorislav Petkov #include <linux/miscdevice.h>
24bad5fa63SBorislav Petkov #include <linux/capability.h>
25fe055896SBorislav Petkov #include <linux/firmware.h>
267eb314a2SThomas Gleixner #include <linux/cpumask.h>
27bad5fa63SBorislav Petkov #include <linux/kernel.h>
28a5321aecSAshok Raj #include <linux/delay.h>
29bad5fa63SBorislav Petkov #include <linux/mutex.h>
30bad5fa63SBorislav Petkov #include <linux/cpu.h>
31a5321aecSAshok Raj #include <linux/nmi.h>
32bad5fa63SBorislav Petkov #include <linux/fs.h>
33bad5fa63SBorislav Petkov #include <linux/mm.h>
34bad5fa63SBorislav Petkov
357eb314a2SThomas Gleixner #include <asm/apic.h>
36fe055896SBorislav Petkov #include <asm/cpu_device_id.h>
37fe055896SBorislav Petkov #include <asm/perf_event.h>
38bad5fa63SBorislav Petkov #include <asm/processor.h>
39fe055896SBorislav Petkov #include <asm/cmdline.h>
4006b8534cSBorislav Petkov #include <asm/setup.h>
41bad5fa63SBorislav Petkov
42d02a0efdSThomas Gleixner #include "internal.h"
43d02a0efdSThomas Gleixner
44bad5fa63SBorislav Petkov static struct microcode_ops *microcode_ops;
45dd5e3e3cSThomas Gleixner bool dis_ucode_ldr = true;
466b26e1bfSBorislav Petkov
479407bda8SThomas Gleixner bool force_minrev = IS_ENABLED(CONFIG_MICROCODE_LATE_FORCE_MINREV);
489407bda8SThomas Gleixner module_param(force_minrev, bool, S_IRUSR | S_IWUSR);
499407bda8SThomas Gleixner
50bad5fa63SBorislav Petkov /*
51bad5fa63SBorislav Petkov * Synchronization.
52bad5fa63SBorislav Petkov *
53bad5fa63SBorislav Petkov * All non cpu-hotplug-callback call sites use:
54bad5fa63SBorislav Petkov *
552089f34fSSebastian Andrzej Siewior * - cpus_read_lock/unlock() to synchronize with
56bad5fa63SBorislav Petkov * the cpu-hotplug-callback call sites.
57bad5fa63SBorislav Petkov *
58bad5fa63SBorislav Petkov * We guarantee that only a single cpu is being
59bad5fa63SBorislav Petkov * updated at any particular moment of time.
60bad5fa63SBorislav Petkov */
61bad5fa63SBorislav Petkov struct ucode_cpu_info ucode_cpu_info[NR_CPUS];
62bad5fa63SBorislav Petkov
63f3ad136dSBorislav Petkov /*
64f3ad136dSBorislav Petkov * Those patch levels cannot be updated to newer ones and thus should be final.
65f3ad136dSBorislav Petkov */
66f3ad136dSBorislav Petkov static u32 final_levels[] = {
67f3ad136dSBorislav Petkov 0x01000098,
68f3ad136dSBorislav Petkov 0x0100009f,
69f3ad136dSBorislav Petkov 0x010000af,
70f3ad136dSBorislav Petkov 0, /* T-101 terminator */
71f3ad136dSBorislav Petkov };
72f3ad136dSBorislav Petkov
73*080990aaSBorislav Petkov (AMD) struct early_load_data early_data;
74*080990aaSBorislav Petkov (AMD)
75f3ad136dSBorislav Petkov /*
76f3ad136dSBorislav Petkov * Check the current patch level on this CPU.
77f3ad136dSBorislav Petkov *
78f3ad136dSBorislav Petkov * Returns:
79f3ad136dSBorislav Petkov * - true: if update should stop
80f3ad136dSBorislav Petkov * - false: otherwise
81f3ad136dSBorislav Petkov */
amd_check_current_patch_level(void)82f3ad136dSBorislav Petkov static bool amd_check_current_patch_level(void)
83f3ad136dSBorislav Petkov {
84f3ad136dSBorislav Petkov u32 lvl, dummy, i;
85f3ad136dSBorislav Petkov u32 *levels;
86f3ad136dSBorislav Petkov
87f3ad136dSBorislav Petkov native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
88f3ad136dSBorislav Petkov
89f3ad136dSBorislav Petkov levels = final_levels;
90f3ad136dSBorislav Petkov
91f3ad136dSBorislav Petkov for (i = 0; levels[i]; i++) {
92f3ad136dSBorislav Petkov if (lvl == levels[i])
93f3ad136dSBorislav Petkov return true;
94f3ad136dSBorislav Petkov }
95f3ad136dSBorislav Petkov return false;
96f3ad136dSBorislav Petkov }
97f3ad136dSBorislav Petkov
check_loader_disabled_bsp(void)98fe055896SBorislav Petkov static bool __init check_loader_disabled_bsp(void)
99fe055896SBorislav Petkov {
100e8c8165eSBorislav Petkov static const char *__dis_opt_str = "dis_ucode_ldr";
101fe055896SBorislav Petkov const char *cmdline = boot_command_line;
102e8c8165eSBorislav Petkov const char *option = __dis_opt_str;
103fe055896SBorislav Petkov
104a15a7535SBorislav Petkov /*
105a15a7535SBorislav Petkov * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not
106a15a7535SBorislav Petkov * completely accurate as xen pv guests don't see that CPUID bit set but
107a15a7535SBorislav Petkov * that's good enough as they don't land on the BSP path anyway.
108a15a7535SBorislav Petkov */
109309aac77SBorislav Petkov if (native_cpuid_ecx(1) & BIT(31))
1100b62f6cbSThomas Gleixner return true;
111a15a7535SBorislav Petkov
112f3ad136dSBorislav Petkov if (x86_cpuid_vendor() == X86_VENDOR_AMD) {
113f3ad136dSBorislav Petkov if (amd_check_current_patch_level())
1140b62f6cbSThomas Gleixner return true;
115f3ad136dSBorislav Petkov }
116f3ad136dSBorislav Petkov
117a15a7535SBorislav Petkov if (cmdline_find_option_bool(cmdline, option) <= 0)
1180b62f6cbSThomas Gleixner dis_ucode_ldr = false;
119fe055896SBorislav Petkov
1200b62f6cbSThomas Gleixner return dis_ucode_ldr;
121fe055896SBorislav Petkov }
122fe055896SBorislav Petkov
load_ucode_bsp(void)123fe055896SBorislav Petkov void __init load_ucode_bsp(void)
124fe055896SBorislav Petkov {
1257a93a40bSBorislav Petkov unsigned int cpuid_1_eax;
1261f161f67SBorislav Petkov bool intel = true;
127fe055896SBorislav Petkov
1281f161f67SBorislav Petkov if (!have_cpuid_p())
129fe055896SBorislav Petkov return;
130fe055896SBorislav Petkov
131309aac77SBorislav Petkov cpuid_1_eax = native_cpuid_eax(1);
132fe055896SBorislav Petkov
1337a93a40bSBorislav Petkov switch (x86_cpuid_vendor()) {
134fe055896SBorislav Petkov case X86_VENDOR_INTEL:
1351f161f67SBorislav Petkov if (x86_family(cpuid_1_eax) < 6)
1361f161f67SBorislav Petkov return;
137fe055896SBorislav Petkov break;
1381f161f67SBorislav Petkov
139fe055896SBorislav Petkov case X86_VENDOR_AMD:
1401f161f67SBorislav Petkov if (x86_family(cpuid_1_eax) < 0x10)
1411f161f67SBorislav Petkov return;
1421f161f67SBorislav Petkov intel = false;
143fe055896SBorislav Petkov break;
1441f161f67SBorislav Petkov
145fe055896SBorislav Petkov default:
1461f161f67SBorislav Petkov return;
147fe055896SBorislav Petkov }
1481f161f67SBorislav Petkov
1491f161f67SBorislav Petkov if (check_loader_disabled_bsp())
1501f161f67SBorislav Petkov return;
1511f161f67SBorislav Petkov
1521f161f67SBorislav Petkov if (intel)
153*080990aaSBorislav Petkov (AMD) load_ucode_intel_bsp(&early_data);
1541f161f67SBorislav Petkov else
155*080990aaSBorislav Petkov (AMD) load_ucode_amd_bsp(&early_data, cpuid_1_eax);
156fe055896SBorislav Petkov }
157fe055896SBorislav Petkov
load_ucode_ap(void)158fe055896SBorislav Petkov void load_ucode_ap(void)
159fe055896SBorislav Petkov {
1607a93a40bSBorislav Petkov unsigned int cpuid_1_eax;
161fe055896SBorislav Petkov
1620b62f6cbSThomas Gleixner if (dis_ucode_ldr)
163fe055896SBorislav Petkov return;
164fe055896SBorislav Petkov
165309aac77SBorislav Petkov cpuid_1_eax = native_cpuid_eax(1);
166fe055896SBorislav Petkov
1677a93a40bSBorislav Petkov switch (x86_cpuid_vendor()) {
168fe055896SBorislav Petkov case X86_VENDOR_INTEL:
169309aac77SBorislav Petkov if (x86_family(cpuid_1_eax) >= 6)
170fe055896SBorislav Petkov load_ucode_intel_ap();
171fe055896SBorislav Petkov break;
172fe055896SBorislav Petkov case X86_VENDOR_AMD:
173309aac77SBorislav Petkov if (x86_family(cpuid_1_eax) >= 0x10)
1745af05b8dSThomas Gleixner load_ucode_amd_ap(cpuid_1_eax);
175fe055896SBorislav Petkov break;
176fe055896SBorislav Petkov default:
177fe055896SBorislav Petkov break;
178fe055896SBorislav Petkov }
179fe055896SBorislav Petkov }
180fe055896SBorislav Petkov
find_microcode_in_initrd(const char * path)1818529e8abSThomas Gleixner struct cpio_data __init find_microcode_in_initrd(const char *path)
18206b8534cSBorislav Petkov {
18306b8534cSBorislav Petkov #ifdef CONFIG_BLK_DEV_INITRD
18406b8534cSBorislav Petkov unsigned long start = 0;
18506b8534cSBorislav Petkov size_t size;
18606b8534cSBorislav Petkov
18706b8534cSBorislav Petkov #ifdef CONFIG_X86_32
1880b62f6cbSThomas Gleixner size = boot_params.hdr.ramdisk_size;
1890b62f6cbSThomas Gleixner /* Early load on BSP has a temporary mapping. */
19006b8534cSBorislav Petkov if (size)
1910b62f6cbSThomas Gleixner start = initrd_start_early;
19206b8534cSBorislav Petkov
19306b8534cSBorislav Petkov #else /* CONFIG_X86_64 */
19406b8534cSBorislav Petkov size = (unsigned long)boot_params.ext_ramdisk_size << 32;
19506b8534cSBorislav Petkov size |= boot_params.hdr.ramdisk_size;
19606b8534cSBorislav Petkov
19706b8534cSBorislav Petkov if (size) {
19806b8534cSBorislav Petkov start = (unsigned long)boot_params.ext_ramdisk_image << 32;
19906b8534cSBorislav Petkov start |= boot_params.hdr.ramdisk_image;
20006b8534cSBorislav Petkov start += PAGE_OFFSET;
20106b8534cSBorislav Petkov }
20206b8534cSBorislav Petkov #endif
20306b8534cSBorislav Petkov
20406b8534cSBorislav Petkov /*
2058877ebddSBorislav Petkov * Fixup the start address: after reserve_initrd() runs, initrd_start
2068877ebddSBorislav Petkov * has the virtual address of the beginning of the initrd. It also
2078877ebddSBorislav Petkov * possibly relocates the ramdisk. In either case, initrd_start contains
2088877ebddSBorislav Petkov * the updated address so use that instead.
20906b8534cSBorislav Petkov */
21024c25032SBorislav Petkov if (initrd_start)
21106b8534cSBorislav Petkov start = initrd_start;
21206b8534cSBorislav Petkov
21306b8534cSBorislav Petkov return find_cpio_data(path, (void *)start, size, NULL);
21406b8534cSBorislav Petkov #else /* !CONFIG_BLK_DEV_INITRD */
21506b8534cSBorislav Petkov return (struct cpio_data){ NULL, 0, "" };
21606b8534cSBorislav Petkov #endif
21706b8534cSBorislav Petkov }
21806b8534cSBorislav Petkov
reload_early_microcode(unsigned int cpu)21918648dbdSThomas Gleixner static void reload_early_microcode(unsigned int cpu)
220fe055896SBorislav Petkov {
221fe055896SBorislav Petkov int vendor, family;
222fe055896SBorislav Petkov
22399f925ceSBorislav Petkov vendor = x86_cpuid_vendor();
22499f925ceSBorislav Petkov family = x86_cpuid_family();
225fe055896SBorislav Petkov
226fe055896SBorislav Petkov switch (vendor) {
227fe055896SBorislav Petkov case X86_VENDOR_INTEL:
228fe055896SBorislav Petkov if (family >= 6)
229fe055896SBorislav Petkov reload_ucode_intel();
230fe055896SBorislav Petkov break;
231fe055896SBorislav Petkov case X86_VENDOR_AMD:
232fe055896SBorislav Petkov if (family >= 0x10)
233a5ad9213SBorislav Petkov (AMD) reload_ucode_amd(cpu);
234fe055896SBorislav Petkov break;
235fe055896SBorislav Petkov default:
236fe055896SBorislav Petkov break;
237fe055896SBorislav Petkov }
238fe055896SBorislav Petkov }
239fe055896SBorislav Petkov
240bad5fa63SBorislav Petkov /* fake device for request_firmware */
241bad5fa63SBorislav Petkov static struct platform_device *microcode_pdev;
242bad5fa63SBorislav Petkov
243a77a94f8SBorislav Petkov #ifdef CONFIG_MICROCODE_LATE_LOADING
244a5321aecSAshok Raj /*
245a5321aecSAshok Raj * Late loading dance. Why the heavy-handed stomp_machine effort?
246a5321aecSAshok Raj *
247a5321aecSAshok Raj * - HT siblings must be idle and not execute other code while the other sibling
248a5321aecSAshok Raj * is loading microcode in order to avoid any negative interactions caused by
249a5321aecSAshok Raj * the loading.
250a5321aecSAshok Raj *
251a5321aecSAshok Raj * - In addition, microcode update on the cores must be serialized until this
252a5321aecSAshok Raj * requirement can be relaxed in the future. Right now, this is conservative
253a5321aecSAshok Raj * and good.
254a5321aecSAshok Raj */
255ba3aeb97SThomas Gleixner enum sibling_ctrl {
256ba3aeb97SThomas Gleixner /* Spinwait with timeout */
257ba3aeb97SThomas Gleixner SCTRL_WAIT,
258ba3aeb97SThomas Gleixner /* Invoke the microcode_apply() callback */
259ba3aeb97SThomas Gleixner SCTRL_APPLY,
260ba3aeb97SThomas Gleixner /* Proceed without invoking the microcode_apply() callback */
261ba3aeb97SThomas Gleixner SCTRL_DONE,
262ba3aeb97SThomas Gleixner };
263ba3aeb97SThomas Gleixner
2644b753955SThomas Gleixner struct microcode_ctrl {
265ba3aeb97SThomas Gleixner enum sibling_ctrl ctrl;
2664b753955SThomas Gleixner enum ucode_state result;
267ba3aeb97SThomas Gleixner unsigned int ctrl_cpu;
2687eb314a2SThomas Gleixner bool nmi_enabled;
2694b753955SThomas Gleixner };
2704b753955SThomas Gleixner
2717eb314a2SThomas Gleixner DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
2724b753955SThomas Gleixner static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl);
2738f849ff6SThomas Gleixner static atomic_t late_cpus_in, offline_in_nmi;
2741582c0f4SThomas Gleixner static unsigned int loops_per_usec;
2758f849ff6SThomas Gleixner static cpumask_t cpu_offline_mask;
276a5321aecSAshok Raj
wait_for_cpus(atomic_t * cnt)2771582c0f4SThomas Gleixner static noinstr bool wait_for_cpus(atomic_t *cnt)
278bb8c13d6SBorislav Petkov {
2791582c0f4SThomas Gleixner unsigned int timeout, loops;
280bb8c13d6SBorislav Petkov
2811582c0f4SThomas Gleixner WARN_ON_ONCE(raw_atomic_dec_return(cnt) < 0);
282bb8c13d6SBorislav Petkov
2830772b9aaSThomas Gleixner for (timeout = 0; timeout < USEC_PER_SEC; timeout++) {
2841582c0f4SThomas Gleixner if (!raw_atomic_read(cnt))
2850772b9aaSThomas Gleixner return true;
286bb8c13d6SBorislav Petkov
2871582c0f4SThomas Gleixner for (loops = 0; loops < loops_per_usec; loops++)
2881582c0f4SThomas Gleixner cpu_relax();
289bb8c13d6SBorislav Petkov
2907eb314a2SThomas Gleixner /* If invoked directly, tickle the NMI watchdog */
2911582c0f4SThomas Gleixner if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) {
2921582c0f4SThomas Gleixner instrumentation_begin();
293bb8c13d6SBorislav Petkov touch_nmi_watchdog();
2941582c0f4SThomas Gleixner instrumentation_end();
2951582c0f4SThomas Gleixner }
296bb8c13d6SBorislav Petkov }
2970772b9aaSThomas Gleixner /* Prevent the late comers from making progress and let them time out */
2981582c0f4SThomas Gleixner raw_atomic_inc(cnt);
2990772b9aaSThomas Gleixner return false;
300bb8c13d6SBorislav Petkov }
301a5321aecSAshok Raj
wait_for_ctrl(void)3021582c0f4SThomas Gleixner static noinstr bool wait_for_ctrl(void)
3036067788fSThomas Gleixner {
3041582c0f4SThomas Gleixner unsigned int timeout, loops;
3056067788fSThomas Gleixner
3066067788fSThomas Gleixner for (timeout = 0; timeout < USEC_PER_SEC; timeout++) {
3071582c0f4SThomas Gleixner if (raw_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT)
3086067788fSThomas Gleixner return true;
3091582c0f4SThomas Gleixner
3101582c0f4SThomas Gleixner for (loops = 0; loops < loops_per_usec; loops++)
3111582c0f4SThomas Gleixner cpu_relax();
3121582c0f4SThomas Gleixner
3137eb314a2SThomas Gleixner /* If invoked directly, tickle the NMI watchdog */
3141582c0f4SThomas Gleixner if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) {
3151582c0f4SThomas Gleixner instrumentation_begin();
3166067788fSThomas Gleixner touch_nmi_watchdog();
3171582c0f4SThomas Gleixner instrumentation_end();
3181582c0f4SThomas Gleixner }
3196067788fSThomas Gleixner }
3206067788fSThomas Gleixner return false;
3216067788fSThomas Gleixner }
3226067788fSThomas Gleixner
3231582c0f4SThomas Gleixner /*
3241582c0f4SThomas Gleixner * Protected against instrumentation up to the point where the primary
3251582c0f4SThomas Gleixner * thread completed the update. See microcode_nmi_handler() for details.
3261582c0f4SThomas Gleixner */
load_secondary_wait(unsigned int ctrl_cpu)3271582c0f4SThomas Gleixner static noinstr bool load_secondary_wait(unsigned int ctrl_cpu)
3286067788fSThomas Gleixner {
3296067788fSThomas Gleixner /* Initial rendezvous to ensure that all CPUs have arrived */
3306067788fSThomas Gleixner if (!wait_for_cpus(&late_cpus_in)) {
3311582c0f4SThomas Gleixner raw_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT);
3321582c0f4SThomas Gleixner return false;
3336067788fSThomas Gleixner }
3346067788fSThomas Gleixner
3356067788fSThomas Gleixner /*
3366067788fSThomas Gleixner * Wait for primary threads to complete. If one of them hangs due
3376067788fSThomas Gleixner * to the update, there is no way out. This is non-recoverable
3386067788fSThomas Gleixner * because the CPU might hold locks or resources and confuse the
3396067788fSThomas Gleixner * scheduler, watchdogs etc. There is no way to safely evacuate the
3406067788fSThomas Gleixner * machine.
3416067788fSThomas Gleixner */
3421582c0f4SThomas Gleixner if (wait_for_ctrl())
3431582c0f4SThomas Gleixner return true;
3446067788fSThomas Gleixner
3451582c0f4SThomas Gleixner instrumentation_begin();
3461582c0f4SThomas Gleixner panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu);
3471582c0f4SThomas Gleixner instrumentation_end();
3481582c0f4SThomas Gleixner }
3491582c0f4SThomas Gleixner
3501582c0f4SThomas Gleixner /*
3511582c0f4SThomas Gleixner * Protected against instrumentation up to the point where the primary
3521582c0f4SThomas Gleixner * thread completed the update. See microcode_nmi_handler() for details.
3531582c0f4SThomas Gleixner */
load_secondary(unsigned int cpu)3541582c0f4SThomas Gleixner static noinstr void load_secondary(unsigned int cpu)
3551582c0f4SThomas Gleixner {
3561582c0f4SThomas Gleixner unsigned int ctrl_cpu = raw_cpu_read(ucode_ctrl.ctrl_cpu);
3571582c0f4SThomas Gleixner enum ucode_state ret;
3581582c0f4SThomas Gleixner
3591582c0f4SThomas Gleixner if (!load_secondary_wait(ctrl_cpu)) {
3601582c0f4SThomas Gleixner instrumentation_begin();
3611582c0f4SThomas Gleixner pr_err_once("load: %d CPUs timed out\n",
3621582c0f4SThomas Gleixner atomic_read(&late_cpus_in) - 1);
3631582c0f4SThomas Gleixner instrumentation_end();
3641582c0f4SThomas Gleixner return;
3651582c0f4SThomas Gleixner }
3661582c0f4SThomas Gleixner
3671582c0f4SThomas Gleixner /* Primary thread completed. Allow to invoke instrumentable code */
3681582c0f4SThomas Gleixner instrumentation_begin();
3696067788fSThomas Gleixner /*
3706067788fSThomas Gleixner * If the primary succeeded then invoke the apply() callback,
3716067788fSThomas Gleixner * otherwise copy the state from the primary thread.
3726067788fSThomas Gleixner */
3736067788fSThomas Gleixner if (this_cpu_read(ucode_ctrl.ctrl) == SCTRL_APPLY)
3746067788fSThomas Gleixner ret = microcode_ops->apply_microcode(cpu);
3756067788fSThomas Gleixner else
3766067788fSThomas Gleixner ret = per_cpu(ucode_ctrl.result, ctrl_cpu);
3776067788fSThomas Gleixner
3786067788fSThomas Gleixner this_cpu_write(ucode_ctrl.result, ret);
3796067788fSThomas Gleixner this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE);
3801582c0f4SThomas Gleixner instrumentation_end();
3816067788fSThomas Gleixner }
3826067788fSThomas Gleixner
__load_primary(unsigned int cpu)3838f849ff6SThomas Gleixner static void __load_primary(unsigned int cpu)
3846067788fSThomas Gleixner {
3856067788fSThomas Gleixner struct cpumask *secondaries = topology_sibling_cpumask(cpu);
3866067788fSThomas Gleixner enum sibling_ctrl ctrl;
3876067788fSThomas Gleixner enum ucode_state ret;
3886067788fSThomas Gleixner unsigned int sibling;
3896067788fSThomas Gleixner
3906067788fSThomas Gleixner /* Initial rendezvous to ensure that all CPUs have arrived */
3916067788fSThomas Gleixner if (!wait_for_cpus(&late_cpus_in)) {
3926067788fSThomas Gleixner this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT);
3936067788fSThomas Gleixner pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1);
3946067788fSThomas Gleixner return;
3956067788fSThomas Gleixner }
3966067788fSThomas Gleixner
3976067788fSThomas Gleixner ret = microcode_ops->apply_microcode(cpu);
3986067788fSThomas Gleixner this_cpu_write(ucode_ctrl.result, ret);
3996067788fSThomas Gleixner this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE);
4006067788fSThomas Gleixner
4016067788fSThomas Gleixner /*
4026067788fSThomas Gleixner * If the update was successful, let the siblings run the apply()
4036067788fSThomas Gleixner * callback. If not, tell them it's done. This also covers the
4046067788fSThomas Gleixner * case where the CPU has uniform loading at package or system
4056067788fSThomas Gleixner * scope implemented but does not advertise it.
4066067788fSThomas Gleixner */
4076067788fSThomas Gleixner if (ret == UCODE_UPDATED || ret == UCODE_OK)
4086067788fSThomas Gleixner ctrl = SCTRL_APPLY;
4096067788fSThomas Gleixner else
4106067788fSThomas Gleixner ctrl = SCTRL_DONE;
4116067788fSThomas Gleixner
4126067788fSThomas Gleixner for_each_cpu(sibling, secondaries) {
4136067788fSThomas Gleixner if (sibling != cpu)
4146067788fSThomas Gleixner per_cpu(ucode_ctrl.ctrl, sibling) = ctrl;
4156067788fSThomas Gleixner }
4166067788fSThomas Gleixner }
4176067788fSThomas Gleixner
kick_offline_cpus(unsigned int nr_offl)4188f849ff6SThomas Gleixner static bool kick_offline_cpus(unsigned int nr_offl)
4198f849ff6SThomas Gleixner {
4208f849ff6SThomas Gleixner unsigned int cpu, timeout;
4218f849ff6SThomas Gleixner
4228f849ff6SThomas Gleixner for_each_cpu(cpu, &cpu_offline_mask) {
4238f849ff6SThomas Gleixner /* Enable the rendezvous handler and send NMI */
4248f849ff6SThomas Gleixner per_cpu(ucode_ctrl.nmi_enabled, cpu) = true;
4258f849ff6SThomas Gleixner apic_send_nmi_to_offline_cpu(cpu);
4268f849ff6SThomas Gleixner }
4278f849ff6SThomas Gleixner
4288f849ff6SThomas Gleixner /* Wait for them to arrive */
4298f849ff6SThomas Gleixner for (timeout = 0; timeout < (USEC_PER_SEC / 2); timeout++) {
4308f849ff6SThomas Gleixner if (atomic_read(&offline_in_nmi) == nr_offl)
4318f849ff6SThomas Gleixner return true;
4328f849ff6SThomas Gleixner udelay(1);
4338f849ff6SThomas Gleixner }
4348f849ff6SThomas Gleixner /* Let the others time out */
4358f849ff6SThomas Gleixner return false;
4368f849ff6SThomas Gleixner }
4378f849ff6SThomas Gleixner
release_offline_cpus(void)4388f849ff6SThomas Gleixner static void release_offline_cpus(void)
4398f849ff6SThomas Gleixner {
4408f849ff6SThomas Gleixner unsigned int cpu;
4418f849ff6SThomas Gleixner
4428f849ff6SThomas Gleixner for_each_cpu(cpu, &cpu_offline_mask)
4438f849ff6SThomas Gleixner per_cpu(ucode_ctrl.ctrl, cpu) = SCTRL_DONE;
4448f849ff6SThomas Gleixner }
4458f849ff6SThomas Gleixner
load_primary(unsigned int cpu)4468f849ff6SThomas Gleixner static void load_primary(unsigned int cpu)
4478f849ff6SThomas Gleixner {
4488f849ff6SThomas Gleixner unsigned int nr_offl = cpumask_weight(&cpu_offline_mask);
4498f849ff6SThomas Gleixner bool proceed = true;
4508f849ff6SThomas Gleixner
4518f849ff6SThomas Gleixner /* Kick soft-offlined SMT siblings if required */
4528f849ff6SThomas Gleixner if (!cpu && nr_offl)
4538f849ff6SThomas Gleixner proceed = kick_offline_cpus(nr_offl);
4548f849ff6SThomas Gleixner
4558f849ff6SThomas Gleixner /* If the soft-offlined CPUs did not respond, abort */
4568f849ff6SThomas Gleixner if (proceed)
4578f849ff6SThomas Gleixner __load_primary(cpu);
4588f849ff6SThomas Gleixner
4598f849ff6SThomas Gleixner /* Unconditionally release soft-offlined SMT siblings if required */
4608f849ff6SThomas Gleixner if (!cpu && nr_offl)
4618f849ff6SThomas Gleixner release_offline_cpus();
4628f849ff6SThomas Gleixner }
4638f849ff6SThomas Gleixner
4648f849ff6SThomas Gleixner /*
4658f849ff6SThomas Gleixner * Minimal stub rendezvous handler for soft-offlined CPUs which participate
4668f849ff6SThomas Gleixner * in the NMI rendezvous to protect against a concurrent NMI on affected
4678f849ff6SThomas Gleixner * CPUs.
4688f849ff6SThomas Gleixner */
microcode_offline_nmi_handler(void)4698f849ff6SThomas Gleixner void noinstr microcode_offline_nmi_handler(void)
4708f849ff6SThomas Gleixner {
4718f849ff6SThomas Gleixner if (!raw_cpu_read(ucode_ctrl.nmi_enabled))
4728f849ff6SThomas Gleixner return;
4738f849ff6SThomas Gleixner raw_cpu_write(ucode_ctrl.nmi_enabled, false);
4748f849ff6SThomas Gleixner raw_cpu_write(ucode_ctrl.result, UCODE_OFFLINE);
4758f849ff6SThomas Gleixner raw_atomic_inc(&offline_in_nmi);
4768f849ff6SThomas Gleixner wait_for_ctrl();
4778f849ff6SThomas Gleixner }
4788f849ff6SThomas Gleixner
microcode_update_handler(void)4791582c0f4SThomas Gleixner static noinstr bool microcode_update_handler(void)
480bad5fa63SBorislav Petkov {
4811582c0f4SThomas Gleixner unsigned int cpu = raw_smp_processor_id();
482bad5fa63SBorislav Petkov
4831582c0f4SThomas Gleixner if (raw_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) {
4841582c0f4SThomas Gleixner instrumentation_begin();
4850bf87165SThomas Gleixner load_primary(cpu);
4861582c0f4SThomas Gleixner instrumentation_end();
4871582c0f4SThomas Gleixner } else {
4880bf87165SThomas Gleixner load_secondary(cpu);
4891582c0f4SThomas Gleixner }
490a5321aecSAshok Raj
4911582c0f4SThomas Gleixner instrumentation_begin();
4927eb314a2SThomas Gleixner touch_nmi_watchdog();
4931582c0f4SThomas Gleixner instrumentation_end();
4941582c0f4SThomas Gleixner
4957eb314a2SThomas Gleixner return true;
4967eb314a2SThomas Gleixner }
4977eb314a2SThomas Gleixner
4981582c0f4SThomas Gleixner /*
4991582c0f4SThomas Gleixner * Protection against instrumentation is required for CPUs which are not
5001582c0f4SThomas Gleixner * safe against an NMI which is delivered to the secondary SMT sibling
5011582c0f4SThomas Gleixner * while the primary thread updates the microcode. Instrumentation can end
5021582c0f4SThomas Gleixner * up in #INT3, #DB and #PF. The IRET from those exceptions reenables NMI
5031582c0f4SThomas Gleixner * which is the opposite of what the NMI rendezvous is trying to achieve.
5041582c0f4SThomas Gleixner *
5051582c0f4SThomas Gleixner * The primary thread is safe versus instrumentation as the actual
5061582c0f4SThomas Gleixner * microcode update handles this correctly. It's only the sibling code
5071582c0f4SThomas Gleixner * path which must be NMI safe until the primary thread completed the
5081582c0f4SThomas Gleixner * update.
5091582c0f4SThomas Gleixner */
microcode_nmi_handler(void)5101582c0f4SThomas Gleixner bool noinstr microcode_nmi_handler(void)
5117eb314a2SThomas Gleixner {
5121582c0f4SThomas Gleixner if (!raw_cpu_read(ucode_ctrl.nmi_enabled))
5137eb314a2SThomas Gleixner return false;
5147eb314a2SThomas Gleixner
5151582c0f4SThomas Gleixner raw_cpu_write(ucode_ctrl.nmi_enabled, false);
5167eb314a2SThomas Gleixner return microcode_update_handler();
5177eb314a2SThomas Gleixner }
5187eb314a2SThomas Gleixner
load_cpus_stopped(void * unused)5197eb314a2SThomas Gleixner static int load_cpus_stopped(void *unused)
5207eb314a2SThomas Gleixner {
5217eb314a2SThomas Gleixner if (microcode_ops->use_nmi) {
5227eb314a2SThomas Gleixner /* Enable the NMI handler and raise NMI */
5237eb314a2SThomas Gleixner this_cpu_write(ucode_ctrl.nmi_enabled, true);
5247eb314a2SThomas Gleixner apic->send_IPI(smp_processor_id(), NMI_VECTOR);
5257eb314a2SThomas Gleixner } else {
5267eb314a2SThomas Gleixner /* Just invoke the handler directly */
5277eb314a2SThomas Gleixner microcode_update_handler();
5287eb314a2SThomas Gleixner }
5294b753955SThomas Gleixner return 0;
530a5321aecSAshok Raj }
531a5321aecSAshok Raj
load_late_stop_cpus(bool is_safe)5329407bda8SThomas Gleixner static int load_late_stop_cpus(bool is_safe)
533a5321aecSAshok Raj {
5344b753955SThomas Gleixner unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0;
5358f849ff6SThomas Gleixner unsigned int nr_offl, offline = 0;
5364b753955SThomas Gleixner int old_rev = boot_cpu_data.microcode;
537ab31c744SAshok Raj struct cpuinfo_x86 prev_info;
538a5321aecSAshok Raj
5399407bda8SThomas Gleixner if (!is_safe) {
5409407bda8SThomas Gleixner pr_err("Late microcode loading without minimal revision check.\n");
541d23d33eaSBorislav Petkov pr_err("You should switch to early loading, if possible.\n");
5429407bda8SThomas Gleixner }
543d23d33eaSBorislav Petkov
5440772b9aaSThomas Gleixner atomic_set(&late_cpus_in, num_online_cpus());
5458f849ff6SThomas Gleixner atomic_set(&offline_in_nmi, 0);
5461582c0f4SThomas Gleixner loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000);
547a5321aecSAshok Raj
548c0dd9245SAshok Raj /*
549c0dd9245SAshok Raj * Take a snapshot before the microcode update in order to compare and
550c0dd9245SAshok Raj * check whether any bits changed after an update.
551c0dd9245SAshok Raj */
552c0dd9245SAshok Raj store_cpu_caps(&prev_info);
553c0dd9245SAshok Raj
5547eb314a2SThomas Gleixner if (microcode_ops->use_nmi)
5557eb314a2SThomas Gleixner static_branch_enable_cpuslocked(µcode_nmi_handler_enable);
5567eb314a2SThomas Gleixner
5574b753955SThomas Gleixner stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask);
5584b753955SThomas Gleixner
5597eb314a2SThomas Gleixner if (microcode_ops->use_nmi)
5607eb314a2SThomas Gleixner static_branch_disable_cpuslocked(µcode_nmi_handler_enable);
5617eb314a2SThomas Gleixner
5624b753955SThomas Gleixner /* Analyze the results */
5634b753955SThomas Gleixner for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) {
5644b753955SThomas Gleixner switch (per_cpu(ucode_ctrl.result, cpu)) {
5654b753955SThomas Gleixner case UCODE_UPDATED: updated++; break;
5664b753955SThomas Gleixner case UCODE_TIMEOUT: timedout++; break;
5674b753955SThomas Gleixner case UCODE_OK: siblings++; break;
5688f849ff6SThomas Gleixner case UCODE_OFFLINE: offline++; break;
5694b753955SThomas Gleixner default: failed++; break;
5704b753955SThomas Gleixner }
5714b753955SThomas Gleixner }
5722a1dada3SThomas Gleixner
5732a1dada3SThomas Gleixner if (microcode_ops->finalize_late_load)
5744b753955SThomas Gleixner microcode_ops->finalize_late_load(!updated);
5752a1dada3SThomas Gleixner
5764b753955SThomas Gleixner if (!updated) {
5774b753955SThomas Gleixner /* Nothing changed. */
5784b753955SThomas Gleixner if (!failed && !timedout)
5794b753955SThomas Gleixner return 0;
5808f849ff6SThomas Gleixner
5818f849ff6SThomas Gleixner nr_offl = cpumask_weight(&cpu_offline_mask);
5828f849ff6SThomas Gleixner if (offline < nr_offl) {
5838f849ff6SThomas Gleixner pr_warn("%u offline siblings did not respond.\n",
5848f849ff6SThomas Gleixner nr_offl - atomic_read(&offline_in_nmi));
5858f849ff6SThomas Gleixner return -EIO;
5868f849ff6SThomas Gleixner }
5874b753955SThomas Gleixner pr_err("update failed: %u CPUs failed %u CPUs timed out\n",
5884b753955SThomas Gleixner failed, timedout);
5894b753955SThomas Gleixner return -EIO;
5906eab3abaSAshok Raj }
5914b753955SThomas Gleixner
5929407bda8SThomas Gleixner if (!is_safe || failed || timedout)
5934b753955SThomas Gleixner add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
5949407bda8SThomas Gleixner
5954b753955SThomas Gleixner pr_info("load: updated on %u primary CPUs with %u siblings\n", updated, siblings);
5964b753955SThomas Gleixner if (failed || timedout) {
5974b753955SThomas Gleixner pr_err("load incomplete. %u CPUs timed out or failed\n",
5984b753955SThomas Gleixner num_online_cpus() - (updated + siblings));
5994b753955SThomas Gleixner }
6004b753955SThomas Gleixner pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode);
6014b753955SThomas Gleixner microcode_check(&prev_info);
6024b753955SThomas Gleixner
6034b753955SThomas Gleixner return updated + siblings == num_online_cpus() ? 0 : -EIO;
604bad5fa63SBorislav Petkov }
605bad5fa63SBorislav Petkov
606634ac23aSThomas Gleixner /*
6074b753955SThomas Gleixner * This function does two things:
6084b753955SThomas Gleixner *
6094b753955SThomas Gleixner * 1) Ensure that all required CPUs which are present and have been booted
610634ac23aSThomas Gleixner * once are online.
611634ac23aSThomas Gleixner *
612634ac23aSThomas Gleixner * To pass this check, all primary threads must be online.
613634ac23aSThomas Gleixner *
614634ac23aSThomas Gleixner * If the microcode load is not safe against NMI then all SMT threads
615634ac23aSThomas Gleixner * must be online as well because they still react to NMIs when they are
616634ac23aSThomas Gleixner * soft-offlined and parked in one of the play_dead() variants. So if a
617634ac23aSThomas Gleixner * NMI hits while the primary thread updates the microcode the resulting
618634ac23aSThomas Gleixner * behaviour is undefined. The default play_dead() implementation on
619634ac23aSThomas Gleixner * modern CPUs uses MWAIT, which is also not guaranteed to be safe
620634ac23aSThomas Gleixner * against a microcode update which affects MWAIT.
6214b753955SThomas Gleixner *
6228f849ff6SThomas Gleixner * As soft-offlined CPUs still react on NMIs, the SMT sibling
6238f849ff6SThomas Gleixner * restriction can be lifted when the vendor driver signals to use NMI
6248f849ff6SThomas Gleixner * for rendezvous and the APIC provides a mechanism to send an NMI to a
6258f849ff6SThomas Gleixner * soft-offlined CPU. The soft-offlined CPUs are then able to
6268f849ff6SThomas Gleixner * participate in the rendezvous in a trivial stub handler.
6278f849ff6SThomas Gleixner *
6288f849ff6SThomas Gleixner * 2) Initialize the per CPU control structure and create a cpumask
6298f849ff6SThomas Gleixner * which contains "offline"; secondary threads, so they can be handled
6308f849ff6SThomas Gleixner * correctly by a control CPU.
631634ac23aSThomas Gleixner */
setup_cpus(void)6324b753955SThomas Gleixner static bool setup_cpus(void)
633634ac23aSThomas Gleixner {
634ba3aeb97SThomas Gleixner struct microcode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, };
6358f849ff6SThomas Gleixner bool allow_smt_offline;
636634ac23aSThomas Gleixner unsigned int cpu;
637634ac23aSThomas Gleixner
6388f849ff6SThomas Gleixner allow_smt_offline = microcode_ops->nmi_safe ||
6398f849ff6SThomas Gleixner (microcode_ops->use_nmi && apic->nmi_to_offline_cpu);
6408f849ff6SThomas Gleixner
6418f849ff6SThomas Gleixner cpumask_clear(&cpu_offline_mask);
6428f849ff6SThomas Gleixner
643634ac23aSThomas Gleixner for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) {
6448f849ff6SThomas Gleixner /*
6458f849ff6SThomas Gleixner * Offline CPUs sit in one of the play_dead() functions
6468f849ff6SThomas Gleixner * with interrupts disabled, but they still react on NMIs
6478f849ff6SThomas Gleixner * and execute arbitrary code. Also MWAIT being updated
6488f849ff6SThomas Gleixner * while the offline CPU sits there is not necessarily safe
6498f849ff6SThomas Gleixner * on all CPU variants.
6508f849ff6SThomas Gleixner *
6518f849ff6SThomas Gleixner * Mark them in the offline_cpus mask which will be handled
6528f849ff6SThomas Gleixner * by CPU0 later in the update process.
6538f849ff6SThomas Gleixner *
6548f849ff6SThomas Gleixner * Ensure that the primary thread is online so that it is
6558f849ff6SThomas Gleixner * guaranteed that all cores are updated.
6568f849ff6SThomas Gleixner */
657634ac23aSThomas Gleixner if (!cpu_online(cpu)) {
6588f849ff6SThomas Gleixner if (topology_is_primary_thread(cpu) || !allow_smt_offline) {
6598f849ff6SThomas Gleixner pr_err("CPU %u not online, loading aborted\n", cpu);
660634ac23aSThomas Gleixner return false;
661634ac23aSThomas Gleixner }
6628f849ff6SThomas Gleixner cpumask_set_cpu(cpu, &cpu_offline_mask);
6638f849ff6SThomas Gleixner per_cpu(ucode_ctrl, cpu) = ctrl;
6648f849ff6SThomas Gleixner continue;
665634ac23aSThomas Gleixner }
666ba3aeb97SThomas Gleixner
667ba3aeb97SThomas Gleixner /*
668ba3aeb97SThomas Gleixner * Initialize the per CPU state. This is core scope for now,
669ba3aeb97SThomas Gleixner * but prepared to take package or system scope into account.
670ba3aeb97SThomas Gleixner */
671ba3aeb97SThomas Gleixner ctrl.ctrl_cpu = cpumask_first(topology_sibling_cpumask(cpu));
6724b753955SThomas Gleixner per_cpu(ucode_ctrl, cpu) = ctrl;
673634ac23aSThomas Gleixner }
674634ac23aSThomas Gleixner return true;
675634ac23aSThomas Gleixner }
676634ac23aSThomas Gleixner
load_late_locked(void)6774b753955SThomas Gleixner static int load_late_locked(void)
6786f059e63SThomas Gleixner {
6794b753955SThomas Gleixner if (!setup_cpus())
6806f059e63SThomas Gleixner return -EBUSY;
6816f059e63SThomas Gleixner
6826f059e63SThomas Gleixner switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) {
6836f059e63SThomas Gleixner case UCODE_NEW:
6849407bda8SThomas Gleixner return load_late_stop_cpus(false);
6859407bda8SThomas Gleixner case UCODE_NEW_SAFE:
6869407bda8SThomas Gleixner return load_late_stop_cpus(true);
6876f059e63SThomas Gleixner case UCODE_NFOUND:
6886f059e63SThomas Gleixner return -ENOENT;
6896f059e63SThomas Gleixner default:
6906f059e63SThomas Gleixner return -EBADFD;
6916f059e63SThomas Gleixner }
6926f059e63SThomas Gleixner }
6936f059e63SThomas Gleixner
reload_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)694bad5fa63SBorislav Petkov static ssize_t reload_store(struct device *dev,
695bad5fa63SBorislav Petkov struct device_attribute *attr,
696bad5fa63SBorislav Petkov const char *buf, size_t size)
697bad5fa63SBorislav Petkov {
698bad5fa63SBorislav Petkov unsigned long val;
6996f059e63SThomas Gleixner ssize_t ret;
700bad5fa63SBorislav Petkov
701bad5fa63SBorislav Petkov ret = kstrtoul(buf, 0, &val);
70225d0dc4bSAshok Raj if (ret || val != 1)
70325d0dc4bSAshok Raj return -EINVAL;
704bad5fa63SBorislav Petkov
7052089f34fSSebastian Andrzej Siewior cpus_read_lock();
7064b753955SThomas Gleixner ret = load_late_locked();
7072089f34fSSebastian Andrzej Siewior cpus_read_unlock();
708bad5fa63SBorislav Petkov
7096f059e63SThomas Gleixner return ret ? : size;
710bad5fa63SBorislav Petkov }
711bad5fa63SBorislav Petkov
712a77a94f8SBorislav Petkov static DEVICE_ATTR_WO(reload);
713a77a94f8SBorislav Petkov #endif
714a77a94f8SBorislav Petkov
version_show(struct device * dev,struct device_attribute * attr,char * buf)715bad5fa63SBorislav Petkov static ssize_t version_show(struct device *dev,
716bad5fa63SBorislav Petkov struct device_attribute *attr, char *buf)
717bad5fa63SBorislav Petkov {
718bad5fa63SBorislav Petkov struct ucode_cpu_info *uci = ucode_cpu_info + dev->id;
719bad5fa63SBorislav Petkov
720bad5fa63SBorislav Petkov return sprintf(buf, "0x%x\n", uci->cpu_sig.rev);
721bad5fa63SBorislav Petkov }
722bad5fa63SBorislav Petkov
processor_flags_show(struct device * dev,struct device_attribute * attr,char * buf)72359047d94SGuangju Wang[baidu] static ssize_t processor_flags_show(struct device *dev,
724bad5fa63SBorislav Petkov struct device_attribute *attr, char *buf)
725bad5fa63SBorislav Petkov {
726bad5fa63SBorislav Petkov struct ucode_cpu_info *uci = ucode_cpu_info + dev->id;
727bad5fa63SBorislav Petkov
728bad5fa63SBorislav Petkov return sprintf(buf, "0x%x\n", uci->cpu_sig.pf);
729bad5fa63SBorislav Petkov }
730bad5fa63SBorislav Petkov
73159047d94SGuangju Wang[baidu] static DEVICE_ATTR_RO(version);
73259047d94SGuangju Wang[baidu] static DEVICE_ATTR_RO(processor_flags);
733bad5fa63SBorislav Petkov
734bad5fa63SBorislav Petkov static struct attribute *mc_default_attrs[] = {
735bad5fa63SBorislav Petkov &dev_attr_version.attr,
736bad5fa63SBorislav Petkov &dev_attr_processor_flags.attr,
737bad5fa63SBorislav Petkov NULL
738bad5fa63SBorislav Petkov };
739bad5fa63SBorislav Petkov
74045bd07adSArvind Yadav static const struct attribute_group mc_attr_group = {
741bad5fa63SBorislav Petkov .attrs = mc_default_attrs,
742bad5fa63SBorislav Petkov .name = "microcode",
743bad5fa63SBorislav Petkov };
744bad5fa63SBorislav Petkov
microcode_fini_cpu(int cpu)745bad5fa63SBorislav Petkov static void microcode_fini_cpu(int cpu)
746bad5fa63SBorislav Petkov {
74706b8534cSBorislav Petkov if (microcode_ops->microcode_fini_cpu)
748bad5fa63SBorislav Petkov microcode_ops->microcode_fini_cpu(cpu);
749bad5fa63SBorislav Petkov }
750bad5fa63SBorislav Petkov
751bad5fa63SBorislav Petkov /**
752f9e14dbbSBorislav Petkov * microcode_bsp_resume - Update boot CPU microcode during resume.
753bad5fa63SBorislav Petkov */
microcode_bsp_resume(void)754f9e14dbbSBorislav Petkov void microcode_bsp_resume(void)
755bad5fa63SBorislav Petkov {
756bad5fa63SBorislav Petkov int cpu = smp_processor_id();
757bad5fa63SBorislav Petkov struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
758bad5fa63SBorislav Petkov
759254ed7cfSBorislav Petkov if (uci->mc)
760bad5fa63SBorislav Petkov microcode_ops->apply_microcode(cpu);
761254ed7cfSBorislav Petkov else
762a5ad9213SBorislav Petkov (AMD) reload_early_microcode(cpu);
763bad5fa63SBorislav Petkov }
764bad5fa63SBorislav Petkov
765bad5fa63SBorislav Petkov static struct syscore_ops mc_syscore_ops = {
766f9e14dbbSBorislav Petkov .resume = microcode_bsp_resume,
767bad5fa63SBorislav Petkov };
768bad5fa63SBorislav Petkov
mc_cpu_online(unsigned int cpu)7695423f5ceSThomas Gleixner static int mc_cpu_online(unsigned int cpu)
7705423f5ceSThomas Gleixner {
7712e199733SThomas Gleixner struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
7725423f5ceSThomas Gleixner struct device *dev = get_cpu_device(cpu);
773bad5fa63SBorislav Petkov
7742e199733SThomas Gleixner memset(uci, 0, sizeof(*uci));
7752e199733SThomas Gleixner
7762e199733SThomas Gleixner microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig);
7772e199733SThomas Gleixner cpu_data(cpu).microcode = uci->cpu_sig.rev;
7782e199733SThomas Gleixner if (!cpu)
7792e199733SThomas Gleixner boot_cpu_data.microcode = uci->cpu_sig.rev;
7802e199733SThomas Gleixner
781bad5fa63SBorislav Petkov if (sysfs_create_group(&dev->kobj, &mc_attr_group))
782bad5fa63SBorislav Petkov pr_err("Failed to create group for CPU%d\n", cpu);
78329bd7fbcSSebastian Andrzej Siewior return 0;
78429bd7fbcSSebastian Andrzej Siewior }
785bad5fa63SBorislav Petkov
mc_cpu_down_prep(unsigned int cpu)78629bd7fbcSSebastian Andrzej Siewior static int mc_cpu_down_prep(unsigned int cpu)
78729bd7fbcSSebastian Andrzej Siewior {
788ba48aa32SThomas Gleixner struct device *dev = get_cpu_device(cpu);
789b6f86689SBorislav Petkov
790b6f86689SBorislav Petkov microcode_fini_cpu(cpu);
791bad5fa63SBorislav Petkov sysfs_remove_group(&dev->kobj, &mc_attr_group);
79229bd7fbcSSebastian Andrzej Siewior return 0;
793bad5fa63SBorislav Petkov }
794bad5fa63SBorislav Petkov
795bad5fa63SBorislav Petkov static struct attribute *cpu_root_microcode_attrs[] = {
796a77a94f8SBorislav Petkov #ifdef CONFIG_MICROCODE_LATE_LOADING
797bad5fa63SBorislav Petkov &dev_attr_reload.attr,
798a77a94f8SBorislav Petkov #endif
799bad5fa63SBorislav Petkov NULL
800bad5fa63SBorislav Petkov };
801bad5fa63SBorislav Petkov
80245bd07adSArvind Yadav static const struct attribute_group cpu_root_microcode_group = {
803bad5fa63SBorislav Petkov .name = "microcode",
804bad5fa63SBorislav Petkov .attrs = cpu_root_microcode_attrs,
805bad5fa63SBorislav Petkov };
806bad5fa63SBorislav Petkov
microcode_init(void)807c769dcd4SBorislav Petkov static int __init microcode_init(void)
808bad5fa63SBorislav Petkov {
809216f58beSGreg Kroah-Hartman struct device *dev_root;
8109a2bc335SBorislav Petkov struct cpuinfo_x86 *c = &boot_cpu_data;
811bad5fa63SBorislav Petkov int error;
812bad5fa63SBorislav Petkov
81384aba677SBoris Ostrovsky if (dis_ucode_ldr)
814da63865aSBoris Ostrovsky return -EINVAL;
81565cef131SBorislav Petkov
816bad5fa63SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL)
817bad5fa63SBorislav Petkov microcode_ops = init_intel_microcode();
818bad5fa63SBorislav Petkov else if (c->x86_vendor == X86_VENDOR_AMD)
819bad5fa63SBorislav Petkov microcode_ops = init_amd_microcode();
820bad5fa63SBorislav Petkov else
821bad5fa63SBorislav Petkov pr_err("no support for this CPU vendor\n");
822bad5fa63SBorislav Petkov
823bad5fa63SBorislav Petkov if (!microcode_ops)
824bad5fa63SBorislav Petkov return -ENODEV;
825bad5fa63SBorislav Petkov
826*080990aaSBorislav Petkov (AMD) pr_info_once("Current revision: 0x%08x\n", (early_data.new_rev ?: early_data.old_rev));
827*080990aaSBorislav Petkov (AMD)
828*080990aaSBorislav Petkov (AMD) if (early_data.new_rev)
829*080990aaSBorislav Petkov (AMD) pr_info_once("Updated early from: 0x%08x\n", early_data.old_rev);
830*080990aaSBorislav Petkov (AMD)
8312e6ff405SBorislav Petkov microcode_pdev = platform_device_register_simple("microcode", -1, NULL, 0);
832bad5fa63SBorislav Petkov if (IS_ERR(microcode_pdev))
833bad5fa63SBorislav Petkov return PTR_ERR(microcode_pdev);
834bad5fa63SBorislav Petkov
835216f58beSGreg Kroah-Hartman dev_root = bus_get_dev_root(&cpu_subsys);
836216f58beSGreg Kroah-Hartman if (dev_root) {
837216f58beSGreg Kroah-Hartman error = sysfs_create_group(&dev_root->kobj, &cpu_root_microcode_group);
838216f58beSGreg Kroah-Hartman put_device(dev_root);
839bad5fa63SBorislav Petkov if (error) {
840bad5fa63SBorislav Petkov pr_err("Error creating microcode group!\n");
841b6f86689SBorislav Petkov goto out_pdev;
842bad5fa63SBorislav Petkov }
843216f58beSGreg Kroah-Hartman }
844bad5fa63SBorislav Petkov
845bad5fa63SBorislav Petkov register_syscore_ops(&mc_syscore_ops);
8462e199733SThomas Gleixner cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online",
84729bd7fbcSSebastian Andrzej Siewior mc_cpu_online, mc_cpu_down_prep);
848bad5fa63SBorislav Petkov
849bad5fa63SBorislav Petkov return 0;
850bad5fa63SBorislav Petkov
851bad5fa63SBorislav Petkov out_pdev:
852bad5fa63SBorislav Petkov platform_device_unregister(microcode_pdev);
853bad5fa63SBorislav Petkov return error;
854bad5fa63SBorislav Petkov
855bad5fa63SBorislav Petkov }
8562d5be37dSBorislav Petkov late_initcall(microcode_init);
857