1 /* 2 * AMD CPU Microcode Update Driver for Linux 3 * 4 * This driver allows to upgrade microcode on F10h AMD 5 * CPUs and later. 6 * 7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc. 8 * 2013-2016 Borislav Petkov <bp@alien8.de> 9 * 10 * Author: Peter Oruba <peter.oruba@amd.com> 11 * 12 * Based on work by: 13 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> 14 * 15 * early loader: 16 * Copyright (C) 2013 Advanced Micro Devices, Inc. 17 * 18 * Author: Jacob Shin <jacob.shin@amd.com> 19 * Fixes: Borislav Petkov <bp@suse.de> 20 * 21 * Licensed under the terms of the GNU General Public 22 * License version 2. See file COPYING for details. 23 */ 24 #define pr_fmt(fmt) "microcode: " fmt 25 26 #include <linux/earlycpio.h> 27 #include <linux/firmware.h> 28 #include <linux/uaccess.h> 29 #include <linux/vmalloc.h> 30 #include <linux/initrd.h> 31 #include <linux/kernel.h> 32 #include <linux/pci.h> 33 34 #include <asm/microcode_amd.h> 35 #include <asm/microcode.h> 36 #include <asm/processor.h> 37 #include <asm/setup.h> 38 #include <asm/cpu.h> 39 #include <asm/msr.h> 40 41 static struct equiv_cpu_entry *equiv_cpu_table; 42 43 /* 44 * This points to the current valid container of microcode patches which we will 45 * save from the initrd/builtin before jettisoning its contents. 46 */ 47 struct container { 48 u8 *data; 49 size_t size; 50 } cont; 51 52 static u32 ucode_new_rev; 53 static u8 amd_ucode_patch[PATCH_MAX_SIZE]; 54 static u16 this_equiv_id; 55 56 /* 57 * Microcode patch container file is prepended to the initrd in cpio 58 * format. See Documentation/x86/early-microcode.txt 59 */ 60 static const char 61 ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin"; 62 63 static size_t compute_container_size(u8 *data, u32 total_size) 64 { 65 size_t size = 0; 66 u32 *header = (u32 *)data; 67 68 if (header[0] != UCODE_MAGIC || 69 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */ 70 header[2] == 0) /* size */ 71 return size; 72 73 size = header[2] + CONTAINER_HDR_SZ; 74 total_size -= size; 75 data += size; 76 77 while (total_size) { 78 u16 patch_size; 79 80 header = (u32 *)data; 81 82 if (header[0] != UCODE_UCODE_TYPE) 83 break; 84 85 /* 86 * Sanity-check patch size. 87 */ 88 patch_size = header[1]; 89 if (patch_size > PATCH_MAX_SIZE) 90 break; 91 92 size += patch_size + SECTION_HDR_SIZE; 93 data += patch_size + SECTION_HDR_SIZE; 94 total_size -= patch_size + SECTION_HDR_SIZE; 95 } 96 97 return size; 98 } 99 100 static inline u16 find_equiv_id(struct equiv_cpu_entry *equiv_cpu_table, 101 unsigned int sig) 102 { 103 int i = 0; 104 105 if (!equiv_cpu_table) 106 return 0; 107 108 while (equiv_cpu_table[i].installed_cpu != 0) { 109 if (sig == equiv_cpu_table[i].installed_cpu) 110 return equiv_cpu_table[i].equiv_cpu; 111 112 i++; 113 } 114 return 0; 115 } 116 117 /* 118 * This scans the ucode blob for the proper container as we can have multiple 119 * containers glued together. Returns the equivalence ID from the equivalence 120 * table or 0 if none found. 121 */ 122 static u16 123 find_proper_container(u8 *ucode, size_t size, struct container *ret_cont) 124 { 125 struct container ret = { NULL, 0 }; 126 u32 eax, ebx, ecx, edx; 127 struct equiv_cpu_entry *eq; 128 int offset, left; 129 u16 eq_id = 0; 130 u32 *header; 131 u8 *data; 132 133 data = ucode; 134 left = size; 135 header = (u32 *)data; 136 137 138 /* find equiv cpu table */ 139 if (header[0] != UCODE_MAGIC || 140 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */ 141 header[2] == 0) /* size */ 142 return eq_id; 143 144 eax = 0x00000001; 145 ecx = 0; 146 native_cpuid(&eax, &ebx, &ecx, &edx); 147 148 while (left > 0) { 149 eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ); 150 151 ret.data = data; 152 153 /* Advance past the container header */ 154 offset = header[2] + CONTAINER_HDR_SZ; 155 data += offset; 156 left -= offset; 157 158 eq_id = find_equiv_id(eq, eax); 159 if (eq_id) { 160 ret.size = compute_container_size(ret.data, left + offset); 161 162 /* 163 * truncate how much we need to iterate over in the 164 * ucode update loop below 165 */ 166 left = ret.size - offset; 167 168 *ret_cont = ret; 169 return eq_id; 170 } 171 172 /* 173 * support multiple container files appended together. if this 174 * one does not have a matching equivalent cpu entry, we fast 175 * forward to the next container file. 176 */ 177 while (left > 0) { 178 header = (u32 *)data; 179 180 if (header[0] == UCODE_MAGIC && 181 header[1] == UCODE_EQUIV_CPU_TABLE_TYPE) 182 break; 183 184 offset = header[1] + SECTION_HDR_SIZE; 185 data += offset; 186 left -= offset; 187 } 188 189 /* mark where the next microcode container file starts */ 190 offset = data - (u8 *)ucode; 191 ucode = data; 192 } 193 194 return eq_id; 195 } 196 197 static int __apply_microcode_amd(struct microcode_amd *mc_amd) 198 { 199 u32 rev, dummy; 200 201 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); 202 203 /* verify patch application was successful */ 204 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 205 if (rev != mc_amd->hdr.patch_id) 206 return -1; 207 208 return 0; 209 } 210 211 /* 212 * Early load occurs before we can vmalloc(). So we look for the microcode 213 * patch container file in initrd, traverse equivalent cpu table, look for a 214 * matching microcode patch, and update, all in initrd memory in place. 215 * When vmalloc() is available for use later -- on 64-bit during first AP load, 216 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call 217 * load_microcode_amd() to save equivalent cpu table and microcode patches in 218 * kernel heap memory. 219 * 220 * Returns true if container found (sets @ret_cont), false otherwise. 221 */ 222 static bool apply_microcode_early_amd(void *ucode, size_t size, bool save_patch, 223 struct container *ret_cont) 224 { 225 u8 (*patch)[PATCH_MAX_SIZE]; 226 u32 rev, *header, *new_rev; 227 struct container ret; 228 int offset, left; 229 u16 eq_id = 0; 230 u8 *data; 231 232 #ifdef CONFIG_X86_32 233 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); 234 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); 235 #else 236 new_rev = &ucode_new_rev; 237 patch = &amd_ucode_patch; 238 #endif 239 240 if (check_current_patch_level(&rev, true)) 241 return false; 242 243 eq_id = find_proper_container(ucode, size, &ret); 244 if (!eq_id) 245 return false; 246 247 this_equiv_id = eq_id; 248 header = (u32 *)ret.data; 249 250 /* We're pointing to an equiv table, skip over it. */ 251 data = ret.data + header[2] + CONTAINER_HDR_SZ; 252 left = ret.size - (header[2] + CONTAINER_HDR_SZ); 253 254 while (left > 0) { 255 struct microcode_amd *mc; 256 257 header = (u32 *)data; 258 if (header[0] != UCODE_UCODE_TYPE || /* type */ 259 header[1] == 0) /* size */ 260 break; 261 262 mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE); 263 264 if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) { 265 266 if (!__apply_microcode_amd(mc)) { 267 rev = mc->hdr.patch_id; 268 *new_rev = rev; 269 270 if (save_patch) 271 memcpy(patch, mc, min_t(u32, header[1], PATCH_MAX_SIZE)); 272 } 273 } 274 275 offset = header[1] + SECTION_HDR_SIZE; 276 data += offset; 277 left -= offset; 278 } 279 280 if (ret_cont) 281 *ret_cont = ret; 282 283 return true; 284 } 285 286 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family) 287 { 288 #ifdef CONFIG_X86_64 289 char fw_name[36] = "amd-ucode/microcode_amd.bin"; 290 291 if (family >= 0x15) 292 snprintf(fw_name, sizeof(fw_name), 293 "amd-ucode/microcode_amd_fam%.2xh.bin", family); 294 295 return get_builtin_firmware(cp, fw_name); 296 #else 297 return false; 298 #endif 299 } 300 301 void __init load_ucode_amd_bsp(unsigned int family) 302 { 303 struct ucode_cpu_info *uci; 304 u32 eax, ebx, ecx, edx; 305 struct cpio_data cp; 306 const char *path; 307 bool use_pa; 308 309 if (IS_ENABLED(CONFIG_X86_32)) { 310 uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info); 311 path = (const char *)__pa_nodebug(ucode_path); 312 use_pa = true; 313 } else { 314 uci = ucode_cpu_info; 315 path = ucode_path; 316 use_pa = false; 317 } 318 319 if (!get_builtin_microcode(&cp, family)) 320 cp = find_microcode_in_initrd(path, use_pa); 321 322 if (!(cp.data && cp.size)) 323 return; 324 325 /* Get BSP's CPUID.EAX(1), needed in load_microcode_amd() */ 326 eax = 1; 327 ecx = 0; 328 native_cpuid(&eax, &ebx, &ecx, &edx); 329 uci->cpu_sig.sig = eax; 330 331 apply_microcode_early_amd(cp.data, cp.size, true, NULL); 332 } 333 334 #ifdef CONFIG_X86_32 335 /* 336 * On 32-bit, since AP's early load occurs before paging is turned on, we 337 * cannot traverse cpu_equiv_table and microcode_cache in kernel heap memory. 338 * So during cold boot, AP will apply_ucode_in_initrd() just like the BSP. 339 * In save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch, 340 * which is used upon resume from suspend. 341 */ 342 void load_ucode_amd_ap(unsigned int family) 343 { 344 struct microcode_amd *mc; 345 struct cpio_data cp; 346 347 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch); 348 if (mc->hdr.patch_id && mc->hdr.processor_rev_id) { 349 __apply_microcode_amd(mc); 350 return; 351 } 352 353 if (!get_builtin_microcode(&cp, family)) 354 cp = find_microcode_in_initrd((const char *)__pa_nodebug(ucode_path), true); 355 356 if (!(cp.data && cp.size)) 357 return; 358 359 /* 360 * This would set amd_ucode_patch above so that the following APs can 361 * use it directly instead of going down this path again. 362 */ 363 apply_microcode_early_amd(cp.data, cp.size, true, NULL); 364 } 365 #else 366 void load_ucode_amd_ap(unsigned int family) 367 { 368 struct equiv_cpu_entry *eq; 369 struct microcode_amd *mc; 370 u32 rev, eax; 371 u16 eq_id; 372 373 /* 64-bit runs with paging enabled, thus early==false. */ 374 if (check_current_patch_level(&rev, false)) 375 return; 376 377 /* First AP hasn't cached it yet, go through the blob. */ 378 if (!cont.data) { 379 struct cpio_data cp = { NULL, 0, "" }; 380 381 if (cont.size == -1) 382 return; 383 384 reget: 385 if (!get_builtin_microcode(&cp, family)) { 386 #ifdef CONFIG_BLK_DEV_INITRD 387 cp = find_cpio_data(ucode_path, (void *)initrd_start, 388 initrd_end - initrd_start, NULL); 389 #endif 390 if (!(cp.data && cp.size)) { 391 /* 392 * Mark it so that other APs do not scan again 393 * for no real reason and slow down boot 394 * needlessly. 395 */ 396 cont.size = -1; 397 return; 398 } 399 } 400 401 if (!apply_microcode_early_amd(cp.data, cp.size, false, &cont)) { 402 cont.size = -1; 403 return; 404 } 405 } 406 407 eax = cpuid_eax(0x00000001); 408 eq = (struct equiv_cpu_entry *)(cont.data + CONTAINER_HDR_SZ); 409 410 eq_id = find_equiv_id(eq, eax); 411 if (!eq_id) 412 return; 413 414 if (eq_id == this_equiv_id) { 415 mc = (struct microcode_amd *)amd_ucode_patch; 416 417 if (mc && rev < mc->hdr.patch_id) { 418 if (!__apply_microcode_amd(mc)) 419 ucode_new_rev = mc->hdr.patch_id; 420 } 421 422 } else { 423 424 /* 425 * AP has a different equivalence ID than BSP, looks like 426 * mixed-steppings silicon so go through the ucode blob anew. 427 */ 428 goto reget; 429 } 430 } 431 #endif /* CONFIG_X86_32 */ 432 433 static enum ucode_state 434 load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size); 435 436 int __init save_microcode_in_initrd_amd(unsigned int fam) 437 { 438 enum ucode_state ret; 439 int retval = 0; 440 u16 eq_id; 441 442 if (!cont.data) { 443 if (IS_ENABLED(CONFIG_X86_32) && (cont.size != -1)) { 444 struct cpio_data cp = { NULL, 0, "" }; 445 446 #ifdef CONFIG_BLK_DEV_INITRD 447 cp = find_cpio_data(ucode_path, (void *)initrd_start, 448 initrd_end - initrd_start, NULL); 449 #endif 450 451 if (!(cp.data && cp.size)) { 452 cont.size = -1; 453 return -EINVAL; 454 } 455 456 eq_id = find_proper_container(cp.data, cp.size, &cont); 457 if (!eq_id) { 458 cont.size = -1; 459 return -EINVAL; 460 } 461 462 } else 463 return -EINVAL; 464 } 465 466 ret = load_microcode_amd(smp_processor_id(), fam, cont.data, cont.size); 467 if (ret != UCODE_OK) 468 retval = -EINVAL; 469 470 /* 471 * This will be freed any msec now, stash patches for the current 472 * family and switch to patch cache for cpu hotplug, etc later. 473 */ 474 cont.data = NULL; 475 cont.size = 0; 476 477 return retval; 478 } 479 480 void reload_ucode_amd(void) 481 { 482 struct microcode_amd *mc; 483 u32 rev; 484 485 /* 486 * early==false because this is a syscore ->resume path and by 487 * that time paging is long enabled. 488 */ 489 if (check_current_patch_level(&rev, false)) 490 return; 491 492 mc = (struct microcode_amd *)amd_ucode_patch; 493 if (!mc) 494 return; 495 496 if (rev < mc->hdr.patch_id) { 497 if (!__apply_microcode_amd(mc)) { 498 ucode_new_rev = mc->hdr.patch_id; 499 pr_info("reload patch_level=0x%08x\n", ucode_new_rev); 500 } 501 } 502 } 503 static u16 __find_equiv_id(unsigned int cpu) 504 { 505 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 506 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig); 507 } 508 509 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu) 510 { 511 int i = 0; 512 513 BUG_ON(!equiv_cpu_table); 514 515 while (equiv_cpu_table[i].equiv_cpu != 0) { 516 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu) 517 return equiv_cpu_table[i].installed_cpu; 518 i++; 519 } 520 return 0; 521 } 522 523 /* 524 * a small, trivial cache of per-family ucode patches 525 */ 526 static struct ucode_patch *cache_find_patch(u16 equiv_cpu) 527 { 528 struct ucode_patch *p; 529 530 list_for_each_entry(p, µcode_cache, plist) 531 if (p->equiv_cpu == equiv_cpu) 532 return p; 533 return NULL; 534 } 535 536 static void update_cache(struct ucode_patch *new_patch) 537 { 538 struct ucode_patch *p; 539 540 list_for_each_entry(p, µcode_cache, plist) { 541 if (p->equiv_cpu == new_patch->equiv_cpu) { 542 if (p->patch_id >= new_patch->patch_id) 543 /* we already have the latest patch */ 544 return; 545 546 list_replace(&p->plist, &new_patch->plist); 547 kfree(p->data); 548 kfree(p); 549 return; 550 } 551 } 552 /* no patch found, add it */ 553 list_add_tail(&new_patch->plist, µcode_cache); 554 } 555 556 static void free_cache(void) 557 { 558 struct ucode_patch *p, *tmp; 559 560 list_for_each_entry_safe(p, tmp, µcode_cache, plist) { 561 __list_del(p->plist.prev, p->plist.next); 562 kfree(p->data); 563 kfree(p); 564 } 565 } 566 567 static struct ucode_patch *find_patch(unsigned int cpu) 568 { 569 u16 equiv_id; 570 571 equiv_id = __find_equiv_id(cpu); 572 if (!equiv_id) 573 return NULL; 574 575 return cache_find_patch(equiv_id); 576 } 577 578 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) 579 { 580 struct cpuinfo_x86 *c = &cpu_data(cpu); 581 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 582 struct ucode_patch *p; 583 584 csig->sig = cpuid_eax(0x00000001); 585 csig->rev = c->microcode; 586 587 /* 588 * a patch could have been loaded early, set uci->mc so that 589 * mc_bp_resume() can call apply_microcode() 590 */ 591 p = find_patch(cpu); 592 if (p && (p->patch_id == csig->rev)) 593 uci->mc = p->data; 594 595 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); 596 597 return 0; 598 } 599 600 static unsigned int verify_patch_size(u8 family, u32 patch_size, 601 unsigned int size) 602 { 603 u32 max_size; 604 605 #define F1XH_MPB_MAX_SIZE 2048 606 #define F14H_MPB_MAX_SIZE 1824 607 #define F15H_MPB_MAX_SIZE 4096 608 #define F16H_MPB_MAX_SIZE 3458 609 610 switch (family) { 611 case 0x14: 612 max_size = F14H_MPB_MAX_SIZE; 613 break; 614 case 0x15: 615 max_size = F15H_MPB_MAX_SIZE; 616 break; 617 case 0x16: 618 max_size = F16H_MPB_MAX_SIZE; 619 break; 620 default: 621 max_size = F1XH_MPB_MAX_SIZE; 622 break; 623 } 624 625 if (patch_size > min_t(u32, size, max_size)) { 626 pr_err("patch size mismatch\n"); 627 return 0; 628 } 629 630 return patch_size; 631 } 632 633 /* 634 * Those patch levels cannot be updated to newer ones and thus should be final. 635 */ 636 static u32 final_levels[] = { 637 0x01000098, 638 0x0100009f, 639 0x010000af, 640 0, /* T-101 terminator */ 641 }; 642 643 /* 644 * Check the current patch level on this CPU. 645 * 646 * @rev: Use it to return the patch level. It is set to 0 in the case of 647 * error. 648 * 649 * Returns: 650 * - true: if update should stop 651 * - false: otherwise 652 */ 653 bool check_current_patch_level(u32 *rev, bool early) 654 { 655 u32 lvl, dummy, i; 656 bool ret = false; 657 u32 *levels; 658 659 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); 660 661 if (IS_ENABLED(CONFIG_X86_32) && early) 662 levels = (u32 *)__pa_nodebug(&final_levels); 663 else 664 levels = final_levels; 665 666 for (i = 0; levels[i]; i++) { 667 if (lvl == levels[i]) { 668 lvl = 0; 669 ret = true; 670 break; 671 } 672 } 673 674 if (rev) 675 *rev = lvl; 676 677 return ret; 678 } 679 680 static int apply_microcode_amd(int cpu) 681 { 682 struct cpuinfo_x86 *c = &cpu_data(cpu); 683 struct microcode_amd *mc_amd; 684 struct ucode_cpu_info *uci; 685 struct ucode_patch *p; 686 u32 rev; 687 688 BUG_ON(raw_smp_processor_id() != cpu); 689 690 uci = ucode_cpu_info + cpu; 691 692 p = find_patch(cpu); 693 if (!p) 694 return 0; 695 696 mc_amd = p->data; 697 uci->mc = p->data; 698 699 if (check_current_patch_level(&rev, false)) 700 return -1; 701 702 /* need to apply patch? */ 703 if (rev >= mc_amd->hdr.patch_id) { 704 c->microcode = rev; 705 uci->cpu_sig.rev = rev; 706 return 0; 707 } 708 709 if (__apply_microcode_amd(mc_amd)) { 710 pr_err("CPU%d: update failed for patch_level=0x%08x\n", 711 cpu, mc_amd->hdr.patch_id); 712 return -1; 713 } 714 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, 715 mc_amd->hdr.patch_id); 716 717 uci->cpu_sig.rev = mc_amd->hdr.patch_id; 718 c->microcode = mc_amd->hdr.patch_id; 719 720 return 0; 721 } 722 723 static int install_equiv_cpu_table(const u8 *buf) 724 { 725 unsigned int *ibuf = (unsigned int *)buf; 726 unsigned int type = ibuf[1]; 727 unsigned int size = ibuf[2]; 728 729 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { 730 pr_err("empty section/" 731 "invalid type field in container file section header\n"); 732 return -EINVAL; 733 } 734 735 equiv_cpu_table = vmalloc(size); 736 if (!equiv_cpu_table) { 737 pr_err("failed to allocate equivalent CPU table\n"); 738 return -ENOMEM; 739 } 740 741 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size); 742 743 /* add header length */ 744 return size + CONTAINER_HDR_SZ; 745 } 746 747 static void free_equiv_cpu_table(void) 748 { 749 vfree(equiv_cpu_table); 750 equiv_cpu_table = NULL; 751 } 752 753 static void cleanup(void) 754 { 755 free_equiv_cpu_table(); 756 free_cache(); 757 } 758 759 /* 760 * We return the current size even if some of the checks failed so that 761 * we can skip over the next patch. If we return a negative value, we 762 * signal a grave error like a memory allocation has failed and the 763 * driver cannot continue functioning normally. In such cases, we tear 764 * down everything we've used up so far and exit. 765 */ 766 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover) 767 { 768 struct microcode_header_amd *mc_hdr; 769 struct ucode_patch *patch; 770 unsigned int patch_size, crnt_size, ret; 771 u32 proc_fam; 772 u16 proc_id; 773 774 patch_size = *(u32 *)(fw + 4); 775 crnt_size = patch_size + SECTION_HDR_SIZE; 776 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE); 777 proc_id = mc_hdr->processor_rev_id; 778 779 proc_fam = find_cpu_family_by_equiv_cpu(proc_id); 780 if (!proc_fam) { 781 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id); 782 return crnt_size; 783 } 784 785 /* check if patch is for the current family */ 786 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff); 787 if (proc_fam != family) 788 return crnt_size; 789 790 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { 791 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", 792 mc_hdr->patch_id); 793 return crnt_size; 794 } 795 796 ret = verify_patch_size(family, patch_size, leftover); 797 if (!ret) { 798 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id); 799 return crnt_size; 800 } 801 802 patch = kzalloc(sizeof(*patch), GFP_KERNEL); 803 if (!patch) { 804 pr_err("Patch allocation failure.\n"); 805 return -EINVAL; 806 } 807 808 patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL); 809 if (!patch->data) { 810 pr_err("Patch data allocation failure.\n"); 811 kfree(patch); 812 return -EINVAL; 813 } 814 815 INIT_LIST_HEAD(&patch->plist); 816 patch->patch_id = mc_hdr->patch_id; 817 patch->equiv_cpu = proc_id; 818 819 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n", 820 __func__, patch->patch_id, proc_id); 821 822 /* ... and add to cache. */ 823 update_cache(patch); 824 825 return crnt_size; 826 } 827 828 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, 829 size_t size) 830 { 831 enum ucode_state ret = UCODE_ERROR; 832 unsigned int leftover; 833 u8 *fw = (u8 *)data; 834 int crnt_size = 0; 835 int offset; 836 837 offset = install_equiv_cpu_table(data); 838 if (offset < 0) { 839 pr_err("failed to create equivalent cpu table\n"); 840 return ret; 841 } 842 fw += offset; 843 leftover = size - offset; 844 845 if (*(u32 *)fw != UCODE_UCODE_TYPE) { 846 pr_err("invalid type field in container file section header\n"); 847 free_equiv_cpu_table(); 848 return ret; 849 } 850 851 while (leftover) { 852 crnt_size = verify_and_add_patch(family, fw, leftover); 853 if (crnt_size < 0) 854 return ret; 855 856 fw += crnt_size; 857 leftover -= crnt_size; 858 } 859 860 return UCODE_OK; 861 } 862 863 static enum ucode_state 864 load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size) 865 { 866 enum ucode_state ret; 867 868 /* free old equiv table */ 869 free_equiv_cpu_table(); 870 871 ret = __load_microcode_amd(family, data, size); 872 873 if (ret != UCODE_OK) 874 cleanup(); 875 876 #ifdef CONFIG_X86_32 877 /* save BSP's matching patch for early load */ 878 if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) { 879 struct ucode_patch *p = find_patch(cpu); 880 if (p) { 881 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); 882 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), 883 PATCH_MAX_SIZE)); 884 } 885 } 886 #endif 887 return ret; 888 } 889 890 /* 891 * AMD microcode firmware naming convention, up to family 15h they are in 892 * the legacy file: 893 * 894 * amd-ucode/microcode_amd.bin 895 * 896 * This legacy file is always smaller than 2K in size. 897 * 898 * Beginning with family 15h, they are in family-specific firmware files: 899 * 900 * amd-ucode/microcode_amd_fam15h.bin 901 * amd-ucode/microcode_amd_fam16h.bin 902 * ... 903 * 904 * These might be larger than 2K. 905 */ 906 static enum ucode_state request_microcode_amd(int cpu, struct device *device, 907 bool refresh_fw) 908 { 909 char fw_name[36] = "amd-ucode/microcode_amd.bin"; 910 struct cpuinfo_x86 *c = &cpu_data(cpu); 911 enum ucode_state ret = UCODE_NFOUND; 912 const struct firmware *fw; 913 914 /* reload ucode container only on the boot cpu */ 915 if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index) 916 return UCODE_OK; 917 918 if (c->x86 >= 0x15) 919 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); 920 921 if (request_firmware_direct(&fw, (const char *)fw_name, device)) { 922 pr_debug("failed to load file %s\n", fw_name); 923 goto out; 924 } 925 926 ret = UCODE_ERROR; 927 if (*(u32 *)fw->data != UCODE_MAGIC) { 928 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); 929 goto fw_release; 930 } 931 932 ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size); 933 934 fw_release: 935 release_firmware(fw); 936 937 out: 938 return ret; 939 } 940 941 static enum ucode_state 942 request_microcode_user(int cpu, const void __user *buf, size_t size) 943 { 944 return UCODE_ERROR; 945 } 946 947 static void microcode_fini_cpu_amd(int cpu) 948 { 949 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 950 951 uci->mc = NULL; 952 } 953 954 static struct microcode_ops microcode_amd_ops = { 955 .request_microcode_user = request_microcode_user, 956 .request_microcode_fw = request_microcode_amd, 957 .collect_cpu_info = collect_cpu_info_amd, 958 .apply_microcode = apply_microcode_amd, 959 .microcode_fini_cpu = microcode_fini_cpu_amd, 960 }; 961 962 struct microcode_ops * __init init_amd_microcode(void) 963 { 964 struct cpuinfo_x86 *c = &boot_cpu_data; 965 966 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { 967 pr_warn("AMD CPU family 0x%x not supported\n", c->x86); 968 return NULL; 969 } 970 971 if (ucode_new_rev) 972 pr_info_once("microcode updated early to new patch_level=0x%08x\n", 973 ucode_new_rev); 974 975 return µcode_amd_ops; 976 } 977 978 void __exit exit_amd_microcode(void) 979 { 980 cleanup(); 981 } 982