1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MCE grading rules. 4 * Copyright 2008, 2009 Intel Corporation. 5 * 6 * Author: Andi Kleen 7 */ 8 #include <linux/kernel.h> 9 #include <linux/seq_file.h> 10 #include <linux/init.h> 11 #include <linux/debugfs.h> 12 #include <linux/uaccess.h> 13 14 #include <asm/mce.h> 15 #include <asm/intel-family.h> 16 17 #include "internal.h" 18 19 /* 20 * Grade an mce by severity. In general the most severe ones are processed 21 * first. Since there are quite a lot of combinations test the bits in a 22 * table-driven way. The rules are simply processed in order, first 23 * match wins. 24 * 25 * Note this is only used for machine check exceptions, the corrected 26 * errors use much simpler rules. The exceptions still check for the corrected 27 * errors, but only to leave them alone for the CMCI handler (except for 28 * panic situations) 29 */ 30 31 enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 }; 32 enum ser { SER_REQUIRED = 1, NO_SER = 2 }; 33 enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 }; 34 35 static struct severity { 36 u64 mask; 37 u64 result; 38 unsigned char sev; 39 unsigned char mcgmask; 40 unsigned char mcgres; 41 unsigned char ser; 42 unsigned char context; 43 unsigned char excp; 44 unsigned char covered; 45 unsigned char cpu_model; 46 unsigned char cpu_minstepping; 47 unsigned char bank_lo, bank_hi; 48 char *msg; 49 } severities[] = { 50 #define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c } 51 #define BANK_RANGE(l, h) .bank_lo = l, .bank_hi = h 52 #define MODEL_STEPPING(m, s) .cpu_model = m, .cpu_minstepping = s 53 #define KERNEL .context = IN_KERNEL 54 #define USER .context = IN_USER 55 #define KERNEL_RECOV .context = IN_KERNEL_RECOV 56 #define SER .ser = SER_REQUIRED 57 #define NOSER .ser = NO_SER 58 #define EXCP .excp = EXCP_CONTEXT 59 #define NOEXCP .excp = NO_EXCP 60 #define BITCLR(x) .mask = x, .result = 0 61 #define BITSET(x) .mask = x, .result = x 62 #define MCGMASK(x, y) .mcgmask = x, .mcgres = y 63 #define MASK(x, y) .mask = x, .result = y 64 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S) 65 #define MCI_UC_AR (MCI_STATUS_UC|MCI_STATUS_AR) 66 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR) 67 #define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV) 68 69 MCESEV( 70 NO, "Invalid", 71 BITCLR(MCI_STATUS_VAL) 72 ), 73 MCESEV( 74 NO, "Not enabled", 75 EXCP, BITCLR(MCI_STATUS_EN) 76 ), 77 MCESEV( 78 PANIC, "Processor context corrupt", 79 BITSET(MCI_STATUS_PCC) 80 ), 81 /* When MCIP is not set something is very confused */ 82 MCESEV( 83 PANIC, "MCIP not set in MCA handler", 84 EXCP, MCGMASK(MCG_STATUS_MCIP, 0) 85 ), 86 /* Neither return not error IP -- no chance to recover -> PANIC */ 87 MCESEV( 88 PANIC, "Neither restart nor error IP", 89 EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0) 90 ), 91 MCESEV( 92 PANIC, "In kernel and no restart IP", 93 EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0) 94 ), 95 MCESEV( 96 PANIC, "In kernel and no restart IP", 97 EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0) 98 ), 99 MCESEV( 100 KEEP, "Corrected error", 101 NOSER, BITCLR(MCI_STATUS_UC) 102 ), 103 /* 104 * known AO MCACODs reported via MCE or CMC: 105 * 106 * SRAO could be signaled either via a machine check exception or 107 * CMCI with the corresponding bit S 1 or 0. So we don't need to 108 * check bit S for SRAO. 109 */ 110 MCESEV( 111 AO, "Action optional: memory scrubbing error", 112 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB) 113 ), 114 MCESEV( 115 AO, "Action optional: last level cache writeback error", 116 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB) 117 ), 118 /* 119 * Quirk for Skylake/Cascade Lake. Patrol scrubber may be configured 120 * to report uncorrected errors using CMCI with a special signature. 121 * UC=0, MSCOD=0x0010, MCACOD=binary(000X 0000 1100 XXXX) reported 122 * in one of the memory controller banks. 123 * Set severity to "AO" for same action as normal patrol scrub error. 124 */ 125 MCESEV( 126 AO, "Uncorrected Patrol Scrub Error", 127 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0), 128 MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18) 129 ), 130 131 /* ignore OVER for UCNA */ 132 MCESEV( 133 UCNA, "Uncorrected no action required", 134 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC) 135 ), 136 MCESEV( 137 PANIC, "Illegal combination (UCNA with AR=1)", 138 SER, 139 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR) 140 ), 141 MCESEV( 142 KEEP, "Non signalled machine check", 143 SER, BITCLR(MCI_STATUS_S) 144 ), 145 146 MCESEV( 147 PANIC, "Action required with lost events", 148 SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR) 149 ), 150 151 /* known AR MCACODs: */ 152 #ifdef CONFIG_MEMORY_FAILURE 153 MCESEV( 154 KEEP, "Action required but unaffected thread is continuable", 155 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR), 156 MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV) 157 ), 158 MCESEV( 159 AR, "Action required: data load in error recoverable area of kernel", 160 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), 161 KERNEL_RECOV 162 ), 163 MCESEV( 164 AR, "Action required: data load error in a user process", 165 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), 166 USER 167 ), 168 MCESEV( 169 AR, "Action required: instruction fetch error in a user process", 170 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), 171 USER 172 ), 173 MCESEV( 174 PANIC, "Data load in unrecoverable area of kernel", 175 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), 176 KERNEL 177 ), 178 MCESEV( 179 PANIC, "Instruction fetch error in kernel", 180 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), 181 KERNEL 182 ), 183 #endif 184 MCESEV( 185 PANIC, "Action required: unknown MCACOD", 186 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR) 187 ), 188 189 MCESEV( 190 SOME, "Action optional: unknown MCACOD", 191 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S) 192 ), 193 MCESEV( 194 SOME, "Action optional with lost events", 195 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S) 196 ), 197 198 MCESEV( 199 PANIC, "Overflowed uncorrected", 200 BITSET(MCI_STATUS_OVER|MCI_STATUS_UC) 201 ), 202 MCESEV( 203 UC, "Uncorrected", 204 BITSET(MCI_STATUS_UC) 205 ), 206 MCESEV( 207 SOME, "No match", 208 BITSET(0) 209 ) /* always matches. keep at end */ 210 }; 211 212 #define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \ 213 (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) 214 215 /* 216 * If mcgstatus indicated that ip/cs on the stack were 217 * no good, then "m->cs" will be zero and we will have 218 * to assume the worst case (IN_KERNEL) as we actually 219 * have no idea what we were executing when the machine 220 * check hit. 221 * If we do have a good "m->cs" (or a faked one in the 222 * case we were executing in VM86 mode) we can use it to 223 * distinguish an exception taken in user from from one 224 * taken in the kernel. 225 */ 226 static int error_context(struct mce *m) 227 { 228 if ((m->cs & 3) == 3) 229 return IN_USER; 230 231 if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip)) { 232 m->kflags |= MCE_IN_KERNEL_RECOV; 233 return IN_KERNEL_RECOV; 234 } 235 236 return IN_KERNEL; 237 } 238 239 static int mce_severity_amd_smca(struct mce *m, enum context err_ctx) 240 { 241 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); 242 u32 low, high; 243 244 /* 245 * We need to look at the following bits: 246 * - "succor" bit (data poisoning support), and 247 * - TCC bit (Task Context Corrupt) 248 * in MCi_STATUS to determine error severity. 249 */ 250 if (!mce_flags.succor) 251 return MCE_PANIC_SEVERITY; 252 253 if (rdmsr_safe(addr, &low, &high)) 254 return MCE_PANIC_SEVERITY; 255 256 /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */ 257 if ((low & MCI_CONFIG_MCAX) && 258 (m->status & MCI_STATUS_TCC) && 259 (err_ctx == IN_KERNEL)) 260 return MCE_PANIC_SEVERITY; 261 262 /* ...otherwise invoke hwpoison handler. */ 263 return MCE_AR_SEVERITY; 264 } 265 266 /* 267 * See AMD Error Scope Hierarchy table in a newer BKDG. For example 268 * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features" 269 */ 270 static int mce_severity_amd(struct mce *m, int tolerant, char **msg, bool is_excp) 271 { 272 enum context ctx = error_context(m); 273 274 /* Processor Context Corrupt, no need to fumble too much, die! */ 275 if (m->status & MCI_STATUS_PCC) 276 return MCE_PANIC_SEVERITY; 277 278 if (m->status & MCI_STATUS_UC) { 279 280 if (ctx == IN_KERNEL) 281 return MCE_PANIC_SEVERITY; 282 283 /* 284 * On older systems where overflow_recov flag is not present, we 285 * should simply panic if an error overflow occurs. If 286 * overflow_recov flag is present and set, then software can try 287 * to at least kill process to prolong system operation. 288 */ 289 if (mce_flags.overflow_recov) { 290 if (mce_flags.smca) 291 return mce_severity_amd_smca(m, ctx); 292 293 /* kill current process */ 294 return MCE_AR_SEVERITY; 295 } else { 296 /* at least one error was not logged */ 297 if (m->status & MCI_STATUS_OVER) 298 return MCE_PANIC_SEVERITY; 299 } 300 301 /* 302 * For any other case, return MCE_UC_SEVERITY so that we log the 303 * error and exit #MC handler. 304 */ 305 return MCE_UC_SEVERITY; 306 } 307 308 /* 309 * deferred error: poll handler catches these and adds to mce_ring so 310 * memory-failure can take recovery actions. 311 */ 312 if (m->status & MCI_STATUS_DEFERRED) 313 return MCE_DEFERRED_SEVERITY; 314 315 /* 316 * corrected error: poll handler catches these and passes responsibility 317 * of decoding the error to EDAC 318 */ 319 return MCE_KEEP_SEVERITY; 320 } 321 322 static int mce_severity_intel(struct mce *m, int tolerant, char **msg, bool is_excp) 323 { 324 enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP); 325 enum context ctx = error_context(m); 326 struct severity *s; 327 328 for (s = severities;; s++) { 329 if ((m->status & s->mask) != s->result) 330 continue; 331 if ((m->mcgstatus & s->mcgmask) != s->mcgres) 332 continue; 333 if (s->ser == SER_REQUIRED && !mca_cfg.ser) 334 continue; 335 if (s->ser == NO_SER && mca_cfg.ser) 336 continue; 337 if (s->context && ctx != s->context) 338 continue; 339 if (s->excp && excp != s->excp) 340 continue; 341 if (s->cpu_model && boot_cpu_data.x86_model != s->cpu_model) 342 continue; 343 if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping) 344 continue; 345 if (s->bank_lo && (m->bank < s->bank_lo || m->bank > s->bank_hi)) 346 continue; 347 if (msg) 348 *msg = s->msg; 349 s->covered = 1; 350 if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) { 351 if (tolerant < 1) 352 return MCE_PANIC_SEVERITY; 353 } 354 return s->sev; 355 } 356 } 357 358 /* Default to mce_severity_intel */ 359 int (*mce_severity)(struct mce *m, int tolerant, char **msg, bool is_excp) = 360 mce_severity_intel; 361 362 void __init mcheck_vendor_init_severity(void) 363 { 364 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 365 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 366 mce_severity = mce_severity_amd; 367 } 368 369 #ifdef CONFIG_DEBUG_FS 370 static void *s_start(struct seq_file *f, loff_t *pos) 371 { 372 if (*pos >= ARRAY_SIZE(severities)) 373 return NULL; 374 return &severities[*pos]; 375 } 376 377 static void *s_next(struct seq_file *f, void *data, loff_t *pos) 378 { 379 if (++(*pos) >= ARRAY_SIZE(severities)) 380 return NULL; 381 return &severities[*pos]; 382 } 383 384 static void s_stop(struct seq_file *f, void *data) 385 { 386 } 387 388 static int s_show(struct seq_file *f, void *data) 389 { 390 struct severity *ser = data; 391 seq_printf(f, "%d\t%s\n", ser->covered, ser->msg); 392 return 0; 393 } 394 395 static const struct seq_operations severities_seq_ops = { 396 .start = s_start, 397 .next = s_next, 398 .stop = s_stop, 399 .show = s_show, 400 }; 401 402 static int severities_coverage_open(struct inode *inode, struct file *file) 403 { 404 return seq_open(file, &severities_seq_ops); 405 } 406 407 static ssize_t severities_coverage_write(struct file *file, 408 const char __user *ubuf, 409 size_t count, loff_t *ppos) 410 { 411 int i; 412 for (i = 0; i < ARRAY_SIZE(severities); i++) 413 severities[i].covered = 0; 414 return count; 415 } 416 417 static const struct file_operations severities_coverage_fops = { 418 .open = severities_coverage_open, 419 .release = seq_release, 420 .read = seq_read, 421 .write = severities_coverage_write, 422 .llseek = seq_lseek, 423 }; 424 425 static int __init severities_debugfs_init(void) 426 { 427 struct dentry *dmce; 428 429 dmce = mce_get_debugfs_dir(); 430 431 debugfs_create_file("severities-coverage", 0444, dmce, NULL, 432 &severities_coverage_fops); 433 return 0; 434 } 435 late_initcall(severities_debugfs_init); 436 #endif /* CONFIG_DEBUG_FS */ 437