1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 */ 8 #include <linux/interrupt.h> 9 #include <linux/notifier.h> 10 #include <linux/kobject.h> 11 #include <linux/percpu.h> 12 #include <linux/errno.h> 13 #include <linux/sched.h> 14 #include <linux/sysfs.h> 15 #include <linux/slab.h> 16 #include <linux/init.h> 17 #include <linux/cpu.h> 18 #include <linux/smp.h> 19 #include <linux/string.h> 20 21 #include <asm/traps.h> 22 #include <asm/apic.h> 23 #include <asm/mce.h> 24 #include <asm/msr.h> 25 #include <asm/trace/irq_vectors.h> 26 27 #include "internal.h" 28 29 #define NR_BLOCKS 5 30 #define THRESHOLD_MAX 0xFFF 31 #define INT_TYPE_APIC 0x00020000 32 #define MASK_VALID_HI 0x80000000 33 #define MASK_CNTP_HI 0x40000000 34 #define MASK_LOCKED_HI 0x20000000 35 #define MASK_LVTOFF_HI 0x00F00000 36 #define MASK_COUNT_EN_HI 0x00080000 37 #define MASK_INT_TYPE_HI 0x00060000 38 #define MASK_OVERFLOW_HI 0x00010000 39 #define MASK_ERR_COUNT_HI 0x00000FFF 40 #define MASK_BLKPTR_LO 0xFF000000 41 #define MCG_XBLK_ADDR 0xC0000400 42 43 /* Deferred error settings */ 44 #define MSR_CU_DEF_ERR 0xC0000410 45 #define MASK_DEF_LVTOFF 0x000000F0 46 47 /* Scalable MCA: */ 48 49 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 50 #define SMCA_THR_LVT_OFF 0xF000 51 52 static bool thresholding_irq_en; 53 54 struct mce_amd_cpu_data { 55 mce_banks_t thr_intr_banks; 56 mce_banks_t dfr_intr_banks; 57 58 u32 thr_intr_en: 1, 59 dfr_intr_en: 1, 60 __resv: 30; 61 }; 62 63 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); 64 65 static const char * const th_names[] = { 66 "load_store", 67 "insn_fetch", 68 "combined_unit", 69 "decode_unit", 70 "northbridge", 71 "execution_unit", 72 }; 73 74 static const char * const smca_umc_block_names[] = { 75 "dram_ecc", 76 "misc_umc" 77 }; 78 79 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) 80 81 struct smca_hwid { 82 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ 83 u32 hwid_mcatype; /* (hwid,mcatype) tuple */ 84 }; 85 86 struct smca_bank { 87 const struct smca_hwid *hwid; 88 u32 id; /* Value of MCA_IPID[InstanceId]. */ 89 u8 sysfs_id; /* Value used for sysfs name. */ 90 u64 paddrv :1, /* Physical Address Valid bit in MCA_CONFIG */ 91 __reserved :63; 92 }; 93 94 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); 95 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); 96 97 static const char * const smca_names[] = { 98 [SMCA_CS ... SMCA_CS_V2] = "coherent_station", 99 [SMCA_DACC_BE] = "dacc_be", 100 [SMCA_DACC_FE] = "dacc_fe", 101 [SMCA_DE] = "decode_unit", 102 [SMCA_EDDR5CMN] = "eddr5_cmn", 103 [SMCA_EX] = "execution_unit", 104 [SMCA_FP] = "floating_point", 105 [SMCA_GMI_PCS] = "gmi_pcs", 106 [SMCA_GMI_PHY] = "gmi_phy", 107 [SMCA_IF] = "insn_fetch", 108 [SMCA_L2_CACHE] = "l2_cache", 109 [SMCA_L3_CACHE] = "l3_cache", 110 [SMCA_LS ... SMCA_LS_V2] = "load_store", 111 [SMCA_MA_LLC] = "ma_llc", 112 [SMCA_MP5] = "mp5", 113 [SMCA_MPART] = "mpart", 114 [SMCA_MPASP ... SMCA_MPASP_V2] = "mpasp", 115 [SMCA_MPDACC] = "mpdacc", 116 [SMCA_MPDMA] = "mpdma", 117 [SMCA_MPM] = "mpm", 118 [SMCA_MPRAS] = "mpras", 119 [SMCA_NBIF] = "nbif", 120 [SMCA_NBIO] = "nbio", 121 [SMCA_PB] = "param_block", 122 [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", 123 [SMCA_PCIE_PL] = "pcie_pl", 124 [SMCA_PIE] = "pie", 125 [SMCA_PSP ... SMCA_PSP_V2] = "psp", 126 [SMCA_RESERVED] = "reserved", 127 [SMCA_SATA] = "sata", 128 [SMCA_SHUB] = "shub", 129 [SMCA_SMU ... SMCA_SMU_V2] = "smu", 130 [SMCA_SSBDCI] = "ssbdci", 131 132 /* UMC v2 is separate because both of them can exist in a single system. */ 133 [SMCA_UMC] = "umc", 134 [SMCA_UMC_V2] = "umc_v2", 135 [SMCA_USB] = "usb", 136 [SMCA_USR_CP] = "usr_cp", 137 [SMCA_USR_DP] = "usr_dp", 138 [SMCA_WAFL_PHY] = "wafl_phy", 139 [SMCA_XGMI_PCS] = "xgmi_pcs", 140 [SMCA_XGMI_PHY] = "xgmi_phy", 141 }; 142 143 static const char *smca_get_name(enum smca_bank_types t) 144 { 145 if (t >= N_SMCA_BANK_TYPES) 146 return NULL; 147 148 return smca_names[t]; 149 } 150 151 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) 152 { 153 struct smca_bank *b; 154 155 if (bank >= MAX_NR_BANKS) 156 return N_SMCA_BANK_TYPES; 157 158 b = &per_cpu(smca_banks, cpu)[bank]; 159 if (!b->hwid) 160 return N_SMCA_BANK_TYPES; 161 162 return b->hwid->bank_type; 163 } 164 EXPORT_SYMBOL_GPL(smca_get_bank_type); 165 166 /* 167 * Format: 168 * { bank_type, hwid_mcatype } 169 * 170 * alphanumerically sorted by bank type. 171 */ 172 static const struct smca_hwid smca_hwid_mcatypes[] = { 173 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 174 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 175 { SMCA_DACC_BE, HWID_MCATYPE(0x164, 0x0) }, 176 { SMCA_DACC_FE, HWID_MCATYPE(0x157, 0x0) }, 177 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 178 { SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0) }, 179 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 180 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 181 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 182 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 183 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 184 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 185 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 186 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 187 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 188 { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, 189 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 190 { SMCA_MPART, HWID_MCATYPE(0xFF, 0x2) }, 191 { SMCA_MPASP, HWID_MCATYPE(0xFD, 0x0) }, 192 { SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1) }, 193 { SMCA_MPDACC, HWID_MCATYPE(0xBE, 0x0) }, 194 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 195 { SMCA_MPM, HWID_MCATYPE(0xF9, 0x0) }, 196 { SMCA_MPRAS, HWID_MCATYPE(0x12, 0x0) }, 197 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 198 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 199 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 200 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 201 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 202 { SMCA_PCIE_PL, HWID_MCATYPE(0x1E1, 0x0) }, 203 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 204 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 205 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 206 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 207 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 208 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 209 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 210 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 211 { SMCA_SSBDCI, HWID_MCATYPE(0x5C, 0x0) }, 212 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 213 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 214 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 215 { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, 216 { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, 217 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 218 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 219 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 220 }; 221 222 /* 223 * In SMCA enabled processors, we can have multiple banks for a given IP type. 224 * So to define a unique name for each bank, we use a temp c-string to append 225 * the MCA_IPID[InstanceId] to type's name in get_name(). 226 * 227 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 228 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 229 */ 230 #define MAX_MCATYPE_NAME_LEN 30 231 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 232 233 struct threshold_block { 234 /* This block's number within its bank. */ 235 unsigned int block; 236 /* MCA bank number that contains this block. */ 237 unsigned int bank; 238 /* CPU which controls this block's MCA bank. */ 239 unsigned int cpu; 240 /* MCA_MISC MSR address for this block. */ 241 u32 address; 242 /* Enable/Disable APIC interrupt. */ 243 bool interrupt_enable; 244 /* Bank can generate an interrupt. */ 245 bool interrupt_capable; 246 /* Value upon which threshold interrupt is generated. */ 247 u16 threshold_limit; 248 /* sysfs object */ 249 struct kobject kobj; 250 /* List of threshold blocks within this block's MCA bank. */ 251 struct list_head miscj; 252 }; 253 254 struct threshold_bank { 255 struct kobject *kobj; 256 /* List of threshold blocks within this MCA bank. */ 257 struct list_head miscj; 258 }; 259 260 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 261 262 /* 263 * A list of the banks enabled on each logical CPU. Controls which respective 264 * descriptors to initialize later in mce_threshold_create_device(). 265 */ 266 static DEFINE_PER_CPU(u64, bank_map); 267 268 static void amd_threshold_interrupt(void); 269 static void amd_deferred_error_interrupt(void); 270 271 static void default_deferred_error_interrupt(void) 272 { 273 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 274 } 275 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 276 277 static void smca_configure(unsigned int bank, unsigned int cpu) 278 { 279 struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data); 280 u8 *bank_counts = this_cpu_ptr(smca_bank_counts); 281 const struct smca_hwid *s_hwid; 282 unsigned int i, hwid_mcatype; 283 struct msr val; 284 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 285 286 /* Set appropriate bits in MCA_CONFIG */ 287 if (!rdmsrq_safe(smca_config, &val.q)) { 288 /* 289 * OS is required to set the MCAX bit to acknowledge that it is 290 * now using the new MSR ranges and new registers under each 291 * bank. It also means that the OS will configure deferred 292 * errors in the new MCx_CONFIG register. If the bit is not set, 293 * uncorrectable errors will cause a system panic. 294 * 295 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 296 */ 297 val.h |= BIT(0); 298 299 /* 300 * SMCA sets the Deferred Error Interrupt type per bank. 301 * 302 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 303 * if the DeferredIntType bit field is available. 304 * 305 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 306 * high portion of the MSR). OS should set this to 0x1 to enable 307 * APIC based interrupt. First, check that no interrupt has been 308 * set. 309 */ 310 if ((val.l & BIT(5)) && !((val.h >> 5) & 0x3) && data->dfr_intr_en) { 311 __set_bit(bank, data->dfr_intr_banks); 312 val.h |= BIT(5); 313 } 314 315 /* 316 * SMCA Corrected Error Interrupt 317 * 318 * MCA_CONFIG[IntPresent] is bit 10, and tells us if the bank can 319 * send an MCA Thresholding interrupt without the OS initializing 320 * this feature. This can be used if the threshold limit is managed 321 * by the platform. 322 * 323 * MCA_CONFIG[IntEn] is bit 40 (8 in the high portion of the MSR). 324 * The OS should set this to inform the platform that the OS is ready 325 * to handle the MCA Thresholding interrupt. 326 */ 327 if ((val.l & BIT(10)) && data->thr_intr_en) { 328 __set_bit(bank, data->thr_intr_banks); 329 val.h |= BIT(8); 330 } 331 332 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(val.l & BIT(8)); 333 334 if (val.l & MCI_CONFIG_PADDRV) 335 this_cpu_ptr(smca_banks)[bank].paddrv = 1; 336 337 wrmsrq(smca_config, val.q); 338 } 339 340 if (rdmsrq_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &val.q)) { 341 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 342 return; 343 } 344 345 hwid_mcatype = HWID_MCATYPE(val.h & MCI_IPID_HWID, 346 (val.h & MCI_IPID_MCATYPE) >> 16); 347 348 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 349 s_hwid = &smca_hwid_mcatypes[i]; 350 351 if (hwid_mcatype == s_hwid->hwid_mcatype) { 352 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; 353 this_cpu_ptr(smca_banks)[bank].id = val.l; 354 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; 355 break; 356 } 357 } 358 } 359 360 struct thresh_restart { 361 struct threshold_block *b; 362 int set_lvt_off; 363 int lvt_off; 364 u16 old_limit; 365 }; 366 367 static const char *bank4_names(const struct threshold_block *b) 368 { 369 switch (b->address) { 370 /* MSR4_MISC0 */ 371 case 0x00000413: 372 return "dram"; 373 374 case 0xc0000408: 375 return "ht_links"; 376 377 case 0xc0000409: 378 return "l3_cache"; 379 380 default: 381 WARN(1, "Funny MSR: 0x%08x\n", b->address); 382 return ""; 383 } 384 }; 385 386 387 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 388 { 389 /* 390 * bank 4 supports APIC LVT interrupts implicitly since forever. 391 */ 392 if (bank == 4) 393 return true; 394 395 /* 396 * IntP: interrupt present; if this bit is set, the thresholding 397 * bank can generate APIC LVT interrupts 398 */ 399 return msr_high_bits & BIT(28); 400 } 401 402 static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 403 { 404 int msr = (hi & MASK_LVTOFF_HI) >> 20; 405 406 /* 407 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 408 * the BIOS provides the value. The original field where LVT offset 409 * was set is reserved. Return early here: 410 */ 411 if (mce_flags.smca) 412 return false; 413 414 if (apic < 0) { 415 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 416 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 417 b->bank, b->block, b->address, hi, lo); 418 return false; 419 } 420 421 if (apic != msr) { 422 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 423 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 424 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 425 return false; 426 } 427 428 return true; 429 }; 430 431 /* Reprogram MCx_MISC MSR behind this threshold block. */ 432 static void threshold_restart_block(void *_tr) 433 { 434 struct thresh_restart *tr = _tr; 435 struct msr val; 436 437 /* sysfs write might race against an offline operation */ 438 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) 439 return; 440 441 rdmsrq(tr->b->address, val.q); 442 443 /* 444 * Reset error count and overflow bit. 445 * This is done during init or after handling an interrupt. 446 */ 447 if (val.h & MASK_OVERFLOW_HI || tr->set_lvt_off) { 448 val.h &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI); 449 val.h |= THRESHOLD_MAX - tr->b->threshold_limit; 450 } else if (tr->old_limit) { /* change limit w/o reset */ 451 int new_count = (val.h & THRESHOLD_MAX) + 452 (tr->old_limit - tr->b->threshold_limit); 453 454 val.h = (val.h & ~MASK_ERR_COUNT_HI) | 455 (new_count & THRESHOLD_MAX); 456 } 457 458 /* clear IntType */ 459 val.h &= ~MASK_INT_TYPE_HI; 460 461 if (!tr->b->interrupt_capable) 462 goto done; 463 464 if (tr->set_lvt_off) { 465 if (lvt_off_valid(tr->b, tr->lvt_off, val.l, val.h)) { 466 /* set new lvt offset */ 467 val.h &= ~MASK_LVTOFF_HI; 468 val.h |= tr->lvt_off << 20; 469 } 470 } 471 472 if (tr->b->interrupt_enable) 473 val.h |= INT_TYPE_APIC; 474 475 done: 476 477 val.h |= MASK_COUNT_EN_HI; 478 wrmsrq(tr->b->address, val.q); 479 } 480 481 static void threshold_restart_bank(unsigned int bank, bool intr_en) 482 { 483 struct threshold_bank **thr_banks = this_cpu_read(threshold_banks); 484 struct threshold_block *block, *tmp; 485 struct thresh_restart tr; 486 487 if (!thr_banks || !thr_banks[bank]) 488 return; 489 490 memset(&tr, 0, sizeof(tr)); 491 492 list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) { 493 tr.b = block; 494 tr.b->interrupt_enable = intr_en; 495 threshold_restart_block(&tr); 496 } 497 } 498 499 /* Try to use the threshold limit reported through APEI. */ 500 static u16 get_thr_limit(void) 501 { 502 u32 thr_limit = mce_get_apei_thr_limit(); 503 504 /* Fallback to old default if APEI limit is not available. */ 505 if (!thr_limit) 506 return THRESHOLD_MAX; 507 508 return min(thr_limit, THRESHOLD_MAX); 509 } 510 511 static void mce_threshold_block_init(struct threshold_block *b, int offset) 512 { 513 struct thresh_restart tr = { 514 .b = b, 515 .set_lvt_off = 1, 516 .lvt_off = offset, 517 }; 518 519 b->threshold_limit = get_thr_limit(); 520 threshold_restart_block(&tr); 521 }; 522 523 static int setup_APIC_mce_threshold(int reserved, int new) 524 { 525 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 526 APIC_DELIVERY_MODE_FIXED, 0)) 527 return new; 528 529 return reserved; 530 } 531 532 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 533 unsigned int bank, unsigned int block, 534 unsigned int cpu) 535 { 536 u32 addr = 0, offset = 0; 537 538 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 539 return addr; 540 541 if (mce_flags.smca) { 542 if (!block) 543 return MSR_AMD64_SMCA_MCx_MISC(bank); 544 545 if (!(low & MASK_BLKPTR_LO)) 546 return 0; 547 548 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 549 } 550 551 /* Fall back to method we used for older processors: */ 552 switch (block) { 553 case 0: 554 addr = mca_msr_reg(bank, MCA_MISC); 555 break; 556 case 1: 557 offset = ((low & MASK_BLKPTR_LO) >> 21); 558 if (offset) 559 addr = MCG_XBLK_ADDR + offset; 560 break; 561 default: 562 addr = ++current_addr; 563 } 564 return addr; 565 } 566 567 static int prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 568 int offset, u32 misc_high) 569 { 570 unsigned int cpu = smp_processor_id(); 571 struct threshold_block b; 572 int new; 573 574 if (!block) 575 per_cpu(bank_map, cpu) |= BIT_ULL(bank); 576 577 memset(&b, 0, sizeof(b)); 578 b.cpu = cpu; 579 b.bank = bank; 580 b.block = block; 581 b.address = addr; 582 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 583 584 if (!b.interrupt_capable) 585 goto done; 586 587 __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); 588 b.interrupt_enable = 1; 589 590 if (mce_flags.smca) 591 goto done; 592 593 new = (misc_high & MASK_LVTOFF_HI) >> 20; 594 offset = setup_APIC_mce_threshold(offset, new); 595 if (offset == new) 596 thresholding_irq_en = true; 597 598 done: 599 mce_threshold_block_init(&b, offset); 600 601 return offset; 602 } 603 604 bool amd_filter_mce(struct mce *m) 605 { 606 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); 607 struct cpuinfo_x86 *c = &boot_cpu_data; 608 609 /* Bogus hw errors on Cezanne A0. */ 610 if (c->x86 == 0x19 && 611 c->x86_model == 0x50 && 612 c->x86_stepping == 0x0) { 613 if (!(m->status & MCI_STATUS_EN)) 614 return true; 615 } 616 617 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 618 if (c->x86 == 0x17 && 619 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 620 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 621 return true; 622 623 /* NB GART TLB error reporting is disabled by default. */ 624 if (c->x86 < 0x17) { 625 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 626 return true; 627 } 628 629 return false; 630 } 631 632 /* 633 * Turn off thresholding banks for the following conditions: 634 * - MC4_MISC thresholding is not supported on Family 0x15. 635 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 636 * Models 0x10-0x2F due to Erratum #1114. 637 */ 638 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 639 { 640 int i, num_msrs; 641 u64 hwcr; 642 bool need_toggle; 643 u32 msrs[NR_BLOCKS]; 644 645 if (c->x86 == 0x15 && bank == 4) { 646 msrs[0] = 0x00000413; /* MC4_MISC0 */ 647 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 648 num_msrs = 2; 649 } else if (c->x86 == 0x17 && 650 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 651 652 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) 653 return; 654 655 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 656 num_msrs = 1; 657 } else { 658 return; 659 } 660 661 rdmsrq(MSR_K7_HWCR, hwcr); 662 663 /* McStatusWrEn has to be set */ 664 need_toggle = !(hwcr & BIT(18)); 665 if (need_toggle) 666 wrmsrq(MSR_K7_HWCR, hwcr | BIT(18)); 667 668 /* Clear CntP bit safely */ 669 for (i = 0; i < num_msrs; i++) 670 msr_clear_bit(msrs[i], 62); 671 672 /* restore old settings */ 673 if (need_toggle) 674 wrmsrq(MSR_K7_HWCR, hwcr); 675 } 676 677 static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c) 678 { 679 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 680 681 /* This should be disabled by the BIOS, but isn't always */ 682 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 683 /* 684 * disable GART TBL walk error reporting, which 685 * trips off incorrectly with the IOMMU & 3ware 686 * & Cerberus: 687 */ 688 clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 689 } 690 691 /* 692 * Various K7s with broken bank 0 around. Always disable 693 * by default. 694 */ 695 if (c->x86 == 6 && this_cpu_read(mce_num_banks)) 696 mce_banks[0].ctl = 0; 697 } 698 699 /* 700 * Enable the APIC LVT interrupt vectors once per-CPU. This should be done before hardware is 701 * ready to send interrupts. 702 * 703 * Individual error sources are enabled later during per-bank init. 704 */ 705 static void smca_enable_interrupt_vectors(void) 706 { 707 struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data); 708 u64 mca_intr_cfg, offset; 709 710 if (!mce_flags.smca || !mce_flags.succor) 711 return; 712 713 if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) 714 return; 715 716 offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; 717 if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_FIXED, 0)) 718 data->thr_intr_en = 1; 719 720 offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; 721 if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_FIXED, 0)) 722 data->dfr_intr_en = 1; 723 } 724 725 /* cpu init entry point, called from mce.c with preempt off */ 726 void mce_amd_feature_init(struct cpuinfo_x86 *c) 727 { 728 unsigned int bank, block, cpu = smp_processor_id(); 729 struct msr val = { .q = 0 }; 730 u32 address = 0; 731 int offset = -1; 732 733 amd_apply_cpu_quirks(c); 734 735 mce_flags.amd_threshold = 1; 736 737 smca_enable_interrupt_vectors(); 738 739 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 740 if (mce_flags.smca) { 741 smca_configure(bank, cpu); 742 743 if (!this_cpu_ptr(&mce_amd_data)->thr_intr_en) 744 continue; 745 } 746 747 disable_err_thresholding(c, bank); 748 749 for (block = 0; block < NR_BLOCKS; ++block) { 750 address = get_block_address(address, val.l, val.h, bank, block, cpu); 751 if (!address) 752 break; 753 754 if (rdmsrq_safe(address, &val.q)) 755 break; 756 757 if (!(val.h & MASK_VALID_HI)) 758 continue; 759 760 if (!(val.h & MASK_CNTP_HI) || 761 (val.h & MASK_LOCKED_HI)) 762 continue; 763 764 offset = prepare_threshold_block(bank, block, address, offset, val.h); 765 } 766 } 767 } 768 769 void smca_bsp_init(void) 770 { 771 mce_threshold_vector = amd_threshold_interrupt; 772 deferred_error_int_vector = amd_deferred_error_interrupt; 773 } 774 775 /* 776 * DRAM ECC errors are reported in the Northbridge (bank 4) with 777 * Extended Error Code 8. 778 */ 779 static bool legacy_mce_is_memory_error(struct mce *m) 780 { 781 return m->bank == 4 && XEC(m->status, 0x1f) == 8; 782 } 783 784 /* 785 * DRAM ECC errors are reported in Unified Memory Controllers with 786 * Extended Error Code 0. 787 */ 788 static bool smca_mce_is_memory_error(struct mce *m) 789 { 790 enum smca_bank_types bank_type; 791 792 if (XEC(m->status, 0x3f)) 793 return false; 794 795 bank_type = smca_get_bank_type(m->extcpu, m->bank); 796 797 return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2; 798 } 799 800 bool amd_mce_is_memory_error(struct mce *m) 801 { 802 if (mce_flags.smca) 803 return smca_mce_is_memory_error(m); 804 else 805 return legacy_mce_is_memory_error(m); 806 } 807 808 /* 809 * Some AMD systems have an explicit indicator that the value in MCA_ADDR is a 810 * system physical address. Individual cases though, need to be detected for 811 * other systems. Future cases will be added as needed. 812 * 813 * 1) General case 814 * a) Assume address is not usable. 815 * 2) Poison errors 816 * a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy 817 * northbridge (bank 4). 818 * b) Refers to poison consumption in the core. Does not include "no action", 819 * "action optional", or "deferred" error severities. 820 * c) Will include a usable address so that immediate action can be taken. 821 * 3) Northbridge DRAM ECC errors 822 * a) Reported in legacy bank 4 with extended error code (XEC) 8. 823 * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore, 824 * this bit should not be checked. 825 * 4) MCI_STATUS_PADDRVAL is set 826 * a) Will provide a valid system physical address. 827 * 828 * NOTE: SMCA UMC memory errors fall into case #1. 829 */ 830 bool amd_mce_usable_address(struct mce *m) 831 { 832 /* Check special northbridge case 3) first. */ 833 if (!mce_flags.smca) { 834 if (legacy_mce_is_memory_error(m)) 835 return true; 836 else if (m->bank == 4) 837 return false; 838 } 839 840 if (this_cpu_ptr(smca_banks)[m->bank].paddrv) 841 return m->status & MCI_STATUS_PADDRV; 842 843 /* Check poison bit for all other bank types. */ 844 if (m->status & MCI_STATUS_POISON) 845 return true; 846 847 /* Assume address is not usable for all others. */ 848 return false; 849 } 850 851 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 852 { 853 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 854 inc_irq_stat(DEFERRED_ERROR); 855 deferred_error_int_vector(); 856 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 857 apic_eoi(); 858 } 859 860 /* APIC interrupt handler for deferred errors */ 861 static void amd_deferred_error_interrupt(void) 862 { 863 machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_banks); 864 } 865 866 void mce_amd_handle_storm(unsigned int bank, bool on) 867 { 868 threshold_restart_bank(bank, on); 869 } 870 871 static void amd_reset_thr_limit(unsigned int bank) 872 { 873 threshold_restart_bank(bank, true); 874 } 875 876 /* 877 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 878 * goes off when error_count reaches threshold_limit. 879 */ 880 static void amd_threshold_interrupt(void) 881 { 882 machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->thr_intr_banks); 883 } 884 885 void amd_clear_bank(struct mce *m) 886 { 887 amd_reset_thr_limit(m->bank); 888 889 if (mce_flags.smca) { 890 /* 891 * Clear MCA_DESTAT for all deferred errors even those 892 * logged in MCA_STATUS. 893 */ 894 if (m->status & MCI_STATUS_DEFERRED) 895 mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); 896 897 /* Don't clear MCA_STATUS if MCA_DESTAT was used exclusively. */ 898 if (m->kflags & MCE_CHECK_DFR_REGS) 899 return; 900 } 901 902 mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0); 903 } 904 905 /* 906 * Sysfs Interface 907 */ 908 909 struct threshold_attr { 910 struct attribute attr; 911 ssize_t (*show) (struct threshold_block *, char *); 912 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 913 }; 914 915 #define SHOW_FIELDS(name) \ 916 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 917 { \ 918 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 919 } 920 SHOW_FIELDS(interrupt_enable) 921 SHOW_FIELDS(threshold_limit) 922 923 static ssize_t 924 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 925 { 926 struct thresh_restart tr; 927 unsigned long new; 928 929 if (!b->interrupt_capable) 930 return -EINVAL; 931 932 if (kstrtoul(buf, 0, &new) < 0) 933 return -EINVAL; 934 935 b->interrupt_enable = !!new; 936 937 memset(&tr, 0, sizeof(tr)); 938 tr.b = b; 939 940 if (smp_call_function_single(b->cpu, threshold_restart_block, &tr, 1)) 941 return -ENODEV; 942 943 return size; 944 } 945 946 static ssize_t 947 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 948 { 949 struct thresh_restart tr; 950 unsigned long new; 951 952 if (kstrtoul(buf, 0, &new) < 0) 953 return -EINVAL; 954 955 if (new > THRESHOLD_MAX) 956 new = THRESHOLD_MAX; 957 if (new < 1) 958 new = 1; 959 960 memset(&tr, 0, sizeof(tr)); 961 tr.old_limit = b->threshold_limit; 962 b->threshold_limit = new; 963 tr.b = b; 964 965 if (smp_call_function_single(b->cpu, threshold_restart_block, &tr, 1)) 966 return -ENODEV; 967 968 return size; 969 } 970 971 static ssize_t show_error_count(struct threshold_block *b, char *buf) 972 { 973 struct msr val; 974 975 /* CPU might be offline by now */ 976 if (rdmsrq_on_cpu(b->cpu, b->address, &val.q)) 977 return -ENODEV; 978 979 return sprintf(buf, "%u\n", ((val.h & THRESHOLD_MAX) - 980 (THRESHOLD_MAX - b->threshold_limit))); 981 } 982 983 static struct threshold_attr error_count = { 984 .attr = {.name = __stringify(error_count), .mode = 0444 }, 985 .show = show_error_count, 986 }; 987 988 #define RW_ATTR(val) \ 989 static struct threshold_attr val = { \ 990 .attr = {.name = __stringify(val), .mode = 0644 }, \ 991 .show = show_## val, \ 992 .store = store_## val, \ 993 }; 994 995 RW_ATTR(interrupt_enable); 996 RW_ATTR(threshold_limit); 997 998 static struct attribute *default_attrs[] = { 999 &threshold_limit.attr, 1000 &error_count.attr, 1001 NULL, /* possibly interrupt_enable if supported, see below */ 1002 NULL, 1003 }; 1004 ATTRIBUTE_GROUPS(default); 1005 1006 #define to_block(k) container_of(k, struct threshold_block, kobj) 1007 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1008 1009 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1010 { 1011 struct threshold_block *b = to_block(kobj); 1012 struct threshold_attr *a = to_attr(attr); 1013 ssize_t ret; 1014 1015 ret = a->show ? a->show(b, buf) : -EIO; 1016 1017 return ret; 1018 } 1019 1020 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1021 const char *buf, size_t count) 1022 { 1023 struct threshold_block *b = to_block(kobj); 1024 struct threshold_attr *a = to_attr(attr); 1025 ssize_t ret; 1026 1027 ret = a->store ? a->store(b, buf, count) : -EIO; 1028 1029 return ret; 1030 } 1031 1032 static const struct sysfs_ops threshold_ops = { 1033 .show = show, 1034 .store = store, 1035 }; 1036 1037 static void threshold_block_release(struct kobject *kobj); 1038 1039 static const struct kobj_type threshold_ktype = { 1040 .sysfs_ops = &threshold_ops, 1041 .default_groups = default_groups, 1042 .release = threshold_block_release, 1043 }; 1044 1045 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) 1046 { 1047 enum smca_bank_types bank_type; 1048 1049 if (!mce_flags.smca) { 1050 if (b && bank == 4) 1051 return bank4_names(b); 1052 1053 return th_names[bank]; 1054 } 1055 1056 bank_type = smca_get_bank_type(cpu, bank); 1057 1058 if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) { 1059 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1060 return smca_umc_block_names[b->block]; 1061 } 1062 1063 if (b && b->block) { 1064 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_block_%u", b->block); 1065 return buf_mcatype; 1066 } 1067 1068 if (bank_type >= N_SMCA_BANK_TYPES) { 1069 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_bank_%u", bank); 1070 return buf_mcatype; 1071 } 1072 1073 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) 1074 return smca_get_name(bank_type); 1075 1076 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1077 "%s_%u", smca_get_name(bank_type), 1078 per_cpu(smca_banks, cpu)[bank].sysfs_id); 1079 return buf_mcatype; 1080 } 1081 1082 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1083 unsigned int bank, unsigned int block, 1084 u32 address) 1085 { 1086 struct threshold_block *b = NULL; 1087 struct msr val; 1088 int err; 1089 1090 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1091 return 0; 1092 1093 if (rdmsrq_safe(address, &val.q)) 1094 return 0; 1095 1096 if (!(val.h & MASK_VALID_HI)) { 1097 if (block) 1098 goto recurse; 1099 else 1100 return 0; 1101 } 1102 1103 if (!(val.h & MASK_CNTP_HI) || 1104 (val.h & MASK_LOCKED_HI)) 1105 goto recurse; 1106 1107 b = kzalloc_obj(struct threshold_block); 1108 if (!b) 1109 return -ENOMEM; 1110 1111 b->block = block; 1112 b->bank = bank; 1113 b->cpu = cpu; 1114 b->address = address; 1115 b->interrupt_enable = 0; 1116 b->interrupt_capable = lvt_interrupt_supported(bank, val.h); 1117 b->threshold_limit = get_thr_limit(); 1118 1119 if (b->interrupt_capable) { 1120 default_attrs[2] = &interrupt_enable.attr; 1121 b->interrupt_enable = 1; 1122 } else { 1123 default_attrs[2] = NULL; 1124 } 1125 1126 list_add(&b->miscj, &tb->miscj); 1127 1128 mce_threshold_block_init(b, (val.h & MASK_LVTOFF_HI) >> 20); 1129 1130 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); 1131 if (err) 1132 goto out_free; 1133 recurse: 1134 address = get_block_address(address, val.l, val.h, bank, ++block, cpu); 1135 if (!address) 1136 return 0; 1137 1138 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1139 if (err) 1140 goto out_free; 1141 1142 if (b) 1143 kobject_uevent(&b->kobj, KOBJ_ADD); 1144 1145 return 0; 1146 1147 out_free: 1148 if (b) { 1149 list_del(&b->miscj); 1150 kobject_put(&b->kobj); 1151 } 1152 return err; 1153 } 1154 1155 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1156 unsigned int bank) 1157 { 1158 struct device *dev = this_cpu_read(mce_device); 1159 struct threshold_bank *b = NULL; 1160 const char *name = get_name(cpu, bank, NULL); 1161 int err = 0; 1162 1163 if (!dev) 1164 return -ENODEV; 1165 1166 b = kzalloc_obj(struct threshold_bank); 1167 if (!b) { 1168 err = -ENOMEM; 1169 goto out; 1170 } 1171 1172 /* Associate the bank with the per-CPU MCE device */ 1173 b->kobj = kobject_create_and_add(name, &dev->kobj); 1174 if (!b->kobj) { 1175 err = -EINVAL; 1176 goto out_free; 1177 } 1178 1179 INIT_LIST_HEAD(&b->miscj); 1180 1181 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 1182 if (err) 1183 goto out_kobj; 1184 1185 bp[bank] = b; 1186 return 0; 1187 1188 out_kobj: 1189 kobject_put(b->kobj); 1190 out_free: 1191 kfree(b); 1192 out: 1193 return err; 1194 } 1195 1196 static void threshold_block_release(struct kobject *kobj) 1197 { 1198 kfree(to_block(kobj)); 1199 } 1200 1201 static void threshold_remove_bank(struct threshold_bank *bank) 1202 { 1203 struct threshold_block *pos, *tmp; 1204 1205 list_for_each_entry_safe(pos, tmp, &bank->miscj, miscj) { 1206 list_del(&pos->miscj); 1207 kobject_put(&pos->kobj); 1208 } 1209 1210 kobject_put(bank->kobj); 1211 kfree(bank); 1212 } 1213 1214 static void __threshold_remove_device(struct threshold_bank **bp) 1215 { 1216 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1217 1218 for (bank = 0; bank < numbanks; bank++) { 1219 if (!bp[bank]) 1220 continue; 1221 1222 threshold_remove_bank(bp[bank]); 1223 bp[bank] = NULL; 1224 } 1225 kfree(bp); 1226 } 1227 1228 void mce_threshold_remove_device(unsigned int cpu) 1229 { 1230 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1231 1232 if (!bp) 1233 return; 1234 1235 /* 1236 * Clear the pointer before cleaning up, so that the interrupt won't 1237 * touch anything of this. 1238 */ 1239 this_cpu_write(threshold_banks, NULL); 1240 1241 __threshold_remove_device(bp); 1242 return; 1243 } 1244 1245 /** 1246 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1247 * @cpu: The plugged in CPU 1248 * 1249 * Create directories and files for all valid threshold banks. 1250 * 1251 * This is invoked from the CPU hotplug callback which was installed in 1252 * mcheck_init_device(). The invocation happens in context of the hotplug 1253 * thread running on @cpu. The callback is invoked on all CPUs which are 1254 * online when the callback is installed or during a real hotplug event. 1255 */ 1256 void mce_threshold_create_device(unsigned int cpu) 1257 { 1258 unsigned int numbanks, bank; 1259 struct threshold_bank **bp; 1260 1261 if (!mce_flags.amd_threshold) 1262 return; 1263 1264 bp = this_cpu_read(threshold_banks); 1265 if (bp) 1266 return; 1267 1268 numbanks = this_cpu_read(mce_num_banks); 1269 bp = kzalloc_objs(*bp, numbanks); 1270 if (!bp) 1271 return; 1272 1273 for (bank = 0; bank < numbanks; ++bank) { 1274 if (!(this_cpu_read(bank_map) & BIT_ULL(bank))) 1275 continue; 1276 if (threshold_create_bank(bp, cpu, bank)) { 1277 __threshold_remove_device(bp); 1278 return; 1279 } 1280 } 1281 this_cpu_write(threshold_banks, bp); 1282 1283 if (thresholding_irq_en) 1284 mce_threshold_vector = amd_threshold_interrupt; 1285 return; 1286 } 1287