1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 */ 8 #include <linux/interrupt.h> 9 #include <linux/notifier.h> 10 #include <linux/kobject.h> 11 #include <linux/percpu.h> 12 #include <linux/errno.h> 13 #include <linux/sched.h> 14 #include <linux/sysfs.h> 15 #include <linux/slab.h> 16 #include <linux/init.h> 17 #include <linux/cpu.h> 18 #include <linux/smp.h> 19 #include <linux/string.h> 20 21 #include <asm/traps.h> 22 #include <asm/apic.h> 23 #include <asm/mce.h> 24 #include <asm/msr.h> 25 #include <asm/trace/irq_vectors.h> 26 27 #include "internal.h" 28 29 #define NR_BLOCKS 5 30 #define THRESHOLD_MAX 0xFFF 31 #define INT_TYPE_APIC 0x00020000 32 #define MASK_VALID_HI 0x80000000 33 #define MASK_CNTP_HI 0x40000000 34 #define MASK_LOCKED_HI 0x20000000 35 #define MASK_LVTOFF_HI 0x00F00000 36 #define MASK_COUNT_EN_HI 0x00080000 37 #define MASK_INT_TYPE_HI 0x00060000 38 #define MASK_OVERFLOW_HI 0x00010000 39 #define MASK_ERR_COUNT_HI 0x00000FFF 40 #define MASK_BLKPTR_LO 0xFF000000 41 #define MCG_XBLK_ADDR 0xC0000400 42 43 /* Deferred error settings */ 44 #define MSR_CU_DEF_ERR 0xC0000410 45 #define MASK_DEF_LVTOFF 0x000000F0 46 #define MASK_DEF_INT_TYPE 0x00000006 47 #define DEF_LVT_OFF 0x2 48 #define DEF_INT_TYPE_APIC 0x2 49 50 /* Scalable MCA: */ 51 52 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 53 #define SMCA_THR_LVT_OFF 0xF000 54 55 static bool thresholding_irq_en; 56 57 static const char * const th_names[] = { 58 "load_store", 59 "insn_fetch", 60 "combined_unit", 61 "decode_unit", 62 "northbridge", 63 "execution_unit", 64 }; 65 66 static const char * const smca_umc_block_names[] = { 67 "dram_ecc", 68 "misc_umc" 69 }; 70 71 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) 72 73 struct smca_hwid { 74 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ 75 u32 hwid_mcatype; /* (hwid,mcatype) tuple */ 76 }; 77 78 struct smca_bank { 79 const struct smca_hwid *hwid; 80 u32 id; /* Value of MCA_IPID[InstanceId]. */ 81 u8 sysfs_id; /* Value used for sysfs name. */ 82 }; 83 84 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); 85 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); 86 87 static const char * const smca_names[] = { 88 [SMCA_LS ... SMCA_LS_V2] = "load_store", 89 [SMCA_IF] = "insn_fetch", 90 [SMCA_L2_CACHE] = "l2_cache", 91 [SMCA_DE] = "decode_unit", 92 [SMCA_RESERVED] = "reserved", 93 [SMCA_EX] = "execution_unit", 94 [SMCA_FP] = "floating_point", 95 [SMCA_L3_CACHE] = "l3_cache", 96 [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", 97 [SMCA_PIE] = "pie", 98 99 /* UMC v2 is separate because both of them can exist in a single system. */ 100 [SMCA_UMC] = "umc", 101 [SMCA_UMC_V2] = "umc_v2", 102 [SMCA_MA_LLC] = "ma_llc", 103 [SMCA_PB] = "param_block", 104 [SMCA_PSP ... SMCA_PSP_V2] = "psp", 105 [SMCA_SMU ... SMCA_SMU_V2] = "smu", 106 [SMCA_MP5] = "mp5", 107 [SMCA_MPDMA] = "mpdma", 108 [SMCA_NBIO] = "nbio", 109 [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", 110 [SMCA_XGMI_PCS] = "xgmi_pcs", 111 [SMCA_NBIF] = "nbif", 112 [SMCA_SHUB] = "shub", 113 [SMCA_SATA] = "sata", 114 [SMCA_USB] = "usb", 115 [SMCA_USR_DP] = "usr_dp", 116 [SMCA_USR_CP] = "usr_cp", 117 [SMCA_GMI_PCS] = "gmi_pcs", 118 [SMCA_XGMI_PHY] = "xgmi_phy", 119 [SMCA_WAFL_PHY] = "wafl_phy", 120 [SMCA_GMI_PHY] = "gmi_phy", 121 }; 122 123 static const char *smca_get_name(enum smca_bank_types t) 124 { 125 if (t >= N_SMCA_BANK_TYPES) 126 return NULL; 127 128 return smca_names[t]; 129 } 130 131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) 132 { 133 struct smca_bank *b; 134 135 if (bank >= MAX_NR_BANKS) 136 return N_SMCA_BANK_TYPES; 137 138 b = &per_cpu(smca_banks, cpu)[bank]; 139 if (!b->hwid) 140 return N_SMCA_BANK_TYPES; 141 142 return b->hwid->bank_type; 143 } 144 EXPORT_SYMBOL_GPL(smca_get_bank_type); 145 146 static const struct smca_hwid smca_hwid_mcatypes[] = { 147 /* { bank_type, hwid_mcatype } */ 148 149 /* Reserved type */ 150 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 151 152 /* ZN Core (HWID=0xB0) MCA types */ 153 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 154 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 155 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 156 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 157 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 158 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 159 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 160 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 161 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 162 163 /* Data Fabric MCA types */ 164 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 165 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 166 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 167 { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, 168 169 /* Unified Memory Controller MCA type */ 170 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 171 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 172 173 /* Parameter Block MCA type */ 174 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 175 176 /* Platform Security Processor MCA type */ 177 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 178 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 179 180 /* System Management Unit MCA type */ 181 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 182 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 183 184 /* Microprocessor 5 Unit MCA type */ 185 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 186 187 /* MPDMA MCA type */ 188 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 189 190 /* Northbridge IO Unit MCA type */ 191 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 192 193 /* PCI Express Unit MCA type */ 194 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 195 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 196 197 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 198 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 199 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 200 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 201 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 202 { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, 203 { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, 204 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 205 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 206 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 207 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 208 }; 209 210 /* 211 * In SMCA enabled processors, we can have multiple banks for a given IP type. 212 * So to define a unique name for each bank, we use a temp c-string to append 213 * the MCA_IPID[InstanceId] to type's name in get_name(). 214 * 215 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 216 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 217 */ 218 #define MAX_MCATYPE_NAME_LEN 30 219 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 220 221 struct threshold_block { 222 /* This block's number within its bank. */ 223 unsigned int block; 224 /* MCA bank number that contains this block. */ 225 unsigned int bank; 226 /* CPU which controls this block's MCA bank. */ 227 unsigned int cpu; 228 /* MCA_MISC MSR address for this block. */ 229 u32 address; 230 /* Enable/Disable APIC interrupt. */ 231 bool interrupt_enable; 232 /* Bank can generate an interrupt. */ 233 bool interrupt_capable; 234 /* Value upon which threshold interrupt is generated. */ 235 u16 threshold_limit; 236 /* sysfs object */ 237 struct kobject kobj; 238 /* List of threshold blocks within this block's MCA bank. */ 239 struct list_head miscj; 240 }; 241 242 struct threshold_bank { 243 struct kobject *kobj; 244 struct threshold_block *blocks; 245 }; 246 247 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 248 249 /* 250 * A list of the banks enabled on each logical CPU. Controls which respective 251 * descriptors to initialize later in mce_threshold_create_device(). 252 */ 253 static DEFINE_PER_CPU(u64, bank_map); 254 255 /* Map of banks that have more than MCA_MISC0 available. */ 256 static DEFINE_PER_CPU(u64, smca_misc_banks_map); 257 258 static void amd_threshold_interrupt(void); 259 static void amd_deferred_error_interrupt(void); 260 261 static void default_deferred_error_interrupt(void) 262 { 263 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 264 } 265 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 266 267 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 268 { 269 u32 low, high; 270 271 /* 272 * For SMCA enabled processors, BLKPTR field of the first MISC register 273 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 274 */ 275 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 276 return; 277 278 if (!(low & MCI_CONFIG_MCAX)) 279 return; 280 281 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 282 return; 283 284 if (low & MASK_BLKPTR_LO) 285 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); 286 287 } 288 289 static void smca_configure(unsigned int bank, unsigned int cpu) 290 { 291 u8 *bank_counts = this_cpu_ptr(smca_bank_counts); 292 const struct smca_hwid *s_hwid; 293 unsigned int i, hwid_mcatype; 294 u32 high, low; 295 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 296 297 /* Set appropriate bits in MCA_CONFIG */ 298 if (!rdmsr_safe(smca_config, &low, &high)) { 299 /* 300 * OS is required to set the MCAX bit to acknowledge that it is 301 * now using the new MSR ranges and new registers under each 302 * bank. It also means that the OS will configure deferred 303 * errors in the new MCx_CONFIG register. If the bit is not set, 304 * uncorrectable errors will cause a system panic. 305 * 306 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 307 */ 308 high |= BIT(0); 309 310 /* 311 * SMCA sets the Deferred Error Interrupt type per bank. 312 * 313 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 314 * if the DeferredIntType bit field is available. 315 * 316 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 317 * high portion of the MSR). OS should set this to 0x1 to enable 318 * APIC based interrupt. First, check that no interrupt has been 319 * set. 320 */ 321 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 322 high |= BIT(5); 323 324 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); 325 326 wrmsr(smca_config, low, high); 327 } 328 329 smca_set_misc_banks_map(bank, cpu); 330 331 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 332 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 333 return; 334 } 335 336 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 337 (high & MCI_IPID_MCATYPE) >> 16); 338 339 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 340 s_hwid = &smca_hwid_mcatypes[i]; 341 342 if (hwid_mcatype == s_hwid->hwid_mcatype) { 343 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; 344 this_cpu_ptr(smca_banks)[bank].id = low; 345 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; 346 break; 347 } 348 } 349 } 350 351 struct thresh_restart { 352 struct threshold_block *b; 353 int set_lvt_off; 354 int lvt_off; 355 u16 old_limit; 356 }; 357 358 static const char *bank4_names(const struct threshold_block *b) 359 { 360 switch (b->address) { 361 /* MSR4_MISC0 */ 362 case 0x00000413: 363 return "dram"; 364 365 case 0xc0000408: 366 return "ht_links"; 367 368 case 0xc0000409: 369 return "l3_cache"; 370 371 default: 372 WARN(1, "Funny MSR: 0x%08x\n", b->address); 373 return ""; 374 } 375 }; 376 377 378 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 379 { 380 /* 381 * bank 4 supports APIC LVT interrupts implicitly since forever. 382 */ 383 if (bank == 4) 384 return true; 385 386 /* 387 * IntP: interrupt present; if this bit is set, the thresholding 388 * bank can generate APIC LVT interrupts 389 */ 390 return msr_high_bits & BIT(28); 391 } 392 393 static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 394 { 395 int msr = (hi & MASK_LVTOFF_HI) >> 20; 396 397 if (apic < 0) { 398 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 399 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 400 b->bank, b->block, b->address, hi, lo); 401 return false; 402 } 403 404 if (apic != msr) { 405 /* 406 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 407 * the BIOS provides the value. The original field where LVT offset 408 * was set is reserved. Return early here: 409 */ 410 if (mce_flags.smca) 411 return false; 412 413 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 414 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 415 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 416 return false; 417 } 418 419 return true; 420 }; 421 422 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 423 static void threshold_restart_bank(void *_tr) 424 { 425 struct thresh_restart *tr = _tr; 426 u32 hi, lo; 427 428 /* sysfs write might race against an offline operation */ 429 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) 430 return; 431 432 rdmsr(tr->b->address, lo, hi); 433 434 /* 435 * Reset error count and overflow bit. 436 * This is done during init or after handling an interrupt. 437 */ 438 if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) { 439 hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI); 440 hi |= THRESHOLD_MAX - tr->b->threshold_limit; 441 } else if (tr->old_limit) { /* change limit w/o reset */ 442 int new_count = (hi & THRESHOLD_MAX) + 443 (tr->old_limit - tr->b->threshold_limit); 444 445 hi = (hi & ~MASK_ERR_COUNT_HI) | 446 (new_count & THRESHOLD_MAX); 447 } 448 449 /* clear IntType */ 450 hi &= ~MASK_INT_TYPE_HI; 451 452 if (!tr->b->interrupt_capable) 453 goto done; 454 455 if (tr->set_lvt_off) { 456 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 457 /* set new lvt offset */ 458 hi &= ~MASK_LVTOFF_HI; 459 hi |= tr->lvt_off << 20; 460 } 461 } 462 463 if (tr->b->interrupt_enable) 464 hi |= INT_TYPE_APIC; 465 466 done: 467 468 hi |= MASK_COUNT_EN_HI; 469 wrmsr(tr->b->address, lo, hi); 470 } 471 472 static void mce_threshold_block_init(struct threshold_block *b, int offset) 473 { 474 struct thresh_restart tr = { 475 .b = b, 476 .set_lvt_off = 1, 477 .lvt_off = offset, 478 }; 479 480 b->threshold_limit = THRESHOLD_MAX; 481 threshold_restart_bank(&tr); 482 }; 483 484 static int setup_APIC_mce_threshold(int reserved, int new) 485 { 486 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 487 APIC_EILVT_MSG_FIX, 0)) 488 return new; 489 490 return reserved; 491 } 492 493 static int setup_APIC_deferred_error(int reserved, int new) 494 { 495 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 496 APIC_EILVT_MSG_FIX, 0)) 497 return new; 498 499 return reserved; 500 } 501 502 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 503 { 504 u32 low = 0, high = 0; 505 int def_offset = -1, def_new; 506 507 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 508 return; 509 510 def_new = (low & MASK_DEF_LVTOFF) >> 4; 511 if (!(low & MASK_DEF_LVTOFF)) { 512 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 513 def_new = DEF_LVT_OFF; 514 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 515 } 516 517 def_offset = setup_APIC_deferred_error(def_offset, def_new); 518 if ((def_offset == def_new) && 519 (deferred_error_int_vector != amd_deferred_error_interrupt)) 520 deferred_error_int_vector = amd_deferred_error_interrupt; 521 522 if (!mce_flags.smca) 523 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 524 525 wrmsr(MSR_CU_DEF_ERR, low, high); 526 } 527 528 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 529 unsigned int cpu) 530 { 531 if (!block) 532 return MSR_AMD64_SMCA_MCx_MISC(bank); 533 534 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank))) 535 return 0; 536 537 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 538 } 539 540 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 541 unsigned int bank, unsigned int block, 542 unsigned int cpu) 543 { 544 u32 addr = 0, offset = 0; 545 546 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 547 return addr; 548 549 if (mce_flags.smca) 550 return smca_get_block_address(bank, block, cpu); 551 552 /* Fall back to method we used for older processors: */ 553 switch (block) { 554 case 0: 555 addr = mca_msr_reg(bank, MCA_MISC); 556 break; 557 case 1: 558 offset = ((low & MASK_BLKPTR_LO) >> 21); 559 if (offset) 560 addr = MCG_XBLK_ADDR + offset; 561 break; 562 default: 563 addr = ++current_addr; 564 } 565 return addr; 566 } 567 568 static int 569 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 570 int offset, u32 misc_high) 571 { 572 unsigned int cpu = smp_processor_id(); 573 u32 smca_low, smca_high; 574 struct threshold_block b; 575 int new; 576 577 if (!block) 578 per_cpu(bank_map, cpu) |= BIT_ULL(bank); 579 580 memset(&b, 0, sizeof(b)); 581 b.cpu = cpu; 582 b.bank = bank; 583 b.block = block; 584 b.address = addr; 585 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 586 587 if (!b.interrupt_capable) 588 goto done; 589 590 b.interrupt_enable = 1; 591 592 if (!mce_flags.smca) { 593 new = (misc_high & MASK_LVTOFF_HI) >> 20; 594 goto set_offset; 595 } 596 597 /* Gather LVT offset for thresholding: */ 598 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 599 goto out; 600 601 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 602 603 set_offset: 604 offset = setup_APIC_mce_threshold(offset, new); 605 if (offset == new) 606 thresholding_irq_en = true; 607 608 done: 609 mce_threshold_block_init(&b, offset); 610 611 out: 612 return offset; 613 } 614 615 bool amd_filter_mce(struct mce *m) 616 { 617 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); 618 struct cpuinfo_x86 *c = &boot_cpu_data; 619 620 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 621 if (c->x86 == 0x17 && 622 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 623 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 624 return true; 625 626 /* NB GART TLB error reporting is disabled by default. */ 627 if (c->x86 < 0x17) { 628 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 629 return true; 630 } 631 632 return false; 633 } 634 635 /* 636 * Turn off thresholding banks for the following conditions: 637 * - MC4_MISC thresholding is not supported on Family 0x15. 638 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 639 * Models 0x10-0x2F due to Erratum #1114. 640 */ 641 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 642 { 643 int i, num_msrs; 644 u64 hwcr; 645 bool need_toggle; 646 u32 msrs[NR_BLOCKS]; 647 648 if (c->x86 == 0x15 && bank == 4) { 649 msrs[0] = 0x00000413; /* MC4_MISC0 */ 650 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 651 num_msrs = 2; 652 } else if (c->x86 == 0x17 && 653 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 654 655 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) 656 return; 657 658 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 659 num_msrs = 1; 660 } else { 661 return; 662 } 663 664 rdmsrq(MSR_K7_HWCR, hwcr); 665 666 /* McStatusWrEn has to be set */ 667 need_toggle = !(hwcr & BIT(18)); 668 if (need_toggle) 669 wrmsrq(MSR_K7_HWCR, hwcr | BIT(18)); 670 671 /* Clear CntP bit safely */ 672 for (i = 0; i < num_msrs; i++) 673 msr_clear_bit(msrs[i], 62); 674 675 /* restore old settings */ 676 if (need_toggle) 677 wrmsrq(MSR_K7_HWCR, hwcr); 678 } 679 680 /* cpu init entry point, called from mce.c with preempt off */ 681 void mce_amd_feature_init(struct cpuinfo_x86 *c) 682 { 683 unsigned int bank, block, cpu = smp_processor_id(); 684 u32 low = 0, high = 0, address = 0; 685 int offset = -1; 686 687 688 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 689 if (mce_flags.smca) 690 smca_configure(bank, cpu); 691 692 disable_err_thresholding(c, bank); 693 694 for (block = 0; block < NR_BLOCKS; ++block) { 695 address = get_block_address(address, low, high, bank, block, cpu); 696 if (!address) 697 break; 698 699 if (rdmsr_safe(address, &low, &high)) 700 break; 701 702 if (!(high & MASK_VALID_HI)) 703 continue; 704 705 if (!(high & MASK_CNTP_HI) || 706 (high & MASK_LOCKED_HI)) 707 continue; 708 709 offset = prepare_threshold_block(bank, block, address, offset, high); 710 } 711 } 712 713 if (mce_flags.succor) 714 deferred_error_interrupt_enable(c); 715 } 716 717 /* 718 * DRAM ECC errors are reported in the Northbridge (bank 4) with 719 * Extended Error Code 8. 720 */ 721 static bool legacy_mce_is_memory_error(struct mce *m) 722 { 723 return m->bank == 4 && XEC(m->status, 0x1f) == 8; 724 } 725 726 /* 727 * DRAM ECC errors are reported in Unified Memory Controllers with 728 * Extended Error Code 0. 729 */ 730 static bool smca_mce_is_memory_error(struct mce *m) 731 { 732 enum smca_bank_types bank_type; 733 734 if (XEC(m->status, 0x3f)) 735 return false; 736 737 bank_type = smca_get_bank_type(m->extcpu, m->bank); 738 739 return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2; 740 } 741 742 bool amd_mce_is_memory_error(struct mce *m) 743 { 744 if (mce_flags.smca) 745 return smca_mce_is_memory_error(m); 746 else 747 return legacy_mce_is_memory_error(m); 748 } 749 750 /* 751 * AMD systems do not have an explicit indicator that the value in MCA_ADDR is 752 * a system physical address. Therefore, individual cases need to be detected. 753 * Future cases and checks will be added as needed. 754 * 755 * 1) General case 756 * a) Assume address is not usable. 757 * 2) Poison errors 758 * a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy 759 * northbridge (bank 4). 760 * b) Refers to poison consumption in the core. Does not include "no action", 761 * "action optional", or "deferred" error severities. 762 * c) Will include a usable address so that immediate action can be taken. 763 * 3) Northbridge DRAM ECC errors 764 * a) Reported in legacy bank 4 with extended error code (XEC) 8. 765 * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore, 766 * this bit should not be checked. 767 * 768 * NOTE: SMCA UMC memory errors fall into case #1. 769 */ 770 bool amd_mce_usable_address(struct mce *m) 771 { 772 /* Check special northbridge case 3) first. */ 773 if (!mce_flags.smca) { 774 if (legacy_mce_is_memory_error(m)) 775 return true; 776 else if (m->bank == 4) 777 return false; 778 } 779 780 /* Check poison bit for all other bank types. */ 781 if (m->status & MCI_STATUS_POISON) 782 return true; 783 784 /* Assume address is not usable for all others. */ 785 return false; 786 } 787 788 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 789 { 790 struct mce_hw_err err; 791 struct mce *m = &err.m; 792 793 mce_prep_record(&err); 794 795 m->status = status; 796 m->misc = misc; 797 m->bank = bank; 798 m->tsc = rdtsc(); 799 800 if (m->status & MCI_STATUS_ADDRV) { 801 m->addr = addr; 802 803 smca_extract_err_addr(m); 804 } 805 806 if (mce_flags.smca) { 807 rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); 808 809 if (m->status & MCI_STATUS_SYNDV) { 810 rdmsrq(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); 811 rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); 812 rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); 813 } 814 } 815 816 mce_log(&err); 817 } 818 819 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 820 { 821 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 822 inc_irq_stat(irq_deferred_error_count); 823 deferred_error_int_vector(); 824 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 825 apic_eoi(); 826 } 827 828 /* 829 * Returns true if the logged error is deferred. False, otherwise. 830 */ 831 static inline bool 832 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 833 { 834 u64 status, addr = 0; 835 836 rdmsrq(msr_stat, status); 837 if (!(status & MCI_STATUS_VAL)) 838 return false; 839 840 if (status & MCI_STATUS_ADDRV) 841 rdmsrq(msr_addr, addr); 842 843 __log_error(bank, status, addr, misc); 844 845 wrmsrq(msr_stat, 0); 846 847 return status & MCI_STATUS_DEFERRED; 848 } 849 850 static bool _log_error_deferred(unsigned int bank, u32 misc) 851 { 852 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), 853 mca_msr_reg(bank, MCA_ADDR), misc)) 854 return false; 855 856 /* 857 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. 858 * Return true here to avoid accessing these registers. 859 */ 860 if (!mce_flags.smca) 861 return true; 862 863 /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ 864 wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 865 return true; 866 } 867 868 /* 869 * We have three scenarios for checking for Deferred errors: 870 * 871 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 872 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 873 * clear MCA_DESTAT. 874 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 875 * log it. 876 */ 877 static void log_error_deferred(unsigned int bank) 878 { 879 if (_log_error_deferred(bank, 0)) 880 return; 881 882 /* 883 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 884 * for a valid error. 885 */ 886 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 887 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 888 } 889 890 /* APIC interrupt handler for deferred errors */ 891 static void amd_deferred_error_interrupt(void) 892 { 893 unsigned int bank; 894 895 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 896 log_error_deferred(bank); 897 } 898 899 static void log_error_thresholding(unsigned int bank, u64 misc) 900 { 901 _log_error_deferred(bank, misc); 902 } 903 904 static void log_and_reset_block(struct threshold_block *block) 905 { 906 struct thresh_restart tr; 907 u32 low = 0, high = 0; 908 909 if (!block) 910 return; 911 912 if (rdmsr_safe(block->address, &low, &high)) 913 return; 914 915 if (!(high & MASK_OVERFLOW_HI)) 916 return; 917 918 /* Log the MCE which caused the threshold event. */ 919 log_error_thresholding(block->bank, ((u64)high << 32) | low); 920 921 /* Reset threshold block after logging error. */ 922 memset(&tr, 0, sizeof(tr)); 923 tr.b = block; 924 threshold_restart_bank(&tr); 925 } 926 927 /* 928 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 929 * goes off when error_count reaches threshold_limit. 930 */ 931 static void amd_threshold_interrupt(void) 932 { 933 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 934 struct threshold_bank **bp = this_cpu_read(threshold_banks); 935 unsigned int bank, cpu = smp_processor_id(); 936 937 /* 938 * Validate that the threshold bank has been initialized already. The 939 * handler is installed at boot time, but on a hotplug event the 940 * interrupt might fire before the data has been initialized. 941 */ 942 if (!bp) 943 return; 944 945 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 946 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) 947 continue; 948 949 first_block = bp[bank]->blocks; 950 if (!first_block) 951 continue; 952 953 /* 954 * The first block is also the head of the list. Check it first 955 * before iterating over the rest. 956 */ 957 log_and_reset_block(first_block); 958 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 959 log_and_reset_block(block); 960 } 961 } 962 963 /* 964 * Sysfs Interface 965 */ 966 967 struct threshold_attr { 968 struct attribute attr; 969 ssize_t (*show) (struct threshold_block *, char *); 970 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 971 }; 972 973 #define SHOW_FIELDS(name) \ 974 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 975 { \ 976 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 977 } 978 SHOW_FIELDS(interrupt_enable) 979 SHOW_FIELDS(threshold_limit) 980 981 static ssize_t 982 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 983 { 984 struct thresh_restart tr; 985 unsigned long new; 986 987 if (!b->interrupt_capable) 988 return -EINVAL; 989 990 if (kstrtoul(buf, 0, &new) < 0) 991 return -EINVAL; 992 993 b->interrupt_enable = !!new; 994 995 memset(&tr, 0, sizeof(tr)); 996 tr.b = b; 997 998 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 999 return -ENODEV; 1000 1001 return size; 1002 } 1003 1004 static ssize_t 1005 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 1006 { 1007 struct thresh_restart tr; 1008 unsigned long new; 1009 1010 if (kstrtoul(buf, 0, &new) < 0) 1011 return -EINVAL; 1012 1013 if (new > THRESHOLD_MAX) 1014 new = THRESHOLD_MAX; 1015 if (new < 1) 1016 new = 1; 1017 1018 memset(&tr, 0, sizeof(tr)); 1019 tr.old_limit = b->threshold_limit; 1020 b->threshold_limit = new; 1021 tr.b = b; 1022 1023 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1024 return -ENODEV; 1025 1026 return size; 1027 } 1028 1029 static ssize_t show_error_count(struct threshold_block *b, char *buf) 1030 { 1031 u32 lo, hi; 1032 1033 /* CPU might be offline by now */ 1034 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 1035 return -ENODEV; 1036 1037 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 1038 (THRESHOLD_MAX - b->threshold_limit))); 1039 } 1040 1041 static struct threshold_attr error_count = { 1042 .attr = {.name = __stringify(error_count), .mode = 0444 }, 1043 .show = show_error_count, 1044 }; 1045 1046 #define RW_ATTR(val) \ 1047 static struct threshold_attr val = { \ 1048 .attr = {.name = __stringify(val), .mode = 0644 }, \ 1049 .show = show_## val, \ 1050 .store = store_## val, \ 1051 }; 1052 1053 RW_ATTR(interrupt_enable); 1054 RW_ATTR(threshold_limit); 1055 1056 static struct attribute *default_attrs[] = { 1057 &threshold_limit.attr, 1058 &error_count.attr, 1059 NULL, /* possibly interrupt_enable if supported, see below */ 1060 NULL, 1061 }; 1062 ATTRIBUTE_GROUPS(default); 1063 1064 #define to_block(k) container_of(k, struct threshold_block, kobj) 1065 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1066 1067 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1068 { 1069 struct threshold_block *b = to_block(kobj); 1070 struct threshold_attr *a = to_attr(attr); 1071 ssize_t ret; 1072 1073 ret = a->show ? a->show(b, buf) : -EIO; 1074 1075 return ret; 1076 } 1077 1078 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1079 const char *buf, size_t count) 1080 { 1081 struct threshold_block *b = to_block(kobj); 1082 struct threshold_attr *a = to_attr(attr); 1083 ssize_t ret; 1084 1085 ret = a->store ? a->store(b, buf, count) : -EIO; 1086 1087 return ret; 1088 } 1089 1090 static const struct sysfs_ops threshold_ops = { 1091 .show = show, 1092 .store = store, 1093 }; 1094 1095 static void threshold_block_release(struct kobject *kobj); 1096 1097 static const struct kobj_type threshold_ktype = { 1098 .sysfs_ops = &threshold_ops, 1099 .default_groups = default_groups, 1100 .release = threshold_block_release, 1101 }; 1102 1103 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) 1104 { 1105 enum smca_bank_types bank_type; 1106 1107 if (!mce_flags.smca) { 1108 if (b && bank == 4) 1109 return bank4_names(b); 1110 1111 return th_names[bank]; 1112 } 1113 1114 bank_type = smca_get_bank_type(cpu, bank); 1115 1116 if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) { 1117 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1118 return smca_umc_block_names[b->block]; 1119 } 1120 1121 if (b && b->block) { 1122 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_block_%u", b->block); 1123 return buf_mcatype; 1124 } 1125 1126 if (bank_type >= N_SMCA_BANK_TYPES) { 1127 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_bank_%u", bank); 1128 return buf_mcatype; 1129 } 1130 1131 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) 1132 return smca_get_name(bank_type); 1133 1134 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1135 "%s_%u", smca_get_name(bank_type), 1136 per_cpu(smca_banks, cpu)[bank].sysfs_id); 1137 return buf_mcatype; 1138 } 1139 1140 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1141 unsigned int bank, unsigned int block, 1142 u32 address) 1143 { 1144 struct threshold_block *b = NULL; 1145 u32 low, high; 1146 int err; 1147 1148 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1149 return 0; 1150 1151 if (rdmsr_safe(address, &low, &high)) 1152 return 0; 1153 1154 if (!(high & MASK_VALID_HI)) { 1155 if (block) 1156 goto recurse; 1157 else 1158 return 0; 1159 } 1160 1161 if (!(high & MASK_CNTP_HI) || 1162 (high & MASK_LOCKED_HI)) 1163 goto recurse; 1164 1165 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1166 if (!b) 1167 return -ENOMEM; 1168 1169 b->block = block; 1170 b->bank = bank; 1171 b->cpu = cpu; 1172 b->address = address; 1173 b->interrupt_enable = 0; 1174 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1175 b->threshold_limit = THRESHOLD_MAX; 1176 1177 if (b->interrupt_capable) { 1178 default_attrs[2] = &interrupt_enable.attr; 1179 b->interrupt_enable = 1; 1180 } else { 1181 default_attrs[2] = NULL; 1182 } 1183 1184 INIT_LIST_HEAD(&b->miscj); 1185 1186 /* This is safe as @tb is not visible yet */ 1187 if (tb->blocks) 1188 list_add(&b->miscj, &tb->blocks->miscj); 1189 else 1190 tb->blocks = b; 1191 1192 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); 1193 if (err) 1194 goto out_free; 1195 recurse: 1196 address = get_block_address(address, low, high, bank, ++block, cpu); 1197 if (!address) 1198 return 0; 1199 1200 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1201 if (err) 1202 goto out_free; 1203 1204 if (b) 1205 kobject_uevent(&b->kobj, KOBJ_ADD); 1206 1207 return 0; 1208 1209 out_free: 1210 if (b) { 1211 list_del(&b->miscj); 1212 kobject_put(&b->kobj); 1213 } 1214 return err; 1215 } 1216 1217 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1218 unsigned int bank) 1219 { 1220 struct device *dev = this_cpu_read(mce_device); 1221 struct threshold_bank *b = NULL; 1222 const char *name = get_name(cpu, bank, NULL); 1223 int err = 0; 1224 1225 if (!dev) 1226 return -ENODEV; 1227 1228 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1229 if (!b) { 1230 err = -ENOMEM; 1231 goto out; 1232 } 1233 1234 /* Associate the bank with the per-CPU MCE device */ 1235 b->kobj = kobject_create_and_add(name, &dev->kobj); 1236 if (!b->kobj) { 1237 err = -EINVAL; 1238 goto out_free; 1239 } 1240 1241 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 1242 if (err) 1243 goto out_kobj; 1244 1245 bp[bank] = b; 1246 return 0; 1247 1248 out_kobj: 1249 kobject_put(b->kobj); 1250 out_free: 1251 kfree(b); 1252 out: 1253 return err; 1254 } 1255 1256 static void threshold_block_release(struct kobject *kobj) 1257 { 1258 kfree(to_block(kobj)); 1259 } 1260 1261 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1262 { 1263 struct threshold_block *pos, *tmp; 1264 1265 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1266 list_del(&pos->miscj); 1267 kobject_put(&pos->kobj); 1268 } 1269 1270 kobject_put(&bank->blocks->kobj); 1271 } 1272 1273 static void threshold_remove_bank(struct threshold_bank *bank) 1274 { 1275 if (!bank->blocks) 1276 goto out_free; 1277 1278 deallocate_threshold_blocks(bank); 1279 1280 out_free: 1281 kobject_put(bank->kobj); 1282 kfree(bank); 1283 } 1284 1285 static void __threshold_remove_device(struct threshold_bank **bp) 1286 { 1287 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1288 1289 for (bank = 0; bank < numbanks; bank++) { 1290 if (!bp[bank]) 1291 continue; 1292 1293 threshold_remove_bank(bp[bank]); 1294 bp[bank] = NULL; 1295 } 1296 kfree(bp); 1297 } 1298 1299 int mce_threshold_remove_device(unsigned int cpu) 1300 { 1301 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1302 1303 if (!bp) 1304 return 0; 1305 1306 /* 1307 * Clear the pointer before cleaning up, so that the interrupt won't 1308 * touch anything of this. 1309 */ 1310 this_cpu_write(threshold_banks, NULL); 1311 1312 __threshold_remove_device(bp); 1313 return 0; 1314 } 1315 1316 /** 1317 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1318 * @cpu: The plugged in CPU 1319 * 1320 * Create directories and files for all valid threshold banks. 1321 * 1322 * This is invoked from the CPU hotplug callback which was installed in 1323 * mcheck_init_device(). The invocation happens in context of the hotplug 1324 * thread running on @cpu. The callback is invoked on all CPUs which are 1325 * online when the callback is installed or during a real hotplug event. 1326 */ 1327 int mce_threshold_create_device(unsigned int cpu) 1328 { 1329 unsigned int numbanks, bank; 1330 struct threshold_bank **bp; 1331 int err; 1332 1333 if (!mce_flags.amd_threshold) 1334 return 0; 1335 1336 bp = this_cpu_read(threshold_banks); 1337 if (bp) 1338 return 0; 1339 1340 numbanks = this_cpu_read(mce_num_banks); 1341 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1342 if (!bp) 1343 return -ENOMEM; 1344 1345 for (bank = 0; bank < numbanks; ++bank) { 1346 if (!(this_cpu_read(bank_map) & BIT_ULL(bank))) 1347 continue; 1348 err = threshold_create_bank(bp, cpu, bank); 1349 if (err) { 1350 __threshold_remove_device(bp); 1351 return err; 1352 } 1353 } 1354 this_cpu_write(threshold_banks, bp); 1355 1356 if (thresholding_irq_en) 1357 mce_threshold_vector = amd_threshold_interrupt; 1358 return 0; 1359 } 1360