1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 struct smca_bank_name { 75 const char *name; /* Short name for sysfs */ 76 const char *long_name; /* Long name for pretty-printing */ 77 }; 78 79 static struct smca_bank_name smca_names[] = { 80 [SMCA_LS] = { "load_store", "Load Store Unit" }, 81 [SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 82 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 83 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 84 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 85 [SMCA_RESERVED] = { "reserved", "Reserved" }, 86 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 87 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 88 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 89 [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, 90 [SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 91 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 92 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 93 [SMCA_PB] = { "param_block", "Parameter Block" }, 94 [SMCA_PSP] = { "psp", "Platform Security Processor" }, 95 [SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 96 [SMCA_SMU] = { "smu", "System Management Unit" }, 97 [SMCA_SMU_V2] = { "smu", "System Management Unit" }, 98 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 99 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 100 [SMCA_PCIE] = { "pcie", "PCI Express Unit" }, 101 }; 102 103 static const char *smca_get_name(enum smca_bank_types t) 104 { 105 if (t >= N_SMCA_BANK_TYPES) 106 return NULL; 107 108 return smca_names[t].name; 109 } 110 111 const char *smca_get_long_name(enum smca_bank_types t) 112 { 113 if (t >= N_SMCA_BANK_TYPES) 114 return NULL; 115 116 return smca_names[t].long_name; 117 } 118 EXPORT_SYMBOL_GPL(smca_get_long_name); 119 120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) 121 { 122 struct smca_bank *b; 123 124 if (bank >= MAX_NR_BANKS) 125 return N_SMCA_BANK_TYPES; 126 127 b = &smca_banks[bank]; 128 if (!b->hwid) 129 return N_SMCA_BANK_TYPES; 130 131 return b->hwid->bank_type; 132 } 133 134 static struct smca_hwid smca_hwid_mcatypes[] = { 135 /* { bank_type, hwid_mcatype, xec_bitmap } */ 136 137 /* Reserved type */ 138 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, 139 140 /* ZN Core (HWID=0xB0) MCA types */ 141 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF }, 142 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10), 0xFFFFFF }, 143 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, 144 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, 145 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, 146 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 147 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0xFFF }, 148 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, 149 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, 150 151 /* Data Fabric MCA types */ 152 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, 153 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0x1F }, 154 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2), 0x3FFF }, 155 156 /* Unified Memory Controller MCA type */ 157 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0xFF }, 158 159 /* Parameter Block MCA type */ 160 { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, 161 162 /* Platform Security Processor MCA type */ 163 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, 164 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1), 0x3FFFF }, 165 166 /* System Management Unit MCA type */ 167 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, 168 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1), 0x7FF }, 169 170 /* Microprocessor 5 Unit MCA type */ 171 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2), 0x3FF }, 172 173 /* Northbridge IO Unit MCA type */ 174 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0), 0x1F }, 175 176 /* PCI Express Unit MCA type */ 177 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0), 0x1F }, 178 }; 179 180 struct smca_bank smca_banks[MAX_NR_BANKS]; 181 EXPORT_SYMBOL_GPL(smca_banks); 182 183 /* 184 * In SMCA enabled processors, we can have multiple banks for a given IP type. 185 * So to define a unique name for each bank, we use a temp c-string to append 186 * the MCA_IPID[InstanceId] to type's name in get_name(). 187 * 188 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 189 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 190 */ 191 #define MAX_MCATYPE_NAME_LEN 30 192 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 193 194 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 195 196 /* 197 * A list of the banks enabled on each logical CPU. Controls which respective 198 * descriptors to initialize later in mce_threshold_create_device(). 199 */ 200 static DEFINE_PER_CPU(unsigned int, bank_map); 201 202 /* Map of banks that have more than MCA_MISC0 available. */ 203 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 204 205 static void amd_threshold_interrupt(void); 206 static void amd_deferred_error_interrupt(void); 207 208 static void default_deferred_error_interrupt(void) 209 { 210 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 211 } 212 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 213 214 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 215 { 216 u32 low, high; 217 218 /* 219 * For SMCA enabled processors, BLKPTR field of the first MISC register 220 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 221 */ 222 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 223 return; 224 225 if (!(low & MCI_CONFIG_MCAX)) 226 return; 227 228 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 229 return; 230 231 if (low & MASK_BLKPTR_LO) 232 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 233 234 } 235 236 static void smca_configure(unsigned int bank, unsigned int cpu) 237 { 238 unsigned int i, hwid_mcatype; 239 struct smca_hwid *s_hwid; 240 u32 high, low; 241 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 242 243 /* Set appropriate bits in MCA_CONFIG */ 244 if (!rdmsr_safe(smca_config, &low, &high)) { 245 /* 246 * OS is required to set the MCAX bit to acknowledge that it is 247 * now using the new MSR ranges and new registers under each 248 * bank. It also means that the OS will configure deferred 249 * errors in the new MCx_CONFIG register. If the bit is not set, 250 * uncorrectable errors will cause a system panic. 251 * 252 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 253 */ 254 high |= BIT(0); 255 256 /* 257 * SMCA sets the Deferred Error Interrupt type per bank. 258 * 259 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 260 * if the DeferredIntType bit field is available. 261 * 262 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 263 * high portion of the MSR). OS should set this to 0x1 to enable 264 * APIC based interrupt. First, check that no interrupt has been 265 * set. 266 */ 267 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 268 high |= BIT(5); 269 270 wrmsr(smca_config, low, high); 271 } 272 273 smca_set_misc_banks_map(bank, cpu); 274 275 /* Return early if this bank was already initialized. */ 276 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) 277 return; 278 279 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 280 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 281 return; 282 } 283 284 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 285 (high & MCI_IPID_MCATYPE) >> 16); 286 287 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 288 s_hwid = &smca_hwid_mcatypes[i]; 289 if (hwid_mcatype == s_hwid->hwid_mcatype) { 290 smca_banks[bank].hwid = s_hwid; 291 smca_banks[bank].id = low; 292 smca_banks[bank].sysfs_id = s_hwid->count++; 293 break; 294 } 295 } 296 } 297 298 struct thresh_restart { 299 struct threshold_block *b; 300 int reset; 301 int set_lvt_off; 302 int lvt_off; 303 u16 old_limit; 304 }; 305 306 static inline bool is_shared_bank(int bank) 307 { 308 /* 309 * Scalable MCA provides for only one core to have access to the MSRs of 310 * a shared bank. 311 */ 312 if (mce_flags.smca) 313 return false; 314 315 /* Bank 4 is for northbridge reporting and is thus shared */ 316 return (bank == 4); 317 } 318 319 static const char *bank4_names(const struct threshold_block *b) 320 { 321 switch (b->address) { 322 /* MSR4_MISC0 */ 323 case 0x00000413: 324 return "dram"; 325 326 case 0xc0000408: 327 return "ht_links"; 328 329 case 0xc0000409: 330 return "l3_cache"; 331 332 default: 333 WARN(1, "Funny MSR: 0x%08x\n", b->address); 334 return ""; 335 } 336 }; 337 338 339 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 340 { 341 /* 342 * bank 4 supports APIC LVT interrupts implicitly since forever. 343 */ 344 if (bank == 4) 345 return true; 346 347 /* 348 * IntP: interrupt present; if this bit is set, the thresholding 349 * bank can generate APIC LVT interrupts 350 */ 351 return msr_high_bits & BIT(28); 352 } 353 354 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 355 { 356 int msr = (hi & MASK_LVTOFF_HI) >> 20; 357 358 if (apic < 0) { 359 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 360 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 361 b->bank, b->block, b->address, hi, lo); 362 return 0; 363 } 364 365 if (apic != msr) { 366 /* 367 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 368 * the BIOS provides the value. The original field where LVT offset 369 * was set is reserved. Return early here: 370 */ 371 if (mce_flags.smca) 372 return 0; 373 374 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 375 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 376 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 377 return 0; 378 } 379 380 return 1; 381 }; 382 383 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 384 static void threshold_restart_bank(void *_tr) 385 { 386 struct thresh_restart *tr = _tr; 387 u32 hi, lo; 388 389 rdmsr(tr->b->address, lo, hi); 390 391 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 392 tr->reset = 1; /* limit cannot be lower than err count */ 393 394 if (tr->reset) { /* reset err count and overflow bit */ 395 hi = 396 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 397 (THRESHOLD_MAX - tr->b->threshold_limit); 398 } else if (tr->old_limit) { /* change limit w/o reset */ 399 int new_count = (hi & THRESHOLD_MAX) + 400 (tr->old_limit - tr->b->threshold_limit); 401 402 hi = (hi & ~MASK_ERR_COUNT_HI) | 403 (new_count & THRESHOLD_MAX); 404 } 405 406 /* clear IntType */ 407 hi &= ~MASK_INT_TYPE_HI; 408 409 if (!tr->b->interrupt_capable) 410 goto done; 411 412 if (tr->set_lvt_off) { 413 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 414 /* set new lvt offset */ 415 hi &= ~MASK_LVTOFF_HI; 416 hi |= tr->lvt_off << 20; 417 } 418 } 419 420 if (tr->b->interrupt_enable) 421 hi |= INT_TYPE_APIC; 422 423 done: 424 425 hi |= MASK_COUNT_EN_HI; 426 wrmsr(tr->b->address, lo, hi); 427 } 428 429 static void mce_threshold_block_init(struct threshold_block *b, int offset) 430 { 431 struct thresh_restart tr = { 432 .b = b, 433 .set_lvt_off = 1, 434 .lvt_off = offset, 435 }; 436 437 b->threshold_limit = THRESHOLD_MAX; 438 threshold_restart_bank(&tr); 439 }; 440 441 static int setup_APIC_mce_threshold(int reserved, int new) 442 { 443 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 444 APIC_EILVT_MSG_FIX, 0)) 445 return new; 446 447 return reserved; 448 } 449 450 static int setup_APIC_deferred_error(int reserved, int new) 451 { 452 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 453 APIC_EILVT_MSG_FIX, 0)) 454 return new; 455 456 return reserved; 457 } 458 459 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 460 { 461 u32 low = 0, high = 0; 462 int def_offset = -1, def_new; 463 464 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 465 return; 466 467 def_new = (low & MASK_DEF_LVTOFF) >> 4; 468 if (!(low & MASK_DEF_LVTOFF)) { 469 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 470 def_new = DEF_LVT_OFF; 471 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 472 } 473 474 def_offset = setup_APIC_deferred_error(def_offset, def_new); 475 if ((def_offset == def_new) && 476 (deferred_error_int_vector != amd_deferred_error_interrupt)) 477 deferred_error_int_vector = amd_deferred_error_interrupt; 478 479 if (!mce_flags.smca) 480 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 481 482 wrmsr(MSR_CU_DEF_ERR, low, high); 483 } 484 485 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 486 unsigned int cpu) 487 { 488 if (!block) 489 return MSR_AMD64_SMCA_MCx_MISC(bank); 490 491 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 492 return 0; 493 494 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 495 } 496 497 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 498 unsigned int bank, unsigned int block, 499 unsigned int cpu) 500 { 501 u32 addr = 0, offset = 0; 502 503 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 504 return addr; 505 506 if (mce_flags.smca) 507 return smca_get_block_address(bank, block, cpu); 508 509 /* Fall back to method we used for older processors: */ 510 switch (block) { 511 case 0: 512 addr = msr_ops.misc(bank); 513 break; 514 case 1: 515 offset = ((low & MASK_BLKPTR_LO) >> 21); 516 if (offset) 517 addr = MCG_XBLK_ADDR + offset; 518 break; 519 default: 520 addr = ++current_addr; 521 } 522 return addr; 523 } 524 525 static int 526 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 527 int offset, u32 misc_high) 528 { 529 unsigned int cpu = smp_processor_id(); 530 u32 smca_low, smca_high; 531 struct threshold_block b; 532 int new; 533 534 if (!block) 535 per_cpu(bank_map, cpu) |= (1 << bank); 536 537 memset(&b, 0, sizeof(b)); 538 b.cpu = cpu; 539 b.bank = bank; 540 b.block = block; 541 b.address = addr; 542 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 543 544 if (!b.interrupt_capable) 545 goto done; 546 547 b.interrupt_enable = 1; 548 549 if (!mce_flags.smca) { 550 new = (misc_high & MASK_LVTOFF_HI) >> 20; 551 goto set_offset; 552 } 553 554 /* Gather LVT offset for thresholding: */ 555 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 556 goto out; 557 558 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 559 560 set_offset: 561 offset = setup_APIC_mce_threshold(offset, new); 562 if (offset == new) 563 thresholding_irq_en = true; 564 565 done: 566 mce_threshold_block_init(&b, offset); 567 568 out: 569 return offset; 570 } 571 572 bool amd_filter_mce(struct mce *m) 573 { 574 enum smca_bank_types bank_type = smca_get_bank_type(m->bank); 575 struct cpuinfo_x86 *c = &boot_cpu_data; 576 u8 xec = (m->status >> 16) & 0x3F; 577 578 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 579 if (c->x86 == 0x17 && 580 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 581 bank_type == SMCA_IF && xec == 10) 582 return true; 583 584 return false; 585 } 586 587 /* 588 * Turn off thresholding banks for the following conditions: 589 * - MC4_MISC thresholding is not supported on Family 0x15. 590 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 591 * Models 0x10-0x2F due to Erratum #1114. 592 */ 593 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 594 { 595 int i, num_msrs; 596 u64 hwcr; 597 bool need_toggle; 598 u32 msrs[NR_BLOCKS]; 599 600 if (c->x86 == 0x15 && bank == 4) { 601 msrs[0] = 0x00000413; /* MC4_MISC0 */ 602 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 603 num_msrs = 2; 604 } else if (c->x86 == 0x17 && 605 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 606 607 if (smca_get_bank_type(bank) != SMCA_IF) 608 return; 609 610 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 611 num_msrs = 1; 612 } else { 613 return; 614 } 615 616 rdmsrl(MSR_K7_HWCR, hwcr); 617 618 /* McStatusWrEn has to be set */ 619 need_toggle = !(hwcr & BIT(18)); 620 if (need_toggle) 621 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 622 623 /* Clear CntP bit safely */ 624 for (i = 0; i < num_msrs; i++) 625 msr_clear_bit(msrs[i], 62); 626 627 /* restore old settings */ 628 if (need_toggle) 629 wrmsrl(MSR_K7_HWCR, hwcr); 630 } 631 632 /* cpu init entry point, called from mce.c with preempt off */ 633 void mce_amd_feature_init(struct cpuinfo_x86 *c) 634 { 635 unsigned int bank, block, cpu = smp_processor_id(); 636 u32 low = 0, high = 0, address = 0; 637 int offset = -1; 638 639 640 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 641 if (mce_flags.smca) 642 smca_configure(bank, cpu); 643 644 disable_err_thresholding(c, bank); 645 646 for (block = 0; block < NR_BLOCKS; ++block) { 647 address = get_block_address(address, low, high, bank, block, cpu); 648 if (!address) 649 break; 650 651 if (rdmsr_safe(address, &low, &high)) 652 break; 653 654 if (!(high & MASK_VALID_HI)) 655 continue; 656 657 if (!(high & MASK_CNTP_HI) || 658 (high & MASK_LOCKED_HI)) 659 continue; 660 661 offset = prepare_threshold_block(bank, block, address, offset, high); 662 } 663 } 664 665 if (mce_flags.succor) 666 deferred_error_interrupt_enable(c); 667 } 668 669 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) 670 { 671 u64 dram_base_addr, dram_limit_addr, dram_hole_base; 672 /* We start from the normalized address */ 673 u64 ret_addr = norm_addr; 674 675 u32 tmp; 676 677 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; 678 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; 679 u8 intlv_addr_sel, intlv_addr_bit; 680 u8 num_intlv_bits, hashed_bit; 681 u8 lgcy_mmio_hole_en, base = 0; 682 u8 cs_mask, cs_id = 0; 683 bool hash_enabled = false; 684 685 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ 686 if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) 687 goto out_err; 688 689 /* Remove HiAddrOffset from normalized address, if enabled: */ 690 if (tmp & BIT(0)) { 691 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; 692 693 if (norm_addr >= hi_addr_offset) { 694 ret_addr -= hi_addr_offset; 695 base = 1; 696 } 697 } 698 699 /* Read D18F0x110 (DramBaseAddress). */ 700 if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) 701 goto out_err; 702 703 /* Check if address range is valid. */ 704 if (!(tmp & BIT(0))) { 705 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", 706 __func__, tmp); 707 goto out_err; 708 } 709 710 lgcy_mmio_hole_en = tmp & BIT(1); 711 intlv_num_chan = (tmp >> 4) & 0xF; 712 intlv_addr_sel = (tmp >> 8) & 0x7; 713 dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; 714 715 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ 716 if (intlv_addr_sel > 3) { 717 pr_err("%s: Invalid interleave address select %d.\n", 718 __func__, intlv_addr_sel); 719 goto out_err; 720 } 721 722 /* Read D18F0x114 (DramLimitAddress). */ 723 if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) 724 goto out_err; 725 726 intlv_num_sockets = (tmp >> 8) & 0x1; 727 intlv_num_dies = (tmp >> 10) & 0x3; 728 dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 729 730 intlv_addr_bit = intlv_addr_sel + 8; 731 732 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ 733 switch (intlv_num_chan) { 734 case 0: intlv_num_chan = 0; break; 735 case 1: intlv_num_chan = 1; break; 736 case 3: intlv_num_chan = 2; break; 737 case 5: intlv_num_chan = 3; break; 738 case 7: intlv_num_chan = 4; break; 739 740 case 8: intlv_num_chan = 1; 741 hash_enabled = true; 742 break; 743 default: 744 pr_err("%s: Invalid number of interleaved channels %d.\n", 745 __func__, intlv_num_chan); 746 goto out_err; 747 } 748 749 num_intlv_bits = intlv_num_chan; 750 751 if (intlv_num_dies > 2) { 752 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", 753 __func__, intlv_num_dies); 754 goto out_err; 755 } 756 757 num_intlv_bits += intlv_num_dies; 758 759 /* Add a bit if sockets are interleaved. */ 760 num_intlv_bits += intlv_num_sockets; 761 762 /* Assert num_intlv_bits <= 4 */ 763 if (num_intlv_bits > 4) { 764 pr_err("%s: Invalid interleave bits %d.\n", 765 __func__, num_intlv_bits); 766 goto out_err; 767 } 768 769 if (num_intlv_bits > 0) { 770 u64 temp_addr_x, temp_addr_i, temp_addr_y; 771 u8 die_id_bit, sock_id_bit, cs_fabric_id; 772 773 /* 774 * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. 775 * This is the fabric id for this coherent slave. Use 776 * umc/channel# as instance id of the coherent slave 777 * for FICAA. 778 */ 779 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) 780 goto out_err; 781 782 cs_fabric_id = (tmp >> 8) & 0xFF; 783 die_id_bit = 0; 784 785 /* If interleaved over more than 1 channel: */ 786 if (intlv_num_chan) { 787 die_id_bit = intlv_num_chan; 788 cs_mask = (1 << die_id_bit) - 1; 789 cs_id = cs_fabric_id & cs_mask; 790 } 791 792 sock_id_bit = die_id_bit; 793 794 /* Read D18F1x208 (SystemFabricIdMask). */ 795 if (intlv_num_dies || intlv_num_sockets) 796 if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) 797 goto out_err; 798 799 /* If interleaved over more than 1 die. */ 800 if (intlv_num_dies) { 801 sock_id_bit = die_id_bit + intlv_num_dies; 802 die_id_shift = (tmp >> 24) & 0xF; 803 die_id_mask = (tmp >> 8) & 0xFF; 804 805 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; 806 } 807 808 /* If interleaved over more than 1 socket. */ 809 if (intlv_num_sockets) { 810 socket_id_shift = (tmp >> 28) & 0xF; 811 socket_id_mask = (tmp >> 16) & 0xFF; 812 813 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; 814 } 815 816 /* 817 * The pre-interleaved address consists of XXXXXXIIIYYYYY 818 * where III is the ID for this CS, and XXXXXXYYYYY are the 819 * address bits from the post-interleaved address. 820 * "num_intlv_bits" has been calculated to tell us how many "I" 821 * bits there are. "intlv_addr_bit" tells us how many "Y" bits 822 * there are (where "I" starts). 823 */ 824 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); 825 temp_addr_i = (cs_id << intlv_addr_bit); 826 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; 827 ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; 828 } 829 830 /* Add dram base address */ 831 ret_addr += dram_base_addr; 832 833 /* If legacy MMIO hole enabled */ 834 if (lgcy_mmio_hole_en) { 835 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) 836 goto out_err; 837 838 dram_hole_base = tmp & GENMASK(31, 24); 839 if (ret_addr >= dram_hole_base) 840 ret_addr += (BIT_ULL(32) - dram_hole_base); 841 } 842 843 if (hash_enabled) { 844 /* Save some parentheses and grab ls-bit at the end. */ 845 hashed_bit = (ret_addr >> 12) ^ 846 (ret_addr >> 18) ^ 847 (ret_addr >> 21) ^ 848 (ret_addr >> 30) ^ 849 cs_id; 850 851 hashed_bit &= BIT(0); 852 853 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) 854 ret_addr ^= BIT(intlv_addr_bit); 855 } 856 857 /* Is calculated system address is above DRAM limit address? */ 858 if (ret_addr > dram_limit_addr) 859 goto out_err; 860 861 *sys_addr = ret_addr; 862 return 0; 863 864 out_err: 865 return -EINVAL; 866 } 867 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); 868 869 bool amd_mce_is_memory_error(struct mce *m) 870 { 871 /* ErrCodeExt[20:16] */ 872 u8 xec = (m->status >> 16) & 0x1f; 873 874 if (mce_flags.smca) 875 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 876 877 return m->bank == 4 && xec == 0x8; 878 } 879 880 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 881 { 882 struct mce m; 883 884 mce_setup(&m); 885 886 m.status = status; 887 m.misc = misc; 888 m.bank = bank; 889 m.tsc = rdtsc(); 890 891 if (m.status & MCI_STATUS_ADDRV) { 892 m.addr = addr; 893 894 /* 895 * Extract [55:<lsb>] where lsb is the least significant 896 * *valid* bit of the address bits. 897 */ 898 if (mce_flags.smca) { 899 u8 lsb = (m.addr >> 56) & 0x3f; 900 901 m.addr &= GENMASK_ULL(55, lsb); 902 } 903 } 904 905 if (mce_flags.smca) { 906 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 907 908 if (m.status & MCI_STATUS_SYNDV) 909 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 910 } 911 912 mce_log(&m); 913 } 914 915 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs) 916 { 917 entering_irq(); 918 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 919 inc_irq_stat(irq_deferred_error_count); 920 deferred_error_int_vector(); 921 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 922 exiting_ack_irq(); 923 } 924 925 /* 926 * Returns true if the logged error is deferred. False, otherwise. 927 */ 928 static inline bool 929 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 930 { 931 u64 status, addr = 0; 932 933 rdmsrl(msr_stat, status); 934 if (!(status & MCI_STATUS_VAL)) 935 return false; 936 937 if (status & MCI_STATUS_ADDRV) 938 rdmsrl(msr_addr, addr); 939 940 __log_error(bank, status, addr, misc); 941 942 wrmsrl(msr_stat, 0); 943 944 return status & MCI_STATUS_DEFERRED; 945 } 946 947 /* 948 * We have three scenarios for checking for Deferred errors: 949 * 950 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 951 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 952 * clear MCA_DESTAT. 953 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 954 * log it. 955 */ 956 static void log_error_deferred(unsigned int bank) 957 { 958 bool defrd; 959 960 defrd = _log_error_bank(bank, msr_ops.status(bank), 961 msr_ops.addr(bank), 0); 962 963 if (!mce_flags.smca) 964 return; 965 966 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 967 if (defrd) { 968 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 969 return; 970 } 971 972 /* 973 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 974 * for a valid error. 975 */ 976 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 977 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 978 } 979 980 /* APIC interrupt handler for deferred errors */ 981 static void amd_deferred_error_interrupt(void) 982 { 983 unsigned int bank; 984 985 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 986 log_error_deferred(bank); 987 } 988 989 static void log_error_thresholding(unsigned int bank, u64 misc) 990 { 991 _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); 992 } 993 994 static void log_and_reset_block(struct threshold_block *block) 995 { 996 struct thresh_restart tr; 997 u32 low = 0, high = 0; 998 999 if (!block) 1000 return; 1001 1002 if (rdmsr_safe(block->address, &low, &high)) 1003 return; 1004 1005 if (!(high & MASK_OVERFLOW_HI)) 1006 return; 1007 1008 /* Log the MCE which caused the threshold event. */ 1009 log_error_thresholding(block->bank, ((u64)high << 32) | low); 1010 1011 /* Reset threshold block after logging error. */ 1012 memset(&tr, 0, sizeof(tr)); 1013 tr.b = block; 1014 threshold_restart_bank(&tr); 1015 } 1016 1017 /* 1018 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 1019 * goes off when error_count reaches threshold_limit. 1020 */ 1021 static void amd_threshold_interrupt(void) 1022 { 1023 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 1024 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1025 unsigned int bank, cpu = smp_processor_id(); 1026 1027 /* 1028 * Validate that the threshold bank has been initialized already. The 1029 * handler is installed at boot time, but on a hotplug event the 1030 * interrupt might fire before the data has been initialized. 1031 */ 1032 if (!bp) 1033 return; 1034 1035 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 1036 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1037 continue; 1038 1039 first_block = bp[bank]->blocks; 1040 if (!first_block) 1041 continue; 1042 1043 /* 1044 * The first block is also the head of the list. Check it first 1045 * before iterating over the rest. 1046 */ 1047 log_and_reset_block(first_block); 1048 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 1049 log_and_reset_block(block); 1050 } 1051 } 1052 1053 /* 1054 * Sysfs Interface 1055 */ 1056 1057 struct threshold_attr { 1058 struct attribute attr; 1059 ssize_t (*show) (struct threshold_block *, char *); 1060 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 1061 }; 1062 1063 #define SHOW_FIELDS(name) \ 1064 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 1065 { \ 1066 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 1067 } 1068 SHOW_FIELDS(interrupt_enable) 1069 SHOW_FIELDS(threshold_limit) 1070 1071 static ssize_t 1072 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 1073 { 1074 struct thresh_restart tr; 1075 unsigned long new; 1076 1077 if (!b->interrupt_capable) 1078 return -EINVAL; 1079 1080 if (kstrtoul(buf, 0, &new) < 0) 1081 return -EINVAL; 1082 1083 b->interrupt_enable = !!new; 1084 1085 memset(&tr, 0, sizeof(tr)); 1086 tr.b = b; 1087 1088 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); 1089 1090 return size; 1091 } 1092 1093 static ssize_t 1094 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 1095 { 1096 struct thresh_restart tr; 1097 unsigned long new; 1098 1099 if (kstrtoul(buf, 0, &new) < 0) 1100 return -EINVAL; 1101 1102 if (new > THRESHOLD_MAX) 1103 new = THRESHOLD_MAX; 1104 if (new < 1) 1105 new = 1; 1106 1107 memset(&tr, 0, sizeof(tr)); 1108 tr.old_limit = b->threshold_limit; 1109 b->threshold_limit = new; 1110 tr.b = b; 1111 1112 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); 1113 1114 return size; 1115 } 1116 1117 static ssize_t show_error_count(struct threshold_block *b, char *buf) 1118 { 1119 u32 lo, hi; 1120 1121 rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); 1122 1123 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 1124 (THRESHOLD_MAX - b->threshold_limit))); 1125 } 1126 1127 static struct threshold_attr error_count = { 1128 .attr = {.name = __stringify(error_count), .mode = 0444 }, 1129 .show = show_error_count, 1130 }; 1131 1132 #define RW_ATTR(val) \ 1133 static struct threshold_attr val = { \ 1134 .attr = {.name = __stringify(val), .mode = 0644 }, \ 1135 .show = show_## val, \ 1136 .store = store_## val, \ 1137 }; 1138 1139 RW_ATTR(interrupt_enable); 1140 RW_ATTR(threshold_limit); 1141 1142 static struct attribute *default_attrs[] = { 1143 &threshold_limit.attr, 1144 &error_count.attr, 1145 NULL, /* possibly interrupt_enable if supported, see below */ 1146 NULL, 1147 }; 1148 1149 #define to_block(k) container_of(k, struct threshold_block, kobj) 1150 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1151 1152 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1153 { 1154 struct threshold_block *b = to_block(kobj); 1155 struct threshold_attr *a = to_attr(attr); 1156 ssize_t ret; 1157 1158 ret = a->show ? a->show(b, buf) : -EIO; 1159 1160 return ret; 1161 } 1162 1163 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1164 const char *buf, size_t count) 1165 { 1166 struct threshold_block *b = to_block(kobj); 1167 struct threshold_attr *a = to_attr(attr); 1168 ssize_t ret; 1169 1170 ret = a->store ? a->store(b, buf, count) : -EIO; 1171 1172 return ret; 1173 } 1174 1175 static const struct sysfs_ops threshold_ops = { 1176 .show = show, 1177 .store = store, 1178 }; 1179 1180 static void threshold_block_release(struct kobject *kobj); 1181 1182 static struct kobj_type threshold_ktype = { 1183 .sysfs_ops = &threshold_ops, 1184 .default_attrs = default_attrs, 1185 .release = threshold_block_release, 1186 }; 1187 1188 static const char *get_name(unsigned int bank, struct threshold_block *b) 1189 { 1190 enum smca_bank_types bank_type; 1191 1192 if (!mce_flags.smca) { 1193 if (b && bank == 4) 1194 return bank4_names(b); 1195 1196 return th_names[bank]; 1197 } 1198 1199 bank_type = smca_get_bank_type(bank); 1200 if (bank_type >= N_SMCA_BANK_TYPES) 1201 return NULL; 1202 1203 if (b && bank_type == SMCA_UMC) { 1204 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1205 return smca_umc_block_names[b->block]; 1206 return NULL; 1207 } 1208 1209 if (smca_banks[bank].hwid->count == 1) 1210 return smca_get_name(bank_type); 1211 1212 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1213 "%s_%x", smca_get_name(bank_type), 1214 smca_banks[bank].sysfs_id); 1215 return buf_mcatype; 1216 } 1217 1218 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1219 unsigned int bank, unsigned int block, 1220 u32 address) 1221 { 1222 struct threshold_block *b = NULL; 1223 u32 low, high; 1224 int err; 1225 1226 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 1227 return 0; 1228 1229 if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) 1230 return 0; 1231 1232 if (!(high & MASK_VALID_HI)) { 1233 if (block) 1234 goto recurse; 1235 else 1236 return 0; 1237 } 1238 1239 if (!(high & MASK_CNTP_HI) || 1240 (high & MASK_LOCKED_HI)) 1241 goto recurse; 1242 1243 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1244 if (!b) 1245 return -ENOMEM; 1246 1247 b->block = block; 1248 b->bank = bank; 1249 b->cpu = cpu; 1250 b->address = address; 1251 b->interrupt_enable = 0; 1252 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1253 b->threshold_limit = THRESHOLD_MAX; 1254 1255 if (b->interrupt_capable) { 1256 threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 1257 b->interrupt_enable = 1; 1258 } else { 1259 threshold_ktype.default_attrs[2] = NULL; 1260 } 1261 1262 INIT_LIST_HEAD(&b->miscj); 1263 1264 /* This is safe as @tb is not visible yet */ 1265 if (tb->blocks) 1266 list_add(&b->miscj, &tb->blocks->miscj); 1267 else 1268 tb->blocks = b; 1269 1270 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); 1271 if (err) 1272 goto out_free; 1273 recurse: 1274 address = get_block_address(address, low, high, bank, ++block, cpu); 1275 if (!address) 1276 return 0; 1277 1278 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1279 if (err) 1280 goto out_free; 1281 1282 if (b) 1283 kobject_uevent(&b->kobj, KOBJ_ADD); 1284 1285 return 0; 1286 1287 out_free: 1288 if (b) { 1289 list_del(&b->miscj); 1290 kobject_put(&b->kobj); 1291 } 1292 return err; 1293 } 1294 1295 static int __threshold_add_blocks(struct threshold_bank *b) 1296 { 1297 struct list_head *head = &b->blocks->miscj; 1298 struct threshold_block *pos = NULL; 1299 struct threshold_block *tmp = NULL; 1300 int err = 0; 1301 1302 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1303 if (err) 1304 return err; 1305 1306 list_for_each_entry_safe(pos, tmp, head, miscj) { 1307 1308 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1309 if (err) { 1310 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1311 kobject_del(&pos->kobj); 1312 1313 return err; 1314 } 1315 } 1316 return err; 1317 } 1318 1319 static int threshold_create_bank(unsigned int cpu, unsigned int bank) 1320 { 1321 struct device *dev = per_cpu(mce_device, cpu); 1322 struct amd_northbridge *nb = NULL; 1323 struct threshold_bank *b = NULL; 1324 const char *name = get_name(bank, NULL); 1325 int err = 0; 1326 1327 if (!dev) 1328 return -ENODEV; 1329 1330 if (is_shared_bank(bank)) { 1331 nb = node_to_amd_nb(amd_get_nb_id(cpu)); 1332 1333 /* threshold descriptor already initialized on this node? */ 1334 if (nb && nb->bank4) { 1335 /* yes, use it */ 1336 b = nb->bank4; 1337 err = kobject_add(b->kobj, &dev->kobj, name); 1338 if (err) 1339 goto out; 1340 1341 per_cpu(threshold_banks, cpu)[bank] = b; 1342 refcount_inc(&b->cpus); 1343 1344 err = __threshold_add_blocks(b); 1345 1346 goto out; 1347 } 1348 } 1349 1350 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1351 if (!b) { 1352 err = -ENOMEM; 1353 goto out; 1354 } 1355 1356 /* Associate the bank with the per-CPU MCE device */ 1357 b->kobj = kobject_create_and_add(name, &dev->kobj); 1358 if (!b->kobj) { 1359 err = -EINVAL; 1360 goto out_free; 1361 } 1362 1363 if (is_shared_bank(bank)) { 1364 refcount_set(&b->cpus, 1); 1365 1366 /* nb is already initialized, see above */ 1367 if (nb) { 1368 WARN_ON(nb->bank4); 1369 nb->bank4 = b; 1370 } 1371 } 1372 1373 err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank)); 1374 if (err) 1375 goto out_kobj; 1376 1377 per_cpu(threshold_banks, cpu)[bank] = b; 1378 1379 return 0; 1380 1381 out_kobj: 1382 kobject_put(b->kobj); 1383 out_free: 1384 kfree(b); 1385 out: 1386 return err; 1387 } 1388 1389 static void threshold_block_release(struct kobject *kobj) 1390 { 1391 kfree(to_block(kobj)); 1392 } 1393 1394 static void deallocate_threshold_block(unsigned int cpu, unsigned int bank) 1395 { 1396 struct threshold_block *pos = NULL; 1397 struct threshold_block *tmp = NULL; 1398 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; 1399 1400 if (!head) 1401 return; 1402 1403 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { 1404 list_del(&pos->miscj); 1405 kobject_put(&pos->kobj); 1406 } 1407 1408 kobject_put(&head->blocks->kobj); 1409 } 1410 1411 static void __threshold_remove_blocks(struct threshold_bank *b) 1412 { 1413 struct threshold_block *pos = NULL; 1414 struct threshold_block *tmp = NULL; 1415 1416 kobject_del(b->kobj); 1417 1418 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1419 kobject_del(&pos->kobj); 1420 } 1421 1422 static void threshold_remove_bank(unsigned int cpu, int bank) 1423 { 1424 struct amd_northbridge *nb; 1425 struct threshold_bank *b; 1426 1427 b = per_cpu(threshold_banks, cpu)[bank]; 1428 if (!b) 1429 return; 1430 1431 if (!b->blocks) 1432 goto free_out; 1433 1434 if (is_shared_bank(bank)) { 1435 if (!refcount_dec_and_test(&b->cpus)) { 1436 __threshold_remove_blocks(b); 1437 per_cpu(threshold_banks, cpu)[bank] = NULL; 1438 return; 1439 } else { 1440 /* 1441 * the last CPU on this node using the shared bank is 1442 * going away, remove that bank now. 1443 */ 1444 nb = node_to_amd_nb(amd_get_nb_id(cpu)); 1445 nb->bank4 = NULL; 1446 } 1447 } 1448 1449 deallocate_threshold_block(cpu, bank); 1450 1451 free_out: 1452 kobject_del(b->kobj); 1453 kobject_put(b->kobj); 1454 kfree(b); 1455 per_cpu(threshold_banks, cpu)[bank] = NULL; 1456 } 1457 1458 int mce_threshold_remove_device(unsigned int cpu) 1459 { 1460 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1461 unsigned int bank; 1462 1463 if (!bp) 1464 return 0; 1465 1466 for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) { 1467 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1468 continue; 1469 threshold_remove_bank(cpu, bank); 1470 } 1471 /* Clear the pointer before freeing the memory */ 1472 this_cpu_write(threshold_banks, NULL); 1473 kfree(bp); 1474 return 0; 1475 } 1476 1477 /** 1478 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1479 * @cpu: The plugged in CPU 1480 * 1481 * Create directories and files for all valid threshold banks. 1482 * 1483 * This is invoked from the CPU hotplug callback which was installed in 1484 * mcheck_init_device(). The invocation happens in context of the hotplug 1485 * thread running on @cpu. The callback is invoked on all CPUs which are 1486 * online when the callback is installed or during a real hotplug event. 1487 */ 1488 int mce_threshold_create_device(unsigned int cpu) 1489 { 1490 unsigned int bank; 1491 struct threshold_bank **bp; 1492 int err; 1493 1494 if (!mce_flags.amd_threshold) 1495 return 0; 1496 1497 bp = per_cpu(threshold_banks, cpu); 1498 if (bp) 1499 return 0; 1500 1501 bp = kcalloc(per_cpu(mce_num_banks, cpu), sizeof(struct threshold_bank *), 1502 GFP_KERNEL); 1503 if (!bp) 1504 return -ENOMEM; 1505 1506 per_cpu(threshold_banks, cpu) = bp; 1507 1508 for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) { 1509 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1510 continue; 1511 err = threshold_create_bank(cpu, bank); 1512 if (err) 1513 goto out_err; 1514 } 1515 1516 if (thresholding_irq_en) 1517 mce_threshold_vector = amd_threshold_interrupt; 1518 1519 return 0; 1520 out_err: 1521 mce_threshold_remove_device(cpu); 1522 return err; 1523 } 1524