1 #include <linux/init.h> 2 #include <linux/kernel.h> 3 4 #include <linux/string.h> 5 #include <linux/bitops.h> 6 #include <linux/smp.h> 7 #include <linux/sched.h> 8 #include <linux/thread_info.h> 9 #include <linux/module.h> 10 11 #include <asm/processor.h> 12 #include <asm/pgtable.h> 13 #include <asm/msr.h> 14 #include <asm/uaccess.h> 15 #include <asm/ds.h> 16 #include <asm/bugs.h> 17 18 #ifdef CONFIG_X86_64 19 #include <asm/topology.h> 20 #include <asm/numa_64.h> 21 #endif 22 23 #include "cpu.h" 24 25 #ifdef CONFIG_X86_LOCAL_APIC 26 #include <asm/mpspec.h> 27 #include <asm/apic.h> 28 #endif 29 30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 31 { 32 /* Unmask CPUID levels if masked: */ 33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 34 u64 misc_enable; 35 36 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 37 38 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { 39 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; 40 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 41 c->cpuid_level = cpuid_eax(0); 42 } 43 } 44 45 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 46 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 47 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 48 49 #ifdef CONFIG_X86_64 50 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 51 #else 52 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 53 if (c->x86 == 15 && c->x86_cache_alignment == 64) 54 c->x86_cache_alignment = 128; 55 #endif 56 57 /* 58 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 59 * with P/T states and does not stop in deep C-states. 60 * 61 * It is also reliable across cores and sockets. (but not across 62 * cabinets - we turn it off in that case explicitly.) 63 */ 64 if (c->x86_power & (1 << 8)) { 65 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 66 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 67 set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE); 68 sched_clock_stable = 1; 69 } 70 71 /* 72 * There is a known erratum on Pentium III and Core Solo 73 * and Core Duo CPUs. 74 * " Page with PAT set to WC while associated MTRR is UC 75 * may consolidate to UC " 76 * Because of this erratum, it is better to stick with 77 * setting WC in MTRR rather than using PAT on these CPUs. 78 * 79 * Enable PAT WC only on P4, Core 2 or later CPUs. 80 */ 81 if (c->x86 == 6 && c->x86_model < 15) 82 clear_cpu_cap(c, X86_FEATURE_PAT); 83 } 84 85 #ifdef CONFIG_X86_32 86 /* 87 * Early probe support logic for ppro memory erratum #50 88 * 89 * This is called before we do cpu ident work 90 */ 91 92 int __cpuinit ppro_with_ram_bug(void) 93 { 94 /* Uses data from early_cpu_detect now */ 95 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 96 boot_cpu_data.x86 == 6 && 97 boot_cpu_data.x86_model == 1 && 98 boot_cpu_data.x86_mask < 8) { 99 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 100 return 1; 101 } 102 return 0; 103 } 104 105 #ifdef CONFIG_X86_F00F_BUG 106 static void __cpuinit trap_init_f00f_bug(void) 107 { 108 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); 109 110 /* 111 * Update the IDT descriptor and reload the IDT so that 112 * it uses the read-only mapped virtual address. 113 */ 114 idt_descr.address = fix_to_virt(FIX_F00F_IDT); 115 load_idt(&idt_descr); 116 } 117 #endif 118 119 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 120 { 121 unsigned long lo, hi; 122 123 #ifdef CONFIG_X86_F00F_BUG 124 /* 125 * All current models of Pentium and Pentium with MMX technology CPUs 126 * have the F0 0F bug, which lets nonprivileged users lock up the system. 127 * Note that the workaround only should be initialized once... 128 */ 129 c->f00f_bug = 0; 130 if (!paravirt_enabled() && c->x86 == 5) { 131 static int f00f_workaround_enabled; 132 133 c->f00f_bug = 1; 134 if (!f00f_workaround_enabled) { 135 trap_init_f00f_bug(); 136 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 137 f00f_workaround_enabled = 1; 138 } 139 } 140 #endif 141 142 /* 143 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 144 * model 3 mask 3 145 */ 146 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 147 clear_cpu_cap(c, X86_FEATURE_SEP); 148 149 /* 150 * P4 Xeon errata 037 workaround. 151 * Hardware prefetcher may cause stale data to be loaded into the cache. 152 */ 153 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 154 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); 155 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) { 156 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); 157 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); 158 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE; 159 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); 160 } 161 } 162 163 /* 164 * See if we have a good local APIC by checking for buggy Pentia, 165 * i.e. all B steppings and the C2 stepping of P54C when using their 166 * integrated APIC (see 11AP erratum in "Pentium Processor 167 * Specification Update"). 168 */ 169 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && 170 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 171 set_cpu_cap(c, X86_FEATURE_11AP); 172 173 174 #ifdef CONFIG_X86_INTEL_USERCOPY 175 /* 176 * Set up the preferred alignment for movsl bulk memory moves 177 */ 178 switch (c->x86) { 179 case 4: /* 486: untested */ 180 break; 181 case 5: /* Old Pentia: untested */ 182 break; 183 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 184 movsl_mask.mask = 7; 185 break; 186 case 15: /* P4 is OK down to 8-byte alignment */ 187 movsl_mask.mask = 7; 188 break; 189 } 190 #endif 191 192 #ifdef CONFIG_X86_NUMAQ 193 numaq_tsc_disable(); 194 #endif 195 } 196 #else 197 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 198 { 199 } 200 #endif 201 202 static void __cpuinit srat_detect_node(void) 203 { 204 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 205 unsigned node; 206 int cpu = smp_processor_id(); 207 int apicid = hard_smp_processor_id(); 208 209 /* Don't do the funky fallback heuristics the AMD version employs 210 for now. */ 211 node = apicid_to_node[apicid]; 212 if (node == NUMA_NO_NODE || !node_online(node)) 213 node = first_node(node_online_map); 214 numa_set_node(cpu, node); 215 216 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); 217 #endif 218 } 219 220 /* 221 * find out the number of processor cores on the die 222 */ 223 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) 224 { 225 unsigned int eax, ebx, ecx, edx; 226 227 if (c->cpuid_level < 4) 228 return 1; 229 230 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 231 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 232 if (eax & 0x1f) 233 return ((eax >> 26) + 1); 234 else 235 return 1; 236 } 237 238 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c) 239 { 240 /* Intel VMX MSR indicated features */ 241 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 242 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 243 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 244 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 245 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 246 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 247 248 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 249 250 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 251 clear_cpu_cap(c, X86_FEATURE_VNMI); 252 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 253 clear_cpu_cap(c, X86_FEATURE_EPT); 254 clear_cpu_cap(c, X86_FEATURE_VPID); 255 256 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 257 msr_ctl = vmx_msr_high | vmx_msr_low; 258 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 259 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 260 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 261 set_cpu_cap(c, X86_FEATURE_VNMI); 262 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 263 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 264 vmx_msr_low, vmx_msr_high); 265 msr_ctl2 = vmx_msr_high | vmx_msr_low; 266 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 267 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 268 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 269 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 270 set_cpu_cap(c, X86_FEATURE_EPT); 271 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 272 set_cpu_cap(c, X86_FEATURE_VPID); 273 } 274 } 275 276 static void __cpuinit init_intel(struct cpuinfo_x86 *c) 277 { 278 unsigned int l2 = 0; 279 280 early_init_intel(c); 281 282 intel_workarounds(c); 283 284 /* 285 * Detect the extended topology information if available. This 286 * will reinitialise the initial_apicid which will be used 287 * in init_intel_cacheinfo() 288 */ 289 detect_extended_topology(c); 290 291 l2 = init_intel_cacheinfo(c); 292 if (c->cpuid_level > 9) { 293 unsigned eax = cpuid_eax(10); 294 /* Check for version and the number of counters */ 295 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 296 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 297 } 298 299 if (cpu_has_xmm2) 300 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 301 if (cpu_has_ds) { 302 unsigned int l1; 303 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 304 if (!(l1 & (1<<11))) 305 set_cpu_cap(c, X86_FEATURE_BTS); 306 if (!(l1 & (1<<12))) 307 set_cpu_cap(c, X86_FEATURE_PEBS); 308 ds_init_intel(c); 309 } 310 311 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush) 312 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR); 313 314 #ifdef CONFIG_X86_64 315 if (c->x86 == 15) 316 c->x86_cache_alignment = c->x86_clflush_size * 2; 317 if (c->x86 == 6) 318 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 319 #else 320 /* 321 * Names for the Pentium II/Celeron processors 322 * detectable only by also checking the cache size. 323 * Dixon is NOT a Celeron. 324 */ 325 if (c->x86 == 6) { 326 char *p = NULL; 327 328 switch (c->x86_model) { 329 case 5: 330 if (c->x86_mask == 0) { 331 if (l2 == 0) 332 p = "Celeron (Covington)"; 333 else if (l2 == 256) 334 p = "Mobile Pentium II (Dixon)"; 335 } 336 break; 337 338 case 6: 339 if (l2 == 128) 340 p = "Celeron (Mendocino)"; 341 else if (c->x86_mask == 0 || c->x86_mask == 5) 342 p = "Celeron-A"; 343 break; 344 345 case 8: 346 if (l2 == 128) 347 p = "Celeron (Coppermine)"; 348 break; 349 } 350 351 if (p) 352 strcpy(c->x86_model_id, p); 353 } 354 355 if (c->x86 == 15) 356 set_cpu_cap(c, X86_FEATURE_P4); 357 if (c->x86 == 6) 358 set_cpu_cap(c, X86_FEATURE_P3); 359 #endif 360 361 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 362 /* 363 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 364 * detection. 365 */ 366 c->x86_max_cores = intel_num_cpu_cores(c); 367 #ifdef CONFIG_X86_32 368 detect_ht(c); 369 #endif 370 } 371 372 /* Work around errata */ 373 srat_detect_node(); 374 375 if (cpu_has(c, X86_FEATURE_VMX)) 376 detect_vmx_virtcap(c); 377 } 378 379 #ifdef CONFIG_X86_32 380 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 381 { 382 /* 383 * Intel PIII Tualatin. This comes in two flavours. 384 * One has 256kb of cache, the other 512. We have no way 385 * to determine which, so we use a boottime override 386 * for the 512kb model, and assume 256 otherwise. 387 */ 388 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 389 size = 256; 390 return size; 391 } 392 #endif 393 394 static struct cpu_dev intel_cpu_dev __cpuinitdata = { 395 .c_vendor = "Intel", 396 .c_ident = { "GenuineIntel" }, 397 #ifdef CONFIG_X86_32 398 .c_models = { 399 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 400 { 401 [0] = "486 DX-25/33", 402 [1] = "486 DX-50", 403 [2] = "486 SX", 404 [3] = "486 DX/2", 405 [4] = "486 SL", 406 [5] = "486 SX/2", 407 [7] = "486 DX/2-WB", 408 [8] = "486 DX/4", 409 [9] = "486 DX/4-WB" 410 } 411 }, 412 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = 413 { 414 [0] = "Pentium 60/66 A-step", 415 [1] = "Pentium 60/66", 416 [2] = "Pentium 75 - 200", 417 [3] = "OverDrive PODP5V83", 418 [4] = "Pentium MMX", 419 [7] = "Mobile Pentium 75 - 200", 420 [8] = "Mobile Pentium MMX" 421 } 422 }, 423 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = 424 { 425 [0] = "Pentium Pro A-step", 426 [1] = "Pentium Pro", 427 [3] = "Pentium II (Klamath)", 428 [4] = "Pentium II (Deschutes)", 429 [5] = "Pentium II (Deschutes)", 430 [6] = "Mobile Pentium II", 431 [7] = "Pentium III (Katmai)", 432 [8] = "Pentium III (Coppermine)", 433 [10] = "Pentium III (Cascades)", 434 [11] = "Pentium III (Tualatin)", 435 } 436 }, 437 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = 438 { 439 [0] = "Pentium 4 (Unknown)", 440 [1] = "Pentium 4 (Willamette)", 441 [2] = "Pentium 4 (Northwood)", 442 [4] = "Pentium 4 (Foster)", 443 [5] = "Pentium 4 (Foster)", 444 } 445 }, 446 }, 447 .c_size_cache = intel_size_cache, 448 #endif 449 .c_early_init = early_init_intel, 450 .c_init = init_intel, 451 .c_x86_vendor = X86_VENDOR_INTEL, 452 }; 453 454 cpu_dev_register(intel_cpu_dev); 455 456