1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/bitops.h> 4 #include <linux/init.h> 5 #include <linux/kernel.h> 6 #include <linux/minmax.h> 7 #include <linux/smp.h> 8 #include <linux/string.h> 9 #include <linux/types.h> 10 11 #ifdef CONFIG_X86_64 12 #include <linux/topology.h> 13 #endif 14 15 #include <asm/bugs.h> 16 #include <asm/cpu_device_id.h> 17 #include <asm/cpufeature.h> 18 #include <asm/cpu.h> 19 #include <asm/cpuid/api.h> 20 #include <asm/hwcap2.h> 21 #include <asm/intel-family.h> 22 #include <asm/microcode.h> 23 #include <asm/msr.h> 24 #include <asm/numa.h> 25 #include <asm/resctrl.h> 26 #include <asm/thermal.h> 27 #include <asm/uaccess.h> 28 29 #include "cpu.h" 30 31 /* 32 * Processors which have self-snooping capability can handle conflicting 33 * memory type across CPUs by snooping its own cache. However, there exists 34 * CPU models in which having conflicting memory types still leads to 35 * unpredictable behavior, machine check errors, or hangs. Clear this 36 * feature to prevent its use on machines with known erratas. 37 */ 38 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) 39 { 40 switch (c->x86_vfm) { 41 case INTEL_CORE_YONAH: 42 case INTEL_CORE2_MEROM: 43 case INTEL_CORE2_MEROM_L: 44 case INTEL_CORE2_PENRYN: 45 case INTEL_CORE2_DUNNINGTON: 46 case INTEL_NEHALEM: 47 case INTEL_NEHALEM_G: 48 case INTEL_NEHALEM_EP: 49 case INTEL_NEHALEM_EX: 50 case INTEL_WESTMERE: 51 case INTEL_WESTMERE_EP: 52 case INTEL_SANDYBRIDGE: 53 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); 54 } 55 } 56 57 static bool ring3mwait_disabled __read_mostly; 58 59 static int __init ring3mwait_disable(char *__unused) 60 { 61 ring3mwait_disabled = true; 62 return 1; 63 } 64 __setup("ring3mwait=disable", ring3mwait_disable); 65 66 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 67 { 68 /* 69 * Ring 3 MONITOR/MWAIT feature cannot be detected without 70 * cpu model and family comparison. 71 */ 72 if (c->x86 != 6) 73 return; 74 switch (c->x86_vfm) { 75 case INTEL_XEON_PHI_KNL: 76 case INTEL_XEON_PHI_KNM: 77 break; 78 default: 79 return; 80 } 81 82 if (ring3mwait_disabled) 83 return; 84 85 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 86 this_cpu_or(msr_misc_features_shadow, 87 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 88 89 if (c == &boot_cpu_data) 90 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 91 } 92 93 /* 94 * Early microcode releases for the Spectre v2 mitigation were broken. 95 * Information taken from; 96 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 97 * - https://kb.vmware.com/s/article/52345 98 * - Microcode revisions observed in the wild 99 * - Release note from 20180108 microcode release 100 */ 101 struct sku_microcode { 102 u32 vfm; 103 u8 stepping; 104 u32 microcode; 105 }; 106 static const struct sku_microcode spectre_bad_microcodes[] = { 107 { INTEL_KABYLAKE, 0x0B, 0x80 }, 108 { INTEL_KABYLAKE, 0x0A, 0x80 }, 109 { INTEL_KABYLAKE, 0x09, 0x80 }, 110 { INTEL_KABYLAKE_L, 0x0A, 0x80 }, 111 { INTEL_KABYLAKE_L, 0x09, 0x80 }, 112 { INTEL_SKYLAKE_X, 0x03, 0x0100013e }, 113 { INTEL_SKYLAKE_X, 0x04, 0x0200003c }, 114 { INTEL_BROADWELL, 0x04, 0x28 }, 115 { INTEL_BROADWELL_G, 0x01, 0x1b }, 116 { INTEL_BROADWELL_D, 0x02, 0x14 }, 117 { INTEL_BROADWELL_D, 0x03, 0x07000011 }, 118 { INTEL_BROADWELL_X, 0x01, 0x0b000025 }, 119 { INTEL_HASWELL_L, 0x01, 0x21 }, 120 { INTEL_HASWELL_G, 0x01, 0x18 }, 121 { INTEL_HASWELL, 0x03, 0x23 }, 122 { INTEL_HASWELL_X, 0x02, 0x3b }, 123 { INTEL_HASWELL_X, 0x04, 0x10 }, 124 { INTEL_IVYBRIDGE_X, 0x04, 0x42a }, 125 /* Observed in the wild */ 126 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b }, 127 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 }, 128 }; 129 130 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 131 { 132 int i; 133 134 /* 135 * We know that the hypervisor lie to us on the microcode version so 136 * we may as well hope that it is running the correct version. 137 */ 138 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 139 return false; 140 141 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 142 if (c->x86_vfm == spectre_bad_microcodes[i].vfm && 143 c->x86_stepping == spectre_bad_microcodes[i].stepping) 144 return (c->microcode <= spectre_bad_microcodes[i].microcode); 145 } 146 return false; 147 } 148 149 #define MSR_IA32_TME_ACTIVATE 0x982 150 151 /* Helpers to access TME_ACTIVATE MSR */ 152 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 153 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 154 155 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 156 157 static void detect_tme_early(struct cpuinfo_x86 *c) 158 { 159 u64 tme_activate; 160 int keyid_bits; 161 162 rdmsrq(MSR_IA32_TME_ACTIVATE, tme_activate); 163 164 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 165 pr_info_once("x86/tme: not enabled by BIOS\n"); 166 clear_cpu_cap(c, X86_FEATURE_TME); 167 return; 168 } 169 pr_info_once("x86/tme: enabled by BIOS\n"); 170 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 171 if (!keyid_bits) 172 return; 173 174 /* 175 * KeyID bits are set by BIOS and can be present regardless 176 * of whether the kernel is using them. They effectively lower 177 * the number of physical address bits. 178 * 179 * Update cpuinfo_x86::x86_phys_bits accordingly. 180 */ 181 c->x86_phys_bits -= keyid_bits; 182 pr_info_once("x86/mktme: BIOS enabled: x86_phys_bits reduced by %d\n", 183 keyid_bits); 184 } 185 186 void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) 187 { 188 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 189 return; 190 191 if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) 192 return; 193 194 /* 195 * The BIOS can have limited CPUID to leaf 2, which breaks feature 196 * enumeration. Unlock it and update the maximum leaf info. 197 */ 198 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) 199 c->cpuid_level = cpuid_eax(0); 200 } 201 202 static void early_init_intel(struct cpuinfo_x86 *c) 203 { 204 u64 misc_enable; 205 206 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 207 c->microcode = intel_get_microcode_revision(); 208 c->intel_platform_id = intel_get_platform_id(); 209 210 /* Now if any of them are set, check the blacklist and clear the lot */ 211 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 212 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 213 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 214 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 215 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 216 setup_clear_cpu_cap(X86_FEATURE_IBRS); 217 setup_clear_cpu_cap(X86_FEATURE_IBPB); 218 setup_clear_cpu_cap(X86_FEATURE_STIBP); 219 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 220 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 221 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 222 setup_clear_cpu_cap(X86_FEATURE_SSBD); 223 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 224 } 225 226 /* 227 * Atom erratum AAE44/AAF40/AAG38/AAH41: 228 * 229 * A race condition between speculative fetches and invalidating 230 * a large page. This is worked around in microcode, but we 231 * need the microcode to have already been loaded... so if it is 232 * not, recommend a BIOS update and disable large pages. 233 */ 234 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && 235 c->microcode < 0x20e) { 236 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 237 clear_cpu_cap(c, X86_FEATURE_PSE); 238 } 239 240 #ifndef CONFIG_X86_64 241 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 242 if (c->x86 == 15 && c->x86_cache_alignment == 64) 243 c->x86_cache_alignment = 128; 244 #endif 245 246 /* CPUID workaround for 0F33/0F34 CPU */ 247 if (c->x86_vfm == INTEL_P4_PRESCOTT && 248 (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 249 c->x86_phys_bits = 36; 250 251 /* 252 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 253 * with P/T states and does not stop in deep C-states. 254 * 255 * It is also reliable across cores and sockets. (but not across 256 * cabinets - we turn it off in that case explicitly.) 257 * 258 * Use a model-specific check for some older CPUs that have invariant 259 * TSC but may not report it architecturally via 8000_0007. 260 */ 261 if (c->x86_power & (1 << 8)) { 262 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 263 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 264 } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) || 265 (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { 266 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 267 } 268 269 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 270 switch (c->x86_vfm) { 271 case INTEL_ATOM_SALTWELL_MID: 272 case INTEL_ATOM_SALTWELL_TABLET: 273 case INTEL_ATOM_SILVERMONT_MID: 274 case INTEL_ATOM_AIRMONT_NP: 275 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 276 break; 277 } 278 279 /* 280 * PAT is broken on early family 6 CPUs, the last of which 281 * is "Yonah" where the erratum is named "AN7": 282 * 283 * Page with PAT (Page Attribute Table) Set to USWC 284 * (Uncacheable Speculative Write Combine) While 285 * Associated MTRR (Memory Type Range Register) Is UC 286 * (Uncacheable) May Consolidate to UC 287 * 288 * Disable PAT and fall back to MTRR on these CPUs. 289 */ 290 if (c->x86_vfm >= INTEL_PENTIUM_PRO && 291 c->x86_vfm <= INTEL_CORE_YONAH) 292 clear_cpu_cap(c, X86_FEATURE_PAT); 293 294 /* 295 * Modern CPUs are generally expected to have a sane fast string 296 * implementation. However, BIOSes typically have a knob to tweak 297 * the architectural MISC_ENABLE.FAST_STRING enable bit. 298 * 299 * Adhere to the preference and program the Linux-defined fast 300 * string flag and enhanced fast string capabilities accordingly. 301 */ 302 if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { 303 rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); 304 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { 305 /* X86_FEATURE_ERMS is set based on CPUID */ 306 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 307 } else { 308 pr_info("Disabled fast string operations\n"); 309 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 310 setup_clear_cpu_cap(X86_FEATURE_ERMS); 311 } 312 } 313 314 /* 315 * Intel Quark Core DevMan_001.pdf section 6.4.11 316 * "The operating system also is required to invalidate (i.e., flush) 317 * the TLB when any changes are made to any of the page table entries. 318 * The operating system must reload CR3 to cause the TLB to be flushed" 319 * 320 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 321 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE 322 * to be modified. 323 */ 324 if (c->x86_vfm == INTEL_QUARK_X1000) { 325 pr_info("Disabling PGE capability bit\n"); 326 setup_clear_cpu_cap(X86_FEATURE_PGE); 327 } 328 329 check_memory_type_self_snoop_errata(c); 330 331 /* 332 * Adjust the number of physical bits early because it affects the 333 * valid bits of the MTRR mask registers. 334 */ 335 if (cpu_has(c, X86_FEATURE_TME)) 336 detect_tme_early(c); 337 } 338 339 static void bsp_init_intel(struct cpuinfo_x86 *c) 340 { 341 resctrl_cpu_detect(c); 342 } 343 344 #ifdef CONFIG_X86_32 345 /* 346 * Early probe support logic for ppro memory erratum #50 347 * 348 * This is called before we do cpu ident work 349 */ 350 351 int ppro_with_ram_bug(void) 352 { 353 /* Uses data from early_cpu_detect now */ 354 if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && 355 boot_cpu_data.x86_stepping < 8) { 356 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 357 return 1; 358 } 359 return 0; 360 } 361 362 static void intel_smp_check(struct cpuinfo_x86 *c) 363 { 364 /* calling is from identify_secondary_cpu() ? */ 365 if (!c->cpu_index) 366 return; 367 368 /* 369 * Mask B, Pentium, but not Pentium MMX 370 */ 371 if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && 372 c->x86_stepping >= 1 && c->x86_stepping <= 4) { 373 /* 374 * Remember we have B step Pentia with bugs 375 */ 376 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 377 "with B stepping processors.\n"); 378 } 379 } 380 381 static int forcepae; 382 static int __init forcepae_setup(char *__unused) 383 { 384 forcepae = 1; 385 return 1; 386 } 387 __setup("forcepae", forcepae_setup); 388 389 static void intel_workarounds(struct cpuinfo_x86 *c) 390 { 391 /* 392 * All models of Pentium and Pentium with MMX technology CPUs 393 * have the F0 0F bug, which lets nonprivileged users lock up the 394 * system. The fault handler always checks for it. 395 * The Quark is also family 5, but does not have the same bug. 396 */ 397 if (IS_ENABLED(CONFIG_X86_F00F_BUG) && 398 (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000)) 399 set_cpu_bug(c, X86_BUG_F00F); 400 401 /* 402 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 403 * model 3 mask 3 404 */ 405 if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || 406 c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) 407 clear_cpu_cap(c, X86_FEATURE_SEP); 408 409 /* 410 * PAE CPUID issue: many Pentium M report no PAE but may have a 411 * functionally usable PAE implementation. 412 * Forcefully enable PAE if kernel parameter "forcepae" is present. 413 */ 414 if (forcepae) { 415 pr_warn("PAE forced!\n"); 416 set_cpu_cap(c, X86_FEATURE_PAE); 417 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 418 } 419 420 /* 421 * P4 Xeon erratum 037 workaround. 422 * Hardware prefetcher may cause stale data to be loaded into the cache. 423 */ 424 if (c->x86_vfm == INTEL_P4_WILLAMETTE && c->x86_stepping == 1) { 425 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 426 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 427 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 428 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 429 } 430 } 431 432 /* 433 * See if we have a good local APIC by checking for buggy Pentia, 434 * i.e. all B steppings and the C2 stepping of P54C when using their 435 * integrated APIC (see 11AP erratum in "Pentium Processor 436 * Specification Update"). 437 */ 438 if (boot_cpu_has(X86_FEATURE_APIC) && c->x86_vfm == INTEL_PENTIUM_75 && 439 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 440 set_cpu_bug(c, X86_BUG_11AP); 441 442 #ifdef CONFIG_X86_INTEL_USERCOPY 443 /* 444 * MOVSL bulk memory moves can be slow when source and dest are not 445 * both 8-byte aligned. PII/PIII only like MOVSL with 8-byte alignment. 446 * 447 * Set the preferred alignment for Pentium Pro and newer processors, as 448 * it has only been tested on these. 449 */ 450 if (c->x86_vfm >= INTEL_PENTIUM_PRO) 451 movsl_mask.mask = 7; 452 #endif 453 454 intel_smp_check(c); 455 } 456 #else 457 static void intel_workarounds(struct cpuinfo_x86 *c) 458 { 459 } 460 #endif 461 462 static void srat_detect_node(struct cpuinfo_x86 *c) 463 { 464 #ifdef CONFIG_NUMA 465 unsigned node; 466 int cpu = smp_processor_id(); 467 468 /* Don't do the funky fallback heuristics the AMD version employs 469 for now. */ 470 node = numa_cpu_node(cpu); 471 if (node == NUMA_NO_NODE || !node_online(node)) { 472 /* reuse the value from init_cpu_to_node() */ 473 node = cpu_to_node(cpu); 474 } 475 numa_set_node(cpu, node); 476 #endif 477 } 478 479 static void init_cpuid_fault(struct cpuinfo_x86 *c) 480 { 481 u64 msr; 482 483 if (!rdmsrq_safe(MSR_PLATFORM_INFO, &msr)) { 484 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 485 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 486 } 487 } 488 489 static void init_intel_misc_features(struct cpuinfo_x86 *c) 490 { 491 u64 msr; 492 493 if (rdmsrq_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 494 return; 495 496 /* Clear all MISC features */ 497 this_cpu_write(msr_misc_features_shadow, 0); 498 499 /* Check features and update capabilities and shadow control bits */ 500 init_cpuid_fault(c); 501 probe_xeon_phi_r3mwait(c); 502 503 msr = this_cpu_read(msr_misc_features_shadow); 504 wrmsrq(MSR_MISC_FEATURES_ENABLES, msr); 505 } 506 507 /* 508 * This is a list of Intel CPUs that are known to suffer from downclocking when 509 * ZMM registers (512-bit vectors) are used. On these CPUs, when the kernel 510 * executes SIMD-optimized code such as cryptography functions or CRCs, it 511 * should prefer 256-bit (YMM) code to 512-bit (ZMM) code. 512 */ 513 static const struct x86_cpu_id zmm_exclusion_list[] = { 514 X86_MATCH_VFM(INTEL_SKYLAKE_X, 0), 515 X86_MATCH_VFM(INTEL_ICELAKE_X, 0), 516 X86_MATCH_VFM(INTEL_ICELAKE_D, 0), 517 X86_MATCH_VFM(INTEL_ICELAKE, 0), 518 X86_MATCH_VFM(INTEL_ICELAKE_L, 0), 519 X86_MATCH_VFM(INTEL_ICELAKE_NNPI, 0), 520 X86_MATCH_VFM(INTEL_TIGERLAKE_L, 0), 521 X86_MATCH_VFM(INTEL_TIGERLAKE, 0), 522 /* Allow Rocket Lake and later, and Sapphire Rapids and later. */ 523 {}, 524 }; 525 526 static void init_intel(struct cpuinfo_x86 *c) 527 { 528 early_init_intel(c); 529 530 intel_workarounds(c); 531 532 init_intel_cacheinfo(c); 533 534 if (c->cpuid_level > 9) { 535 unsigned eax = cpuid_eax(10); 536 /* Check for version and the number of counters */ 537 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 538 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 539 } 540 541 if (cpu_has(c, X86_FEATURE_XMM2)) 542 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 543 544 if (boot_cpu_has(X86_FEATURE_DS)) { 545 unsigned int l1, l2; 546 547 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 548 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) 549 set_cpu_cap(c, X86_FEATURE_BTS); 550 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) 551 set_cpu_cap(c, X86_FEATURE_PEBS); 552 } 553 554 if (boot_cpu_has(X86_FEATURE_CLFLUSH) && 555 (c->x86_vfm == INTEL_CORE2_DUNNINGTON || 556 c->x86_vfm == INTEL_NEHALEM_EX || 557 c->x86_vfm == INTEL_WESTMERE_EX)) 558 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 559 560 if (boot_cpu_has(X86_FEATURE_MWAIT) && 561 (c->x86_vfm == INTEL_ATOM_GOLDMONT || 562 c->x86_vfm == INTEL_LUNARLAKE_M)) 563 set_cpu_bug(c, X86_BUG_MONITOR); 564 565 #ifdef CONFIG_X86_64 566 if (c->x86 == 15) 567 c->x86_cache_alignment = c->x86_clflush_size * 2; 568 #else 569 /* 570 * Names for the Pentium II/Celeron processors 571 * detectable only by also checking the cache size. 572 * Dixon is NOT a Celeron. 573 */ 574 if (c->x86 == 6) { 575 unsigned int l2 = c->x86_cache_size; 576 char *p = NULL; 577 578 switch (c->x86_model) { 579 case 5: 580 if (l2 == 0) 581 p = "Celeron (Covington)"; 582 else if (l2 == 256) 583 p = "Mobile Pentium II (Dixon)"; 584 break; 585 586 case 6: 587 if (l2 == 128) 588 p = "Celeron (Mendocino)"; 589 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 590 p = "Celeron-A"; 591 break; 592 593 case 8: 594 if (l2 == 128) 595 p = "Celeron (Coppermine)"; 596 break; 597 } 598 599 if (p) 600 strcpy(c->x86_model_id, p); 601 } 602 #endif 603 604 if (x86_match_cpu(zmm_exclusion_list)) 605 set_cpu_cap(c, X86_FEATURE_PREFER_YMM); 606 607 /* Work around errata */ 608 srat_detect_node(c); 609 610 init_ia32_feat_ctl(c); 611 612 init_intel_misc_features(c); 613 614 split_lock_init(); 615 616 intel_init_thermal(c); 617 } 618 619 #ifdef CONFIG_X86_32 620 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 621 { 622 /* 623 * Intel PIII Tualatin. This comes in two flavours. 624 * One has 256kb of cache, the other 512. We have no way 625 * to determine which, so we use a boottime override 626 * for the 512kb model, and assume 256 otherwise. 627 */ 628 if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) 629 size = 256; 630 631 /* 632 * Intel Quark SoC X1000 contains a 4-way set associative 633 * 16K cache with a 16 byte cache line and 256 lines per tag 634 */ 635 if (c->x86_vfm == INTEL_QUARK_X1000) 636 size = 16; 637 return size; 638 } 639 #endif 640 641 static void intel_tlb_lookup(const struct leaf_0x2_table *desc) 642 { 643 short entries = desc->entries; 644 645 switch (desc->t_type) { 646 case STLB_4K: 647 tlb_lli_4k = max(tlb_lli_4k, entries); 648 tlb_lld_4k = max(tlb_lld_4k, entries); 649 break; 650 case STLB_4K_2M: 651 tlb_lli_4k = max(tlb_lli_4k, entries); 652 tlb_lld_4k = max(tlb_lld_4k, entries); 653 tlb_lli_2m = max(tlb_lli_2m, entries); 654 tlb_lld_2m = max(tlb_lld_2m, entries); 655 tlb_lli_4m = max(tlb_lli_4m, entries); 656 tlb_lld_4m = max(tlb_lld_4m, entries); 657 break; 658 case TLB_INST_ALL: 659 tlb_lli_4k = max(tlb_lli_4k, entries); 660 tlb_lli_2m = max(tlb_lli_2m, entries); 661 tlb_lli_4m = max(tlb_lli_4m, entries); 662 break; 663 case TLB_INST_4K: 664 tlb_lli_4k = max(tlb_lli_4k, entries); 665 break; 666 case TLB_INST_4M: 667 tlb_lli_4m = max(tlb_lli_4m, entries); 668 break; 669 case TLB_INST_2M_4M: 670 tlb_lli_2m = max(tlb_lli_2m, entries); 671 tlb_lli_4m = max(tlb_lli_4m, entries); 672 break; 673 case TLB_DATA_4K: 674 case TLB_DATA0_4K: 675 tlb_lld_4k = max(tlb_lld_4k, entries); 676 break; 677 case TLB_DATA_4M: 678 case TLB_DATA0_4M: 679 tlb_lld_4m = max(tlb_lld_4m, entries); 680 break; 681 case TLB_DATA_2M_4M: 682 case TLB_DATA0_2M_4M: 683 tlb_lld_2m = max(tlb_lld_2m, entries); 684 tlb_lld_4m = max(tlb_lld_4m, entries); 685 break; 686 case TLB_DATA_4K_4M: 687 tlb_lld_4k = max(tlb_lld_4k, entries); 688 tlb_lld_4m = max(tlb_lld_4m, entries); 689 break; 690 case TLB_DATA_1G_2M_4M: 691 tlb_lld_2m = max(tlb_lld_2m, TLB_0x63_2M_4M_ENTRIES); 692 tlb_lld_4m = max(tlb_lld_4m, TLB_0x63_2M_4M_ENTRIES); 693 fallthrough; 694 case TLB_DATA_1G: 695 tlb_lld_1g = max(tlb_lld_1g, entries); 696 break; 697 } 698 } 699 700 static void intel_detect_tlb(struct cpuinfo_x86 *c) 701 { 702 const struct leaf_0x2_table *desc; 703 union leaf_0x2_regs regs; 704 u8 *ptr; 705 706 if (c->cpuid_level < 2) 707 return; 708 709 cpuid_leaf_0x2(®s); 710 for_each_cpuid_0x2_desc(regs, ptr, desc) 711 intel_tlb_lookup(desc); 712 } 713 714 static const struct cpu_dev intel_cpu_dev = { 715 .c_vendor = "Intel", 716 .c_ident = { "GenuineIntel" }, 717 #ifdef CONFIG_X86_32 718 .legacy_models = { 719 { .family = 4, .model_names = 720 { 721 [0] = "486 DX-25/33", 722 [1] = "486 DX-50", 723 [2] = "486 SX", 724 [3] = "486 DX/2", 725 [4] = "486 SL", 726 [5] = "486 SX/2", 727 [7] = "486 DX/2-WB", 728 [8] = "486 DX/4", 729 [9] = "486 DX/4-WB" 730 } 731 }, 732 { .family = 5, .model_names = 733 { 734 [0] = "Pentium 60/66 A-step", 735 [1] = "Pentium 60/66", 736 [2] = "Pentium 75 - 200", 737 [3] = "OverDrive PODP5V83", 738 [4] = "Pentium MMX", 739 [7] = "Mobile Pentium 75 - 200", 740 [8] = "Mobile Pentium MMX", 741 [9] = "Quark SoC X1000", 742 } 743 }, 744 { .family = 6, .model_names = 745 { 746 [0] = "Pentium Pro A-step", 747 [1] = "Pentium Pro", 748 [3] = "Pentium II (Klamath)", 749 [4] = "Pentium II (Deschutes)", 750 [5] = "Pentium II (Deschutes)", 751 [6] = "Mobile Pentium II", 752 [7] = "Pentium III (Katmai)", 753 [8] = "Pentium III (Coppermine)", 754 [10] = "Pentium III (Cascades)", 755 [11] = "Pentium III (Tualatin)", 756 } 757 }, 758 { .family = 15, .model_names = 759 { 760 [0] = "Pentium 4 (Unknown)", 761 [1] = "Pentium 4 (Willamette)", 762 [2] = "Pentium 4 (Northwood)", 763 [4] = "Pentium 4 (Foster)", 764 [5] = "Pentium 4 (Foster)", 765 } 766 }, 767 }, 768 .legacy_cache_size = intel_size_cache, 769 #endif 770 .c_detect_tlb = intel_detect_tlb, 771 .c_early_init = early_init_intel, 772 .c_bsp_init = bsp_init_intel, 773 .c_init = init_intel, 774 .c_x86_vendor = X86_VENDOR_INTEL, 775 }; 776 777 cpu_dev_register(intel_cpu_dev); 778