1 #include <linux/kernel.h> 2 3 #include <linux/string.h> 4 #include <linux/bitops.h> 5 #include <linux/smp.h> 6 #include <linux/sched.h> 7 #include <linux/thread_info.h> 8 #include <linux/module.h> 9 #include <linux/uaccess.h> 10 11 #include <asm/processor.h> 12 #include <asm/pgtable.h> 13 #include <asm/msr.h> 14 #include <asm/bugs.h> 15 #include <asm/cpu.h> 16 17 #ifdef CONFIG_X86_64 18 #include <linux/topology.h> 19 #endif 20 21 #include "cpu.h" 22 23 #ifdef CONFIG_X86_LOCAL_APIC 24 #include <asm/mpspec.h> 25 #include <asm/apic.h> 26 #endif 27 28 static void early_init_intel(struct cpuinfo_x86 *c) 29 { 30 u64 misc_enable; 31 32 /* Unmask CPUID levels if masked: */ 33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 36 c->cpuid_level = cpuid_eax(0); 37 get_cpu_cap(c); 38 } 39 } 40 41 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 42 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 44 45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) { 46 unsigned lower_word; 47 48 wrmsr(MSR_IA32_UCODE_REV, 0, 0); 49 /* Required by the SDM */ 50 sync_core(); 51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode); 52 } 53 54 /* 55 * Atom erratum AAE44/AAF40/AAG38/AAH41: 56 * 57 * A race condition between speculative fetches and invalidating 58 * a large page. This is worked around in microcode, but we 59 * need the microcode to have already been loaded... so if it is 60 * not, recommend a BIOS update and disable large pages. 61 */ 62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && 63 c->microcode < 0x20e) { 64 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n"); 65 clear_cpu_cap(c, X86_FEATURE_PSE); 66 } 67 68 #ifdef CONFIG_X86_64 69 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 70 #else 71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 72 if (c->x86 == 15 && c->x86_cache_alignment == 64) 73 c->x86_cache_alignment = 128; 74 #endif 75 76 /* CPUID workaround for 0F33/0F34 CPU */ 77 if (c->x86 == 0xF && c->x86_model == 0x3 78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 79 c->x86_phys_bits = 36; 80 81 /* 82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 83 * with P/T states and does not stop in deep C-states. 84 * 85 * It is also reliable across cores and sockets. (but not across 86 * cabinets - we turn it off in that case explicitly.) 87 */ 88 if (c->x86_power & (1 << 8)) { 89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 91 if (!check_tsc_unstable()) 92 set_sched_clock_stable(); 93 } 94 95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 96 if (c->x86 == 6) { 97 switch (c->x86_model) { 98 case 0x27: /* Penwell */ 99 case 0x35: /* Cloverview */ 100 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 101 break; 102 default: 103 break; 104 } 105 } 106 107 /* 108 * There is a known erratum on Pentium III and Core Solo 109 * and Core Duo CPUs. 110 * " Page with PAT set to WC while associated MTRR is UC 111 * may consolidate to UC " 112 * Because of this erratum, it is better to stick with 113 * setting WC in MTRR rather than using PAT on these CPUs. 114 * 115 * Enable PAT WC only on P4, Core 2 or later CPUs. 116 */ 117 if (c->x86 == 6 && c->x86_model < 15) 118 clear_cpu_cap(c, X86_FEATURE_PAT); 119 120 #ifdef CONFIG_KMEMCHECK 121 /* 122 * P4s have a "fast strings" feature which causes single- 123 * stepping REP instructions to only generate a #DB on 124 * cache-line boundaries. 125 * 126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 127 * (model 2) with the same problem. 128 */ 129 if (c->x86 == 15) 130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) 132 pr_info("kmemcheck: Disabling fast string operations\n"); 133 #endif 134 135 /* 136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 137 * clear the fast string and enhanced fast string CPU capabilities. 138 */ 139 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 141 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 142 printk(KERN_INFO "Disabled fast string operations\n"); 143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 144 setup_clear_cpu_cap(X86_FEATURE_ERMS); 145 } 146 } 147 148 /* 149 * Intel Quark Core DevMan_001.pdf section 6.4.11 150 * "The operating system also is required to invalidate (i.e., flush) 151 * the TLB when any changes are made to any of the page table entries. 152 * The operating system must reload CR3 to cause the TLB to be flushed" 153 * 154 * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should 155 * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 156 * to be modified 157 */ 158 if (c->x86 == 5 && c->x86_model == 9) { 159 pr_info("Disabling PGE capability bit\n"); 160 setup_clear_cpu_cap(X86_FEATURE_PGE); 161 } 162 } 163 164 #ifdef CONFIG_X86_32 165 /* 166 * Early probe support logic for ppro memory erratum #50 167 * 168 * This is called before we do cpu ident work 169 */ 170 171 int ppro_with_ram_bug(void) 172 { 173 /* Uses data from early_cpu_detect now */ 174 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 175 boot_cpu_data.x86 == 6 && 176 boot_cpu_data.x86_model == 1 && 177 boot_cpu_data.x86_mask < 8) { 178 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 179 return 1; 180 } 181 return 0; 182 } 183 184 static void intel_smp_check(struct cpuinfo_x86 *c) 185 { 186 /* calling is from identify_secondary_cpu() ? */ 187 if (!c->cpu_index) 188 return; 189 190 /* 191 * Mask B, Pentium, but not Pentium MMX 192 */ 193 if (c->x86 == 5 && 194 c->x86_mask >= 1 && c->x86_mask <= 4 && 195 c->x86_model <= 3) { 196 /* 197 * Remember we have B step Pentia with bugs 198 */ 199 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 200 "with B stepping processors.\n"); 201 } 202 } 203 204 static int forcepae; 205 static int __init forcepae_setup(char *__unused) 206 { 207 forcepae = 1; 208 return 1; 209 } 210 __setup("forcepae", forcepae_setup); 211 212 static void intel_workarounds(struct cpuinfo_x86 *c) 213 { 214 #ifdef CONFIG_X86_F00F_BUG 215 /* 216 * All models of Pentium and Pentium with MMX technology CPUs 217 * have the F0 0F bug, which lets nonprivileged users lock up the 218 * system. Announce that the fault handler will be checking for it. 219 * The Quark is also family 5, but does not have the same bug. 220 */ 221 clear_cpu_bug(c, X86_BUG_F00F); 222 if (!paravirt_enabled() && c->x86 == 5 && c->x86_model < 9) { 223 static int f00f_workaround_enabled; 224 225 set_cpu_bug(c, X86_BUG_F00F); 226 if (!f00f_workaround_enabled) { 227 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 228 f00f_workaround_enabled = 1; 229 } 230 } 231 #endif 232 233 /* 234 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 235 * model 3 mask 3 236 */ 237 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 238 clear_cpu_cap(c, X86_FEATURE_SEP); 239 240 /* 241 * PAE CPUID issue: many Pentium M report no PAE but may have a 242 * functionally usable PAE implementation. 243 * Forcefully enable PAE if kernel parameter "forcepae" is present. 244 */ 245 if (forcepae) { 246 printk(KERN_WARNING "PAE forced!\n"); 247 set_cpu_cap(c, X86_FEATURE_PAE); 248 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 249 } 250 251 /* 252 * P4 Xeon errata 037 workaround. 253 * Hardware prefetcher may cause stale data to be loaded into the cache. 254 */ 255 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 256 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 257 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 258 > 0) { 259 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 260 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); 261 } 262 } 263 264 /* 265 * See if we have a good local APIC by checking for buggy Pentia, 266 * i.e. all B steppings and the C2 stepping of P54C when using their 267 * integrated APIC (see 11AP erratum in "Pentium Processor 268 * Specification Update"). 269 */ 270 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && 271 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 272 set_cpu_bug(c, X86_BUG_11AP); 273 274 275 #ifdef CONFIG_X86_INTEL_USERCOPY 276 /* 277 * Set up the preferred alignment for movsl bulk memory moves 278 */ 279 switch (c->x86) { 280 case 4: /* 486: untested */ 281 break; 282 case 5: /* Old Pentia: untested */ 283 break; 284 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 285 movsl_mask.mask = 7; 286 break; 287 case 15: /* P4 is OK down to 8-byte alignment */ 288 movsl_mask.mask = 7; 289 break; 290 } 291 #endif 292 293 intel_smp_check(c); 294 } 295 #else 296 static void intel_workarounds(struct cpuinfo_x86 *c) 297 { 298 } 299 #endif 300 301 static void srat_detect_node(struct cpuinfo_x86 *c) 302 { 303 #ifdef CONFIG_NUMA 304 unsigned node; 305 int cpu = smp_processor_id(); 306 307 /* Don't do the funky fallback heuristics the AMD version employs 308 for now. */ 309 node = numa_cpu_node(cpu); 310 if (node == NUMA_NO_NODE || !node_online(node)) { 311 /* reuse the value from init_cpu_to_node() */ 312 node = cpu_to_node(cpu); 313 } 314 numa_set_node(cpu, node); 315 #endif 316 } 317 318 /* 319 * find out the number of processor cores on the die 320 */ 321 static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 322 { 323 unsigned int eax, ebx, ecx, edx; 324 325 if (c->cpuid_level < 4) 326 return 1; 327 328 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 329 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 330 if (eax & 0x1f) 331 return (eax >> 26) + 1; 332 else 333 return 1; 334 } 335 336 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 337 { 338 /* Intel VMX MSR indicated features */ 339 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 340 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 341 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 342 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 343 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 344 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 345 346 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 347 348 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 349 clear_cpu_cap(c, X86_FEATURE_VNMI); 350 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 351 clear_cpu_cap(c, X86_FEATURE_EPT); 352 clear_cpu_cap(c, X86_FEATURE_VPID); 353 354 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 355 msr_ctl = vmx_msr_high | vmx_msr_low; 356 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 357 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 358 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 359 set_cpu_cap(c, X86_FEATURE_VNMI); 360 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 361 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 362 vmx_msr_low, vmx_msr_high); 363 msr_ctl2 = vmx_msr_high | vmx_msr_low; 364 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 365 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 366 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 367 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 368 set_cpu_cap(c, X86_FEATURE_EPT); 369 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 370 set_cpu_cap(c, X86_FEATURE_VPID); 371 } 372 } 373 374 static void init_intel_energy_perf(struct cpuinfo_x86 *c) 375 { 376 u64 epb; 377 378 /* 379 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. 380 * (x86_energy_perf_policy(8) is available to change it at run-time.) 381 */ 382 if (!cpu_has(c, X86_FEATURE_EPB)) 383 return; 384 385 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 386 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) 387 return; 388 389 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 390 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); 391 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 392 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 393 } 394 395 static void intel_bsp_resume(struct cpuinfo_x86 *c) 396 { 397 /* 398 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, 399 * so reinitialize it properly like during bootup: 400 */ 401 init_intel_energy_perf(c); 402 } 403 404 static void init_intel(struct cpuinfo_x86 *c) 405 { 406 unsigned int l2 = 0; 407 408 early_init_intel(c); 409 410 intel_workarounds(c); 411 412 /* 413 * Detect the extended topology information if available. This 414 * will reinitialise the initial_apicid which will be used 415 * in init_intel_cacheinfo() 416 */ 417 detect_extended_topology(c); 418 419 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 420 /* 421 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 422 * detection. 423 */ 424 c->x86_max_cores = intel_num_cpu_cores(c); 425 #ifdef CONFIG_X86_32 426 detect_ht(c); 427 #endif 428 } 429 430 l2 = init_intel_cacheinfo(c); 431 432 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 433 if (l2 == 0) { 434 cpu_detect_cache_sizes(c); 435 l2 = c->x86_cache_size; 436 } 437 438 if (c->cpuid_level > 9) { 439 unsigned eax = cpuid_eax(10); 440 /* Check for version and the number of counters */ 441 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 442 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 443 } 444 445 if (cpu_has_xmm2) 446 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 447 if (cpu_has_ds) { 448 unsigned int l1; 449 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 450 if (!(l1 & (1<<11))) 451 set_cpu_cap(c, X86_FEATURE_BTS); 452 if (!(l1 & (1<<12))) 453 set_cpu_cap(c, X86_FEATURE_PEBS); 454 } 455 456 if (c->x86 == 6 && cpu_has_clflush && 457 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 458 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 459 460 #ifdef CONFIG_X86_64 461 if (c->x86 == 15) 462 c->x86_cache_alignment = c->x86_clflush_size * 2; 463 if (c->x86 == 6) 464 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 465 #else 466 /* 467 * Names for the Pentium II/Celeron processors 468 * detectable only by also checking the cache size. 469 * Dixon is NOT a Celeron. 470 */ 471 if (c->x86 == 6) { 472 char *p = NULL; 473 474 switch (c->x86_model) { 475 case 5: 476 if (l2 == 0) 477 p = "Celeron (Covington)"; 478 else if (l2 == 256) 479 p = "Mobile Pentium II (Dixon)"; 480 break; 481 482 case 6: 483 if (l2 == 128) 484 p = "Celeron (Mendocino)"; 485 else if (c->x86_mask == 0 || c->x86_mask == 5) 486 p = "Celeron-A"; 487 break; 488 489 case 8: 490 if (l2 == 128) 491 p = "Celeron (Coppermine)"; 492 break; 493 } 494 495 if (p) 496 strcpy(c->x86_model_id, p); 497 } 498 499 if (c->x86 == 15) 500 set_cpu_cap(c, X86_FEATURE_P4); 501 if (c->x86 == 6) 502 set_cpu_cap(c, X86_FEATURE_P3); 503 #endif 504 505 /* Work around errata */ 506 srat_detect_node(c); 507 508 if (cpu_has(c, X86_FEATURE_VMX)) 509 detect_vmx_virtcap(c); 510 511 init_intel_energy_perf(c); 512 } 513 514 #ifdef CONFIG_X86_32 515 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 516 { 517 /* 518 * Intel PIII Tualatin. This comes in two flavours. 519 * One has 256kb of cache, the other 512. We have no way 520 * to determine which, so we use a boottime override 521 * for the 512kb model, and assume 256 otherwise. 522 */ 523 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 524 size = 256; 525 526 /* 527 * Intel Quark SoC X1000 contains a 4-way set associative 528 * 16K cache with a 16 byte cache line and 256 lines per tag 529 */ 530 if ((c->x86 == 5) && (c->x86_model == 9)) 531 size = 16; 532 return size; 533 } 534 #endif 535 536 #define TLB_INST_4K 0x01 537 #define TLB_INST_4M 0x02 538 #define TLB_INST_2M_4M 0x03 539 540 #define TLB_INST_ALL 0x05 541 #define TLB_INST_1G 0x06 542 543 #define TLB_DATA_4K 0x11 544 #define TLB_DATA_4M 0x12 545 #define TLB_DATA_2M_4M 0x13 546 #define TLB_DATA_4K_4M 0x14 547 548 #define TLB_DATA_1G 0x16 549 550 #define TLB_DATA0_4K 0x21 551 #define TLB_DATA0_4M 0x22 552 #define TLB_DATA0_2M_4M 0x23 553 554 #define STLB_4K 0x41 555 #define STLB_4K_2M 0x42 556 557 static const struct _tlb_table intel_tlb_table[] = { 558 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 559 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 560 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 561 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 562 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 563 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 564 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 565 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 566 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 567 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 568 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 569 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 570 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 571 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 572 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 573 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 574 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 575 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 576 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 577 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 578 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 579 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 580 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 581 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 582 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 583 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 584 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 585 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 586 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 587 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 588 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 589 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 590 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 591 { 0x00, 0, 0 } 592 }; 593 594 static void intel_tlb_lookup(const unsigned char desc) 595 { 596 unsigned char k; 597 if (desc == 0) 598 return; 599 600 /* look up this descriptor in the table */ 601 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 602 intel_tlb_table[k].descriptor != 0; k++) 603 ; 604 605 if (intel_tlb_table[k].tlb_type == 0) 606 return; 607 608 switch (intel_tlb_table[k].tlb_type) { 609 case STLB_4K: 610 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 611 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 612 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 613 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 614 break; 615 case STLB_4K_2M: 616 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 617 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 618 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 619 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 620 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 621 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 622 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 623 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 624 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 625 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 626 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 627 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 628 break; 629 case TLB_INST_ALL: 630 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 631 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 632 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 633 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 634 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 635 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 636 break; 637 case TLB_INST_4K: 638 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 639 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 640 break; 641 case TLB_INST_4M: 642 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 643 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 644 break; 645 case TLB_INST_2M_4M: 646 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 647 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 648 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 649 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 650 break; 651 case TLB_DATA_4K: 652 case TLB_DATA0_4K: 653 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 654 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 655 break; 656 case TLB_DATA_4M: 657 case TLB_DATA0_4M: 658 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 659 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 660 break; 661 case TLB_DATA_2M_4M: 662 case TLB_DATA0_2M_4M: 663 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 664 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 665 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 666 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 667 break; 668 case TLB_DATA_4K_4M: 669 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 670 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 671 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 672 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 673 break; 674 case TLB_DATA_1G: 675 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 676 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 677 break; 678 } 679 } 680 681 static void intel_detect_tlb(struct cpuinfo_x86 *c) 682 { 683 int i, j, n; 684 unsigned int regs[4]; 685 unsigned char *desc = (unsigned char *)regs; 686 687 if (c->cpuid_level < 2) 688 return; 689 690 /* Number of times to iterate */ 691 n = cpuid_eax(2) & 0xFF; 692 693 for (i = 0 ; i < n ; i++) { 694 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 695 696 /* If bit 31 is set, this is an unknown format */ 697 for (j = 0 ; j < 3 ; j++) 698 if (regs[j] & (1 << 31)) 699 regs[j] = 0; 700 701 /* Byte 0 is level count, not a descriptor */ 702 for (j = 1 ; j < 16 ; j++) 703 intel_tlb_lookup(desc[j]); 704 } 705 } 706 707 static const struct cpu_dev intel_cpu_dev = { 708 .c_vendor = "Intel", 709 .c_ident = { "GenuineIntel" }, 710 #ifdef CONFIG_X86_32 711 .legacy_models = { 712 { .family = 4, .model_names = 713 { 714 [0] = "486 DX-25/33", 715 [1] = "486 DX-50", 716 [2] = "486 SX", 717 [3] = "486 DX/2", 718 [4] = "486 SL", 719 [5] = "486 SX/2", 720 [7] = "486 DX/2-WB", 721 [8] = "486 DX/4", 722 [9] = "486 DX/4-WB" 723 } 724 }, 725 { .family = 5, .model_names = 726 { 727 [0] = "Pentium 60/66 A-step", 728 [1] = "Pentium 60/66", 729 [2] = "Pentium 75 - 200", 730 [3] = "OverDrive PODP5V83", 731 [4] = "Pentium MMX", 732 [7] = "Mobile Pentium 75 - 200", 733 [8] = "Mobile Pentium MMX", 734 [9] = "Quark SoC X1000", 735 } 736 }, 737 { .family = 6, .model_names = 738 { 739 [0] = "Pentium Pro A-step", 740 [1] = "Pentium Pro", 741 [3] = "Pentium II (Klamath)", 742 [4] = "Pentium II (Deschutes)", 743 [5] = "Pentium II (Deschutes)", 744 [6] = "Mobile Pentium II", 745 [7] = "Pentium III (Katmai)", 746 [8] = "Pentium III (Coppermine)", 747 [10] = "Pentium III (Cascades)", 748 [11] = "Pentium III (Tualatin)", 749 } 750 }, 751 { .family = 15, .model_names = 752 { 753 [0] = "Pentium 4 (Unknown)", 754 [1] = "Pentium 4 (Willamette)", 755 [2] = "Pentium 4 (Northwood)", 756 [4] = "Pentium 4 (Foster)", 757 [5] = "Pentium 4 (Foster)", 758 } 759 }, 760 }, 761 .legacy_cache_size = intel_size_cache, 762 #endif 763 .c_detect_tlb = intel_detect_tlb, 764 .c_early_init = early_init_intel, 765 .c_init = init_intel, 766 .c_bsp_resume = intel_bsp_resume, 767 .c_x86_vendor = X86_VENDOR_INTEL, 768 }; 769 770 cpu_dev_register(intel_cpu_dev); 771 772