1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 #include <linux/pgtable.h> 4 5 #include <linux/string.h> 6 #include <linux/bitops.h> 7 #include <linux/smp.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/semaphore.h> 11 #include <linux/thread_info.h> 12 #include <linux/init.h> 13 #include <linux/uaccess.h> 14 #include <linux/workqueue.h> 15 #include <linux/delay.h> 16 #include <linux/cpuhotplug.h> 17 18 #include <asm/cpufeature.h> 19 #include <asm/msr.h> 20 #include <asm/bugs.h> 21 #include <asm/cpu.h> 22 #include <asm/intel-family.h> 23 #include <asm/microcode.h> 24 #include <asm/hwcap2.h> 25 #include <asm/elf.h> 26 #include <asm/cpu_device_id.h> 27 #include <asm/cmdline.h> 28 #include <asm/traps.h> 29 #include <asm/resctrl.h> 30 #include <asm/numa.h> 31 #include <asm/thermal.h> 32 33 #ifdef CONFIG_X86_64 34 #include <linux/topology.h> 35 #endif 36 37 #include "cpu.h" 38 39 #ifdef CONFIG_X86_LOCAL_APIC 40 #include <asm/mpspec.h> 41 #include <asm/apic.h> 42 #endif 43 44 enum split_lock_detect_state { 45 sld_off = 0, 46 sld_warn, 47 sld_fatal, 48 sld_ratelimit, 49 }; 50 51 /* 52 * Default to sld_off because most systems do not support split lock detection. 53 * sld_state_setup() will switch this to sld_warn on systems that support 54 * split lock/bus lock detect, unless there is a command line override. 55 */ 56 static enum split_lock_detect_state sld_state __ro_after_init = sld_off; 57 static u64 msr_test_ctrl_cache __ro_after_init; 58 59 /* 60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch 61 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it 62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'. 63 */ 64 static bool cpu_model_supports_sld __ro_after_init; 65 66 /* 67 * Processors which have self-snooping capability can handle conflicting 68 * memory type across CPUs by snooping its own cache. However, there exists 69 * CPU models in which having conflicting memory types still leads to 70 * unpredictable behavior, machine check errors, or hangs. Clear this 71 * feature to prevent its use on machines with known erratas. 72 */ 73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) 74 { 75 switch (c->x86_model) { 76 case INTEL_FAM6_CORE_YONAH: 77 case INTEL_FAM6_CORE2_MEROM: 78 case INTEL_FAM6_CORE2_MEROM_L: 79 case INTEL_FAM6_CORE2_PENRYN: 80 case INTEL_FAM6_CORE2_DUNNINGTON: 81 case INTEL_FAM6_NEHALEM: 82 case INTEL_FAM6_NEHALEM_G: 83 case INTEL_FAM6_NEHALEM_EP: 84 case INTEL_FAM6_NEHALEM_EX: 85 case INTEL_FAM6_WESTMERE: 86 case INTEL_FAM6_WESTMERE_EP: 87 case INTEL_FAM6_SANDYBRIDGE: 88 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); 89 } 90 } 91 92 static bool ring3mwait_disabled __read_mostly; 93 94 static int __init ring3mwait_disable(char *__unused) 95 { 96 ring3mwait_disabled = true; 97 return 1; 98 } 99 __setup("ring3mwait=disable", ring3mwait_disable); 100 101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 102 { 103 /* 104 * Ring 3 MONITOR/MWAIT feature cannot be detected without 105 * cpu model and family comparison. 106 */ 107 if (c->x86 != 6) 108 return; 109 switch (c->x86_model) { 110 case INTEL_FAM6_XEON_PHI_KNL: 111 case INTEL_FAM6_XEON_PHI_KNM: 112 break; 113 default: 114 return; 115 } 116 117 if (ring3mwait_disabled) 118 return; 119 120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 121 this_cpu_or(msr_misc_features_shadow, 122 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 123 124 if (c == &boot_cpu_data) 125 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 126 } 127 128 /* 129 * Early microcode releases for the Spectre v2 mitigation were broken. 130 * Information taken from; 131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 132 * - https://kb.vmware.com/s/article/52345 133 * - Microcode revisions observed in the wild 134 * - Release note from 20180108 microcode release 135 */ 136 struct sku_microcode { 137 u8 model; 138 u8 stepping; 139 u32 microcode; 140 }; 141 static const struct sku_microcode spectre_bad_microcodes[] = { 142 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 }, 143 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 }, 144 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 }, 145 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 }, 146 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 }, 147 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, 148 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, 149 { INTEL_FAM6_BROADWELL, 0x04, 0x28 }, 150 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b }, 151 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 }, 152 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 }, 153 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, 154 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 }, 155 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 }, 156 { INTEL_FAM6_HASWELL, 0x03, 0x23 }, 157 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, 158 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, 159 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, 160 /* Observed in the wild */ 161 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, 162 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, 163 }; 164 165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 166 { 167 int i; 168 169 /* 170 * We know that the hypervisor lie to us on the microcode version so 171 * we may as well hope that it is running the correct version. 172 */ 173 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 174 return false; 175 176 if (c->x86 != 6) 177 return false; 178 179 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 180 if (c->x86_model == spectre_bad_microcodes[i].model && 181 c->x86_stepping == spectre_bad_microcodes[i].stepping) 182 return (c->microcode <= spectre_bad_microcodes[i].microcode); 183 } 184 return false; 185 } 186 187 #define MSR_IA32_TME_ACTIVATE 0x982 188 189 /* Helpers to access TME_ACTIVATE MSR */ 190 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 191 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 192 193 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ 194 #define TME_ACTIVATE_POLICY_AES_XTS_128 0 195 196 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 197 198 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ 199 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 200 201 /* Values for mktme_status (SW only construct) */ 202 #define MKTME_ENABLED 0 203 #define MKTME_DISABLED 1 204 #define MKTME_UNINITIALIZED 2 205 static int mktme_status = MKTME_UNINITIALIZED; 206 207 static void detect_tme_early(struct cpuinfo_x86 *c) 208 { 209 u64 tme_activate, tme_policy, tme_crypto_algs; 210 int keyid_bits = 0, nr_keyids = 0; 211 static u64 tme_activate_cpu0 = 0; 212 213 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); 214 215 if (mktme_status != MKTME_UNINITIALIZED) { 216 if (tme_activate != tme_activate_cpu0) { 217 /* Broken BIOS? */ 218 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); 219 pr_err_once("x86/tme: MKTME is not usable\n"); 220 mktme_status = MKTME_DISABLED; 221 222 /* Proceed. We may need to exclude bits from x86_phys_bits. */ 223 } 224 } else { 225 tme_activate_cpu0 = tme_activate; 226 } 227 228 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 229 pr_info_once("x86/tme: not enabled by BIOS\n"); 230 mktme_status = MKTME_DISABLED; 231 clear_cpu_cap(c, X86_FEATURE_TME); 232 return; 233 } 234 235 if (mktme_status != MKTME_UNINITIALIZED) 236 goto detect_keyid_bits; 237 238 pr_info("x86/tme: enabled by BIOS\n"); 239 240 tme_policy = TME_ACTIVATE_POLICY(tme_activate); 241 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) 242 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); 243 244 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); 245 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { 246 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", 247 tme_crypto_algs); 248 mktme_status = MKTME_DISABLED; 249 } 250 detect_keyid_bits: 251 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 252 nr_keyids = (1UL << keyid_bits) - 1; 253 if (nr_keyids) { 254 pr_info_once("x86/mktme: enabled by BIOS\n"); 255 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); 256 } else { 257 pr_info_once("x86/mktme: disabled by BIOS\n"); 258 } 259 260 if (mktme_status == MKTME_UNINITIALIZED) { 261 /* MKTME is usable */ 262 mktme_status = MKTME_ENABLED; 263 } 264 265 /* 266 * KeyID bits effectively lower the number of physical address 267 * bits. Update cpuinfo_x86::x86_phys_bits accordingly. 268 */ 269 c->x86_phys_bits -= keyid_bits; 270 } 271 272 static void early_init_intel(struct cpuinfo_x86 *c) 273 { 274 u64 misc_enable; 275 276 /* Unmask CPUID levels if masked: */ 277 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 278 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 279 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 280 c->cpuid_level = cpuid_eax(0); 281 get_cpu_cap(c); 282 } 283 } 284 285 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 286 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 287 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 288 289 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 290 c->microcode = intel_get_microcode_revision(); 291 292 /* Now if any of them are set, check the blacklist and clear the lot */ 293 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 294 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 295 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 296 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 297 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 298 setup_clear_cpu_cap(X86_FEATURE_IBRS); 299 setup_clear_cpu_cap(X86_FEATURE_IBPB); 300 setup_clear_cpu_cap(X86_FEATURE_STIBP); 301 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 302 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 303 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 304 setup_clear_cpu_cap(X86_FEATURE_SSBD); 305 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 306 } 307 308 /* 309 * Atom erratum AAE44/AAF40/AAG38/AAH41: 310 * 311 * A race condition between speculative fetches and invalidating 312 * a large page. This is worked around in microcode, but we 313 * need the microcode to have already been loaded... so if it is 314 * not, recommend a BIOS update and disable large pages. 315 */ 316 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && 317 c->microcode < 0x20e) { 318 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 319 clear_cpu_cap(c, X86_FEATURE_PSE); 320 } 321 322 #ifdef CONFIG_X86_64 323 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 324 #else 325 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 326 if (c->x86 == 15 && c->x86_cache_alignment == 64) 327 c->x86_cache_alignment = 128; 328 #endif 329 330 /* CPUID workaround for 0F33/0F34 CPU */ 331 if (c->x86 == 0xF && c->x86_model == 0x3 332 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 333 c->x86_phys_bits = 36; 334 335 /* 336 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 337 * with P/T states and does not stop in deep C-states. 338 * 339 * It is also reliable across cores and sockets. (but not across 340 * cabinets - we turn it off in that case explicitly.) 341 */ 342 if (c->x86_power & (1 << 8)) { 343 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 344 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 345 } 346 347 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 348 if (c->x86 == 6) { 349 switch (c->x86_model) { 350 case INTEL_FAM6_ATOM_SALTWELL_MID: 351 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 352 case INTEL_FAM6_ATOM_SILVERMONT_MID: 353 case INTEL_FAM6_ATOM_AIRMONT_NP: 354 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 355 break; 356 default: 357 break; 358 } 359 } 360 361 /* 362 * There is a known erratum on Pentium III and Core Solo 363 * and Core Duo CPUs. 364 * " Page with PAT set to WC while associated MTRR is UC 365 * may consolidate to UC " 366 * Because of this erratum, it is better to stick with 367 * setting WC in MTRR rather than using PAT on these CPUs. 368 * 369 * Enable PAT WC only on P4, Core 2 or later CPUs. 370 */ 371 if (c->x86 == 6 && c->x86_model < 15) 372 clear_cpu_cap(c, X86_FEATURE_PAT); 373 374 /* 375 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 376 * clear the fast string and enhanced fast string CPU capabilities. 377 */ 378 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 379 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 380 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 381 pr_info("Disabled fast string operations\n"); 382 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 383 setup_clear_cpu_cap(X86_FEATURE_ERMS); 384 } 385 } 386 387 /* 388 * Intel Quark Core DevMan_001.pdf section 6.4.11 389 * "The operating system also is required to invalidate (i.e., flush) 390 * the TLB when any changes are made to any of the page table entries. 391 * The operating system must reload CR3 to cause the TLB to be flushed" 392 * 393 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 394 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE 395 * to be modified. 396 */ 397 if (c->x86 == 5 && c->x86_model == 9) { 398 pr_info("Disabling PGE capability bit\n"); 399 setup_clear_cpu_cap(X86_FEATURE_PGE); 400 } 401 402 check_memory_type_self_snoop_errata(c); 403 404 /* 405 * Adjust the number of physical bits early because it affects the 406 * valid bits of the MTRR mask registers. 407 */ 408 if (cpu_has(c, X86_FEATURE_TME)) 409 detect_tme_early(c); 410 } 411 412 static void bsp_init_intel(struct cpuinfo_x86 *c) 413 { 414 resctrl_cpu_detect(c); 415 } 416 417 #ifdef CONFIG_X86_32 418 /* 419 * Early probe support logic for ppro memory erratum #50 420 * 421 * This is called before we do cpu ident work 422 */ 423 424 int ppro_with_ram_bug(void) 425 { 426 /* Uses data from early_cpu_detect now */ 427 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 428 boot_cpu_data.x86 == 6 && 429 boot_cpu_data.x86_model == 1 && 430 boot_cpu_data.x86_stepping < 8) { 431 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 432 return 1; 433 } 434 return 0; 435 } 436 437 static void intel_smp_check(struct cpuinfo_x86 *c) 438 { 439 /* calling is from identify_secondary_cpu() ? */ 440 if (!c->cpu_index) 441 return; 442 443 /* 444 * Mask B, Pentium, but not Pentium MMX 445 */ 446 if (c->x86 == 5 && 447 c->x86_stepping >= 1 && c->x86_stepping <= 4 && 448 c->x86_model <= 3) { 449 /* 450 * Remember we have B step Pentia with bugs 451 */ 452 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 453 "with B stepping processors.\n"); 454 } 455 } 456 457 static int forcepae; 458 static int __init forcepae_setup(char *__unused) 459 { 460 forcepae = 1; 461 return 1; 462 } 463 __setup("forcepae", forcepae_setup); 464 465 static void intel_workarounds(struct cpuinfo_x86 *c) 466 { 467 #ifdef CONFIG_X86_F00F_BUG 468 /* 469 * All models of Pentium and Pentium with MMX technology CPUs 470 * have the F0 0F bug, which lets nonprivileged users lock up the 471 * system. Announce that the fault handler will be checking for it. 472 * The Quark is also family 5, but does not have the same bug. 473 */ 474 clear_cpu_bug(c, X86_BUG_F00F); 475 if (c->x86 == 5 && c->x86_model < 9) { 476 static int f00f_workaround_enabled; 477 478 set_cpu_bug(c, X86_BUG_F00F); 479 if (!f00f_workaround_enabled) { 480 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 481 f00f_workaround_enabled = 1; 482 } 483 } 484 #endif 485 486 /* 487 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 488 * model 3 mask 3 489 */ 490 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) 491 clear_cpu_cap(c, X86_FEATURE_SEP); 492 493 /* 494 * PAE CPUID issue: many Pentium M report no PAE but may have a 495 * functionally usable PAE implementation. 496 * Forcefully enable PAE if kernel parameter "forcepae" is present. 497 */ 498 if (forcepae) { 499 pr_warn("PAE forced!\n"); 500 set_cpu_cap(c, X86_FEATURE_PAE); 501 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 502 } 503 504 /* 505 * P4 Xeon erratum 037 workaround. 506 * Hardware prefetcher may cause stale data to be loaded into the cache. 507 */ 508 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { 509 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 510 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 511 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 512 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 513 } 514 } 515 516 /* 517 * See if we have a good local APIC by checking for buggy Pentia, 518 * i.e. all B steppings and the C2 stepping of P54C when using their 519 * integrated APIC (see 11AP erratum in "Pentium Processor 520 * Specification Update"). 521 */ 522 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 523 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 524 set_cpu_bug(c, X86_BUG_11AP); 525 526 527 #ifdef CONFIG_X86_INTEL_USERCOPY 528 /* 529 * Set up the preferred alignment for movsl bulk memory moves 530 */ 531 switch (c->x86) { 532 case 4: /* 486: untested */ 533 break; 534 case 5: /* Old Pentia: untested */ 535 break; 536 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 537 movsl_mask.mask = 7; 538 break; 539 case 15: /* P4 is OK down to 8-byte alignment */ 540 movsl_mask.mask = 7; 541 break; 542 } 543 #endif 544 545 intel_smp_check(c); 546 } 547 #else 548 static void intel_workarounds(struct cpuinfo_x86 *c) 549 { 550 } 551 #endif 552 553 static void srat_detect_node(struct cpuinfo_x86 *c) 554 { 555 #ifdef CONFIG_NUMA 556 unsigned node; 557 int cpu = smp_processor_id(); 558 559 /* Don't do the funky fallback heuristics the AMD version employs 560 for now. */ 561 node = numa_cpu_node(cpu); 562 if (node == NUMA_NO_NODE || !node_online(node)) { 563 /* reuse the value from init_cpu_to_node() */ 564 node = cpu_to_node(cpu); 565 } 566 numa_set_node(cpu, node); 567 #endif 568 } 569 570 static void init_cpuid_fault(struct cpuinfo_x86 *c) 571 { 572 u64 msr; 573 574 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 575 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 576 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 577 } 578 } 579 580 static void init_intel_misc_features(struct cpuinfo_x86 *c) 581 { 582 u64 msr; 583 584 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 585 return; 586 587 /* Clear all MISC features */ 588 this_cpu_write(msr_misc_features_shadow, 0); 589 590 /* Check features and update capabilities and shadow control bits */ 591 init_cpuid_fault(c); 592 probe_xeon_phi_r3mwait(c); 593 594 msr = this_cpu_read(msr_misc_features_shadow); 595 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 596 } 597 598 static void split_lock_init(void); 599 static void bus_lock_init(void); 600 601 static void init_intel(struct cpuinfo_x86 *c) 602 { 603 early_init_intel(c); 604 605 intel_workarounds(c); 606 607 init_intel_cacheinfo(c); 608 609 if (c->cpuid_level > 9) { 610 unsigned eax = cpuid_eax(10); 611 /* Check for version and the number of counters */ 612 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 613 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 614 } 615 616 if (cpu_has(c, X86_FEATURE_XMM2)) 617 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 618 619 if (boot_cpu_has(X86_FEATURE_DS)) { 620 unsigned int l1, l2; 621 622 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 623 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) 624 set_cpu_cap(c, X86_FEATURE_BTS); 625 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) 626 set_cpu_cap(c, X86_FEATURE_PEBS); 627 } 628 629 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 630 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 631 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 632 633 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 634 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 635 set_cpu_bug(c, X86_BUG_MONITOR); 636 637 #ifdef CONFIG_X86_64 638 if (c->x86 == 15) 639 c->x86_cache_alignment = c->x86_clflush_size * 2; 640 if (c->x86 == 6) 641 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 642 #else 643 /* 644 * Names for the Pentium II/Celeron processors 645 * detectable only by also checking the cache size. 646 * Dixon is NOT a Celeron. 647 */ 648 if (c->x86 == 6) { 649 unsigned int l2 = c->x86_cache_size; 650 char *p = NULL; 651 652 switch (c->x86_model) { 653 case 5: 654 if (l2 == 0) 655 p = "Celeron (Covington)"; 656 else if (l2 == 256) 657 p = "Mobile Pentium II (Dixon)"; 658 break; 659 660 case 6: 661 if (l2 == 128) 662 p = "Celeron (Mendocino)"; 663 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 664 p = "Celeron-A"; 665 break; 666 667 case 8: 668 if (l2 == 128) 669 p = "Celeron (Coppermine)"; 670 break; 671 } 672 673 if (p) 674 strcpy(c->x86_model_id, p); 675 } 676 677 if (c->x86 == 15) 678 set_cpu_cap(c, X86_FEATURE_P4); 679 if (c->x86 == 6) 680 set_cpu_cap(c, X86_FEATURE_P3); 681 #endif 682 683 /* Work around errata */ 684 srat_detect_node(c); 685 686 init_ia32_feat_ctl(c); 687 688 init_intel_misc_features(c); 689 690 split_lock_init(); 691 bus_lock_init(); 692 693 intel_init_thermal(c); 694 } 695 696 #ifdef CONFIG_X86_32 697 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 698 { 699 /* 700 * Intel PIII Tualatin. This comes in two flavours. 701 * One has 256kb of cache, the other 512. We have no way 702 * to determine which, so we use a boottime override 703 * for the 512kb model, and assume 256 otherwise. 704 */ 705 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 706 size = 256; 707 708 /* 709 * Intel Quark SoC X1000 contains a 4-way set associative 710 * 16K cache with a 16 byte cache line and 256 lines per tag 711 */ 712 if ((c->x86 == 5) && (c->x86_model == 9)) 713 size = 16; 714 return size; 715 } 716 #endif 717 718 #define TLB_INST_4K 0x01 719 #define TLB_INST_4M 0x02 720 #define TLB_INST_2M_4M 0x03 721 722 #define TLB_INST_ALL 0x05 723 #define TLB_INST_1G 0x06 724 725 #define TLB_DATA_4K 0x11 726 #define TLB_DATA_4M 0x12 727 #define TLB_DATA_2M_4M 0x13 728 #define TLB_DATA_4K_4M 0x14 729 730 #define TLB_DATA_1G 0x16 731 732 #define TLB_DATA0_4K 0x21 733 #define TLB_DATA0_4M 0x22 734 #define TLB_DATA0_2M_4M 0x23 735 736 #define STLB_4K 0x41 737 #define STLB_4K_2M 0x42 738 739 static const struct _tlb_table intel_tlb_table[] = { 740 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 741 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 742 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 743 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 744 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 745 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 746 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" }, 747 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 748 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 749 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 750 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 751 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 752 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 753 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 754 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 755 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 756 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 757 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 758 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 759 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 760 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, 761 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, 762 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, 763 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 764 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 765 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 766 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 767 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 768 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 769 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 770 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 771 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 772 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 773 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 774 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" }, 775 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 776 { 0x00, 0, 0 } 777 }; 778 779 static void intel_tlb_lookup(const unsigned char desc) 780 { 781 unsigned char k; 782 if (desc == 0) 783 return; 784 785 /* look up this descriptor in the table */ 786 for (k = 0; intel_tlb_table[k].descriptor != desc && 787 intel_tlb_table[k].descriptor != 0; k++) 788 ; 789 790 if (intel_tlb_table[k].tlb_type == 0) 791 return; 792 793 switch (intel_tlb_table[k].tlb_type) { 794 case STLB_4K: 795 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 796 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 797 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 798 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 799 break; 800 case STLB_4K_2M: 801 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 802 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 803 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 804 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 805 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 806 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 807 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 808 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 809 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 810 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 811 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 812 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 813 break; 814 case TLB_INST_ALL: 815 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 816 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 817 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 818 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 819 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 820 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 821 break; 822 case TLB_INST_4K: 823 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 824 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 825 break; 826 case TLB_INST_4M: 827 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 828 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 829 break; 830 case TLB_INST_2M_4M: 831 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 832 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 833 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 834 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 835 break; 836 case TLB_DATA_4K: 837 case TLB_DATA0_4K: 838 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 839 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 840 break; 841 case TLB_DATA_4M: 842 case TLB_DATA0_4M: 843 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 844 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 845 break; 846 case TLB_DATA_2M_4M: 847 case TLB_DATA0_2M_4M: 848 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 849 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 850 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 851 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 852 break; 853 case TLB_DATA_4K_4M: 854 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 855 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 856 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 857 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 858 break; 859 case TLB_DATA_1G: 860 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 861 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 862 break; 863 } 864 } 865 866 static void intel_detect_tlb(struct cpuinfo_x86 *c) 867 { 868 int i, j, n; 869 unsigned int regs[4]; 870 unsigned char *desc = (unsigned char *)regs; 871 872 if (c->cpuid_level < 2) 873 return; 874 875 /* Number of times to iterate */ 876 n = cpuid_eax(2) & 0xFF; 877 878 for (i = 0 ; i < n ; i++) { 879 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 880 881 /* If bit 31 is set, this is an unknown format */ 882 for (j = 0 ; j < 3 ; j++) 883 if (regs[j] & (1 << 31)) 884 regs[j] = 0; 885 886 /* Byte 0 is level count, not a descriptor */ 887 for (j = 1 ; j < 16 ; j++) 888 intel_tlb_lookup(desc[j]); 889 } 890 } 891 892 static const struct cpu_dev intel_cpu_dev = { 893 .c_vendor = "Intel", 894 .c_ident = { "GenuineIntel" }, 895 #ifdef CONFIG_X86_32 896 .legacy_models = { 897 { .family = 4, .model_names = 898 { 899 [0] = "486 DX-25/33", 900 [1] = "486 DX-50", 901 [2] = "486 SX", 902 [3] = "486 DX/2", 903 [4] = "486 SL", 904 [5] = "486 SX/2", 905 [7] = "486 DX/2-WB", 906 [8] = "486 DX/4", 907 [9] = "486 DX/4-WB" 908 } 909 }, 910 { .family = 5, .model_names = 911 { 912 [0] = "Pentium 60/66 A-step", 913 [1] = "Pentium 60/66", 914 [2] = "Pentium 75 - 200", 915 [3] = "OverDrive PODP5V83", 916 [4] = "Pentium MMX", 917 [7] = "Mobile Pentium 75 - 200", 918 [8] = "Mobile Pentium MMX", 919 [9] = "Quark SoC X1000", 920 } 921 }, 922 { .family = 6, .model_names = 923 { 924 [0] = "Pentium Pro A-step", 925 [1] = "Pentium Pro", 926 [3] = "Pentium II (Klamath)", 927 [4] = "Pentium II (Deschutes)", 928 [5] = "Pentium II (Deschutes)", 929 [6] = "Mobile Pentium II", 930 [7] = "Pentium III (Katmai)", 931 [8] = "Pentium III (Coppermine)", 932 [10] = "Pentium III (Cascades)", 933 [11] = "Pentium III (Tualatin)", 934 } 935 }, 936 { .family = 15, .model_names = 937 { 938 [0] = "Pentium 4 (Unknown)", 939 [1] = "Pentium 4 (Willamette)", 940 [2] = "Pentium 4 (Northwood)", 941 [4] = "Pentium 4 (Foster)", 942 [5] = "Pentium 4 (Foster)", 943 } 944 }, 945 }, 946 .legacy_cache_size = intel_size_cache, 947 #endif 948 .c_detect_tlb = intel_detect_tlb, 949 .c_early_init = early_init_intel, 950 .c_bsp_init = bsp_init_intel, 951 .c_init = init_intel, 952 .c_x86_vendor = X86_VENDOR_INTEL, 953 }; 954 955 cpu_dev_register(intel_cpu_dev); 956 957 #undef pr_fmt 958 #define pr_fmt(fmt) "x86/split lock detection: " fmt 959 960 static const struct { 961 const char *option; 962 enum split_lock_detect_state state; 963 } sld_options[] __initconst = { 964 { "off", sld_off }, 965 { "warn", sld_warn }, 966 { "fatal", sld_fatal }, 967 { "ratelimit:", sld_ratelimit }, 968 }; 969 970 static struct ratelimit_state bld_ratelimit; 971 972 static unsigned int sysctl_sld_mitigate = 1; 973 static DEFINE_SEMAPHORE(buslock_sem, 1); 974 975 #ifdef CONFIG_PROC_SYSCTL 976 static struct ctl_table sld_sysctls[] = { 977 { 978 .procname = "split_lock_mitigate", 979 .data = &sysctl_sld_mitigate, 980 .maxlen = sizeof(unsigned int), 981 .mode = 0644, 982 .proc_handler = proc_douintvec_minmax, 983 .extra1 = SYSCTL_ZERO, 984 .extra2 = SYSCTL_ONE, 985 }, 986 }; 987 988 static int __init sld_mitigate_sysctl_init(void) 989 { 990 register_sysctl_init("kernel", sld_sysctls); 991 return 0; 992 } 993 994 late_initcall(sld_mitigate_sysctl_init); 995 #endif 996 997 static inline bool match_option(const char *arg, int arglen, const char *opt) 998 { 999 int len = strlen(opt), ratelimit; 1000 1001 if (strncmp(arg, opt, len)) 1002 return false; 1003 1004 /* 1005 * Min ratelimit is 1 bus lock/sec. 1006 * Max ratelimit is 1000 bus locks/sec. 1007 */ 1008 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 && 1009 ratelimit > 0 && ratelimit <= 1000) { 1010 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit); 1011 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE); 1012 return true; 1013 } 1014 1015 return len == arglen; 1016 } 1017 1018 static bool split_lock_verify_msr(bool on) 1019 { 1020 u64 ctrl, tmp; 1021 1022 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl)) 1023 return false; 1024 if (on) 1025 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 1026 else 1027 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 1028 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl)) 1029 return false; 1030 rdmsrl(MSR_TEST_CTRL, tmp); 1031 return ctrl == tmp; 1032 } 1033 1034 static void __init sld_state_setup(void) 1035 { 1036 enum split_lock_detect_state state = sld_warn; 1037 char arg[20]; 1038 int i, ret; 1039 1040 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) && 1041 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 1042 return; 1043 1044 ret = cmdline_find_option(boot_command_line, "split_lock_detect", 1045 arg, sizeof(arg)); 1046 if (ret >= 0) { 1047 for (i = 0; i < ARRAY_SIZE(sld_options); i++) { 1048 if (match_option(arg, ret, sld_options[i].option)) { 1049 state = sld_options[i].state; 1050 break; 1051 } 1052 } 1053 } 1054 sld_state = state; 1055 } 1056 1057 static void __init __split_lock_setup(void) 1058 { 1059 if (!split_lock_verify_msr(false)) { 1060 pr_info("MSR access failed: Disabled\n"); 1061 return; 1062 } 1063 1064 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); 1065 1066 if (!split_lock_verify_msr(true)) { 1067 pr_info("MSR access failed: Disabled\n"); 1068 return; 1069 } 1070 1071 /* Restore the MSR to its cached value. */ 1072 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); 1073 1074 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); 1075 } 1076 1077 /* 1078 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking 1079 * is not implemented as one thread could undo the setting of the other 1080 * thread immediately after dropping the lock anyway. 1081 */ 1082 static void sld_update_msr(bool on) 1083 { 1084 u64 test_ctrl_val = msr_test_ctrl_cache; 1085 1086 if (on) 1087 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 1088 1089 wrmsrl(MSR_TEST_CTRL, test_ctrl_val); 1090 } 1091 1092 static void split_lock_init(void) 1093 { 1094 /* 1095 * #DB for bus lock handles ratelimit and #AC for split lock is 1096 * disabled. 1097 */ 1098 if (sld_state == sld_ratelimit) { 1099 split_lock_verify_msr(false); 1100 return; 1101 } 1102 1103 if (cpu_model_supports_sld) 1104 split_lock_verify_msr(sld_state != sld_off); 1105 } 1106 1107 static void __split_lock_reenable_unlock(struct work_struct *work) 1108 { 1109 sld_update_msr(true); 1110 up(&buslock_sem); 1111 } 1112 1113 static DECLARE_DELAYED_WORK(sl_reenable_unlock, __split_lock_reenable_unlock); 1114 1115 static void __split_lock_reenable(struct work_struct *work) 1116 { 1117 sld_update_msr(true); 1118 } 1119 static DECLARE_DELAYED_WORK(sl_reenable, __split_lock_reenable); 1120 1121 /* 1122 * If a CPU goes offline with pending delayed work to re-enable split lock 1123 * detection then the delayed work will be executed on some other CPU. That 1124 * handles releasing the buslock_sem, but because it executes on a 1125 * different CPU probably won't re-enable split lock detection. This is a 1126 * problem on HT systems since the sibling CPU on the same core may then be 1127 * left running with split lock detection disabled. 1128 * 1129 * Unconditionally re-enable detection here. 1130 */ 1131 static int splitlock_cpu_offline(unsigned int cpu) 1132 { 1133 sld_update_msr(true); 1134 1135 return 0; 1136 } 1137 1138 static void split_lock_warn(unsigned long ip) 1139 { 1140 struct delayed_work *work; 1141 int cpu; 1142 1143 if (!current->reported_split_lock) 1144 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n", 1145 current->comm, current->pid, ip); 1146 current->reported_split_lock = 1; 1147 1148 if (sysctl_sld_mitigate) { 1149 /* 1150 * misery factor #1: 1151 * sleep 10ms before trying to execute split lock. 1152 */ 1153 if (msleep_interruptible(10) > 0) 1154 return; 1155 /* 1156 * Misery factor #2: 1157 * only allow one buslocked disabled core at a time. 1158 */ 1159 if (down_interruptible(&buslock_sem) == -EINTR) 1160 return; 1161 work = &sl_reenable_unlock; 1162 } else { 1163 work = &sl_reenable; 1164 } 1165 1166 cpu = get_cpu(); 1167 schedule_delayed_work_on(cpu, work, 2); 1168 1169 /* Disable split lock detection on this CPU to make progress */ 1170 sld_update_msr(false); 1171 put_cpu(); 1172 } 1173 1174 bool handle_guest_split_lock(unsigned long ip) 1175 { 1176 if (sld_state == sld_warn) { 1177 split_lock_warn(ip); 1178 return true; 1179 } 1180 1181 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n", 1182 current->comm, current->pid, 1183 sld_state == sld_fatal ? "fatal" : "bogus", ip); 1184 1185 current->thread.error_code = 0; 1186 current->thread.trap_nr = X86_TRAP_AC; 1187 force_sig_fault(SIGBUS, BUS_ADRALN, NULL); 1188 return false; 1189 } 1190 EXPORT_SYMBOL_GPL(handle_guest_split_lock); 1191 1192 static void bus_lock_init(void) 1193 { 1194 u64 val; 1195 1196 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 1197 return; 1198 1199 rdmsrl(MSR_IA32_DEBUGCTLMSR, val); 1200 1201 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) && 1202 (sld_state == sld_warn || sld_state == sld_fatal)) || 1203 sld_state == sld_off) { 1204 /* 1205 * Warn and fatal are handled by #AC for split lock if #AC for 1206 * split lock is supported. 1207 */ 1208 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT; 1209 } else { 1210 val |= DEBUGCTLMSR_BUS_LOCK_DETECT; 1211 } 1212 1213 wrmsrl(MSR_IA32_DEBUGCTLMSR, val); 1214 } 1215 1216 bool handle_user_split_lock(struct pt_regs *regs, long error_code) 1217 { 1218 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal) 1219 return false; 1220 split_lock_warn(regs->ip); 1221 return true; 1222 } 1223 1224 void handle_bus_lock(struct pt_regs *regs) 1225 { 1226 switch (sld_state) { 1227 case sld_off: 1228 break; 1229 case sld_ratelimit: 1230 /* Enforce no more than bld_ratelimit bus locks/sec. */ 1231 while (!__ratelimit(&bld_ratelimit)) 1232 msleep(20); 1233 /* Warn on the bus lock. */ 1234 fallthrough; 1235 case sld_warn: 1236 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n", 1237 current->comm, current->pid, regs->ip); 1238 break; 1239 case sld_fatal: 1240 force_sig_fault(SIGBUS, BUS_ADRALN, NULL); 1241 break; 1242 } 1243 } 1244 1245 /* 1246 * CPU models that are known to have the per-core split-lock detection 1247 * feature even though they do not enumerate IA32_CORE_CAPABILITIES. 1248 */ 1249 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = { 1250 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0), 1251 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0), 1252 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0), 1253 {} 1254 }; 1255 1256 static void __init split_lock_setup(struct cpuinfo_x86 *c) 1257 { 1258 const struct x86_cpu_id *m; 1259 u64 ia32_core_caps; 1260 1261 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1262 return; 1263 1264 /* Check for CPUs that have support but do not enumerate it: */ 1265 m = x86_match_cpu(split_lock_cpu_ids); 1266 if (m) 1267 goto supported; 1268 1269 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) 1270 return; 1271 1272 /* 1273 * Not all bits in MSR_IA32_CORE_CAPS are architectural, but 1274 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set 1275 * it have split lock detection. 1276 */ 1277 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps); 1278 if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT) 1279 goto supported; 1280 1281 /* CPU is not in the model list and does not have the MSR bit: */ 1282 return; 1283 1284 supported: 1285 cpu_model_supports_sld = true; 1286 __split_lock_setup(); 1287 } 1288 1289 static void sld_state_show(void) 1290 { 1291 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) && 1292 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 1293 return; 1294 1295 switch (sld_state) { 1296 case sld_off: 1297 pr_info("disabled\n"); 1298 break; 1299 case sld_warn: 1300 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { 1301 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n"); 1302 if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 1303 "x86/splitlock", NULL, splitlock_cpu_offline) < 0) 1304 pr_warn("No splitlock CPU offline handler\n"); 1305 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) { 1306 pr_info("#DB: warning on user-space bus_locks\n"); 1307 } 1308 break; 1309 case sld_fatal: 1310 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { 1311 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n"); 1312 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) { 1313 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n", 1314 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ? 1315 " from non-WB" : ""); 1316 } 1317 break; 1318 case sld_ratelimit: 1319 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 1320 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst); 1321 break; 1322 } 1323 } 1324 1325 void __init sld_setup(struct cpuinfo_x86 *c) 1326 { 1327 split_lock_setup(c); 1328 sld_state_setup(); 1329 sld_state_show(); 1330 } 1331 1332 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 1333 1334 /** 1335 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU 1336 * 1337 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in 1338 * a hybrid processor. If the processor is not hybrid, returns 0. 1339 */ 1340 u8 get_this_hybrid_cpu_type(void) 1341 { 1342 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1343 return 0; 1344 1345 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; 1346 } 1347