1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/bitops.h> 4 #include <linux/init.h> 5 #include <linux/kernel.h> 6 #include <linux/minmax.h> 7 #include <linux/smp.h> 8 #include <linux/string.h> 9 10 #ifdef CONFIG_X86_64 11 #include <linux/topology.h> 12 #endif 13 14 #include <asm/bugs.h> 15 #include <asm/cpu_device_id.h> 16 #include <asm/cpufeature.h> 17 #include <asm/cpu.h> 18 #include <asm/hwcap2.h> 19 #include <asm/intel-family.h> 20 #include <asm/microcode.h> 21 #include <asm/msr.h> 22 #include <asm/numa.h> 23 #include <asm/resctrl.h> 24 #include <asm/thermal.h> 25 #include <asm/uaccess.h> 26 27 #include "cpu.h" 28 29 /* 30 * Processors which have self-snooping capability can handle conflicting 31 * memory type across CPUs by snooping its own cache. However, there exists 32 * CPU models in which having conflicting memory types still leads to 33 * unpredictable behavior, machine check errors, or hangs. Clear this 34 * feature to prevent its use on machines with known erratas. 35 */ 36 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) 37 { 38 switch (c->x86_vfm) { 39 case INTEL_CORE_YONAH: 40 case INTEL_CORE2_MEROM: 41 case INTEL_CORE2_MEROM_L: 42 case INTEL_CORE2_PENRYN: 43 case INTEL_CORE2_DUNNINGTON: 44 case INTEL_NEHALEM: 45 case INTEL_NEHALEM_G: 46 case INTEL_NEHALEM_EP: 47 case INTEL_NEHALEM_EX: 48 case INTEL_WESTMERE: 49 case INTEL_WESTMERE_EP: 50 case INTEL_SANDYBRIDGE: 51 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); 52 } 53 } 54 55 static bool ring3mwait_disabled __read_mostly; 56 57 static int __init ring3mwait_disable(char *__unused) 58 { 59 ring3mwait_disabled = true; 60 return 1; 61 } 62 __setup("ring3mwait=disable", ring3mwait_disable); 63 64 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 65 { 66 /* 67 * Ring 3 MONITOR/MWAIT feature cannot be detected without 68 * cpu model and family comparison. 69 */ 70 if (c->x86 != 6) 71 return; 72 switch (c->x86_vfm) { 73 case INTEL_XEON_PHI_KNL: 74 case INTEL_XEON_PHI_KNM: 75 break; 76 default: 77 return; 78 } 79 80 if (ring3mwait_disabled) 81 return; 82 83 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 84 this_cpu_or(msr_misc_features_shadow, 85 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 86 87 if (c == &boot_cpu_data) 88 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 89 } 90 91 /* 92 * Early microcode releases for the Spectre v2 mitigation were broken. 93 * Information taken from; 94 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 95 * - https://kb.vmware.com/s/article/52345 96 * - Microcode revisions observed in the wild 97 * - Release note from 20180108 microcode release 98 */ 99 struct sku_microcode { 100 u32 vfm; 101 u8 stepping; 102 u32 microcode; 103 }; 104 static const struct sku_microcode spectre_bad_microcodes[] = { 105 { INTEL_KABYLAKE, 0x0B, 0x80 }, 106 { INTEL_KABYLAKE, 0x0A, 0x80 }, 107 { INTEL_KABYLAKE, 0x09, 0x80 }, 108 { INTEL_KABYLAKE_L, 0x0A, 0x80 }, 109 { INTEL_KABYLAKE_L, 0x09, 0x80 }, 110 { INTEL_SKYLAKE_X, 0x03, 0x0100013e }, 111 { INTEL_SKYLAKE_X, 0x04, 0x0200003c }, 112 { INTEL_BROADWELL, 0x04, 0x28 }, 113 { INTEL_BROADWELL_G, 0x01, 0x1b }, 114 { INTEL_BROADWELL_D, 0x02, 0x14 }, 115 { INTEL_BROADWELL_D, 0x03, 0x07000011 }, 116 { INTEL_BROADWELL_X, 0x01, 0x0b000025 }, 117 { INTEL_HASWELL_L, 0x01, 0x21 }, 118 { INTEL_HASWELL_G, 0x01, 0x18 }, 119 { INTEL_HASWELL, 0x03, 0x23 }, 120 { INTEL_HASWELL_X, 0x02, 0x3b }, 121 { INTEL_HASWELL_X, 0x04, 0x10 }, 122 { INTEL_IVYBRIDGE_X, 0x04, 0x42a }, 123 /* Observed in the wild */ 124 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b }, 125 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 }, 126 }; 127 128 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 129 { 130 int i; 131 132 /* 133 * We know that the hypervisor lie to us on the microcode version so 134 * we may as well hope that it is running the correct version. 135 */ 136 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 137 return false; 138 139 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 140 if (c->x86_vfm == spectre_bad_microcodes[i].vfm && 141 c->x86_stepping == spectre_bad_microcodes[i].stepping) 142 return (c->microcode <= spectre_bad_microcodes[i].microcode); 143 } 144 return false; 145 } 146 147 #define MSR_IA32_TME_ACTIVATE 0x982 148 149 /* Helpers to access TME_ACTIVATE MSR */ 150 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 151 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 152 153 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 154 155 static void detect_tme_early(struct cpuinfo_x86 *c) 156 { 157 u64 tme_activate; 158 int keyid_bits; 159 160 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); 161 162 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 163 pr_info_once("x86/tme: not enabled by BIOS\n"); 164 clear_cpu_cap(c, X86_FEATURE_TME); 165 return; 166 } 167 pr_info_once("x86/tme: enabled by BIOS\n"); 168 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 169 if (!keyid_bits) 170 return; 171 172 /* 173 * KeyID bits are set by BIOS and can be present regardless 174 * of whether the kernel is using them. They effectively lower 175 * the number of physical address bits. 176 * 177 * Update cpuinfo_x86::x86_phys_bits accordingly. 178 */ 179 c->x86_phys_bits -= keyid_bits; 180 pr_info_once("x86/mktme: BIOS enabled: x86_phys_bits reduced by %d\n", 181 keyid_bits); 182 } 183 184 void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) 185 { 186 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 187 return; 188 189 if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd)) 190 return; 191 192 /* 193 * The BIOS can have limited CPUID to leaf 2, which breaks feature 194 * enumeration. Unlock it and update the maximum leaf info. 195 */ 196 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) 197 c->cpuid_level = cpuid_eax(0); 198 } 199 200 static void early_init_intel(struct cpuinfo_x86 *c) 201 { 202 u64 misc_enable; 203 204 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 205 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 206 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 207 208 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 209 c->microcode = intel_get_microcode_revision(); 210 211 /* Now if any of them are set, check the blacklist and clear the lot */ 212 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 213 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 214 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 215 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 216 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 217 setup_clear_cpu_cap(X86_FEATURE_IBRS); 218 setup_clear_cpu_cap(X86_FEATURE_IBPB); 219 setup_clear_cpu_cap(X86_FEATURE_STIBP); 220 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 221 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 222 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 223 setup_clear_cpu_cap(X86_FEATURE_SSBD); 224 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 225 } 226 227 /* 228 * Atom erratum AAE44/AAF40/AAG38/AAH41: 229 * 230 * A race condition between speculative fetches and invalidating 231 * a large page. This is worked around in microcode, but we 232 * need the microcode to have already been loaded... so if it is 233 * not, recommend a BIOS update and disable large pages. 234 */ 235 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && 236 c->microcode < 0x20e) { 237 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 238 clear_cpu_cap(c, X86_FEATURE_PSE); 239 } 240 241 #ifdef CONFIG_X86_64 242 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 243 #else 244 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 245 if (c->x86 == 15 && c->x86_cache_alignment == 64) 246 c->x86_cache_alignment = 128; 247 #endif 248 249 /* CPUID workaround for 0F33/0F34 CPU */ 250 if (c->x86 == 0xF && c->x86_model == 0x3 251 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 252 c->x86_phys_bits = 36; 253 254 /* 255 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 256 * with P/T states and does not stop in deep C-states. 257 * 258 * It is also reliable across cores and sockets. (but not across 259 * cabinets - we turn it off in that case explicitly.) 260 */ 261 if (c->x86_power & (1 << 8)) { 262 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 263 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 264 } 265 266 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 267 switch (c->x86_vfm) { 268 case INTEL_ATOM_SALTWELL_MID: 269 case INTEL_ATOM_SALTWELL_TABLET: 270 case INTEL_ATOM_SILVERMONT_MID: 271 case INTEL_ATOM_AIRMONT_NP: 272 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 273 break; 274 } 275 276 /* 277 * PAT is broken on early family 6 CPUs, the last of which 278 * is "Yonah" where the erratum is named "AN7": 279 * 280 * Page with PAT (Page Attribute Table) Set to USWC 281 * (Uncacheable Speculative Write Combine) While 282 * Associated MTRR (Memory Type Range Register) Is UC 283 * (Uncacheable) May Consolidate to UC 284 * 285 * Disable PAT and fall back to MTRR on these CPUs. 286 */ 287 if (c->x86_vfm >= INTEL_PENTIUM_PRO && 288 c->x86_vfm <= INTEL_CORE_YONAH) 289 clear_cpu_cap(c, X86_FEATURE_PAT); 290 291 /* 292 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 293 * clear the fast string and enhanced fast string CPU capabilities. 294 */ 295 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 296 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 297 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 298 pr_info("Disabled fast string operations\n"); 299 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 300 setup_clear_cpu_cap(X86_FEATURE_ERMS); 301 } 302 } 303 304 /* 305 * Intel Quark Core DevMan_001.pdf section 6.4.11 306 * "The operating system also is required to invalidate (i.e., flush) 307 * the TLB when any changes are made to any of the page table entries. 308 * The operating system must reload CR3 to cause the TLB to be flushed" 309 * 310 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 311 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE 312 * to be modified. 313 */ 314 if (c->x86_vfm == INTEL_QUARK_X1000) { 315 pr_info("Disabling PGE capability bit\n"); 316 setup_clear_cpu_cap(X86_FEATURE_PGE); 317 } 318 319 check_memory_type_self_snoop_errata(c); 320 321 /* 322 * Adjust the number of physical bits early because it affects the 323 * valid bits of the MTRR mask registers. 324 */ 325 if (cpu_has(c, X86_FEATURE_TME)) 326 detect_tme_early(c); 327 } 328 329 static void bsp_init_intel(struct cpuinfo_x86 *c) 330 { 331 resctrl_cpu_detect(c); 332 } 333 334 #ifdef CONFIG_X86_32 335 /* 336 * Early probe support logic for ppro memory erratum #50 337 * 338 * This is called before we do cpu ident work 339 */ 340 341 int ppro_with_ram_bug(void) 342 { 343 /* Uses data from early_cpu_detect now */ 344 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 345 boot_cpu_data.x86 == 6 && 346 boot_cpu_data.x86_model == 1 && 347 boot_cpu_data.x86_stepping < 8) { 348 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 349 return 1; 350 } 351 return 0; 352 } 353 354 static void intel_smp_check(struct cpuinfo_x86 *c) 355 { 356 /* calling is from identify_secondary_cpu() ? */ 357 if (!c->cpu_index) 358 return; 359 360 /* 361 * Mask B, Pentium, but not Pentium MMX 362 */ 363 if (c->x86 == 5 && 364 c->x86_stepping >= 1 && c->x86_stepping <= 4 && 365 c->x86_model <= 3) { 366 /* 367 * Remember we have B step Pentia with bugs 368 */ 369 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 370 "with B stepping processors.\n"); 371 } 372 } 373 374 static int forcepae; 375 static int __init forcepae_setup(char *__unused) 376 { 377 forcepae = 1; 378 return 1; 379 } 380 __setup("forcepae", forcepae_setup); 381 382 static void intel_workarounds(struct cpuinfo_x86 *c) 383 { 384 #ifdef CONFIG_X86_F00F_BUG 385 /* 386 * All models of Pentium and Pentium with MMX technology CPUs 387 * have the F0 0F bug, which lets nonprivileged users lock up the 388 * system. Announce that the fault handler will be checking for it. 389 * The Quark is also family 5, but does not have the same bug. 390 */ 391 clear_cpu_bug(c, X86_BUG_F00F); 392 if (c->x86 == 5 && c->x86_model < 9) { 393 static int f00f_workaround_enabled; 394 395 set_cpu_bug(c, X86_BUG_F00F); 396 if (!f00f_workaround_enabled) { 397 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 398 f00f_workaround_enabled = 1; 399 } 400 } 401 #endif 402 403 /* 404 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 405 * model 3 mask 3 406 */ 407 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) 408 clear_cpu_cap(c, X86_FEATURE_SEP); 409 410 /* 411 * PAE CPUID issue: many Pentium M report no PAE but may have a 412 * functionally usable PAE implementation. 413 * Forcefully enable PAE if kernel parameter "forcepae" is present. 414 */ 415 if (forcepae) { 416 pr_warn("PAE forced!\n"); 417 set_cpu_cap(c, X86_FEATURE_PAE); 418 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 419 } 420 421 /* 422 * P4 Xeon erratum 037 workaround. 423 * Hardware prefetcher may cause stale data to be loaded into the cache. 424 */ 425 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { 426 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 427 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 428 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 429 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 430 } 431 } 432 433 /* 434 * See if we have a good local APIC by checking for buggy Pentia, 435 * i.e. all B steppings and the C2 stepping of P54C when using their 436 * integrated APIC (see 11AP erratum in "Pentium Processor 437 * Specification Update"). 438 */ 439 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 440 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 441 set_cpu_bug(c, X86_BUG_11AP); 442 443 444 #ifdef CONFIG_X86_INTEL_USERCOPY 445 /* 446 * Set up the preferred alignment for movsl bulk memory moves 447 */ 448 switch (c->x86) { 449 case 4: /* 486: untested */ 450 break; 451 case 5: /* Old Pentia: untested */ 452 break; 453 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 454 movsl_mask.mask = 7; 455 break; 456 case 15: /* P4 is OK down to 8-byte alignment */ 457 movsl_mask.mask = 7; 458 break; 459 } 460 #endif 461 462 intel_smp_check(c); 463 } 464 #else 465 static void intel_workarounds(struct cpuinfo_x86 *c) 466 { 467 } 468 #endif 469 470 static void srat_detect_node(struct cpuinfo_x86 *c) 471 { 472 #ifdef CONFIG_NUMA 473 unsigned node; 474 int cpu = smp_processor_id(); 475 476 /* Don't do the funky fallback heuristics the AMD version employs 477 for now. */ 478 node = numa_cpu_node(cpu); 479 if (node == NUMA_NO_NODE || !node_online(node)) { 480 /* reuse the value from init_cpu_to_node() */ 481 node = cpu_to_node(cpu); 482 } 483 numa_set_node(cpu, node); 484 #endif 485 } 486 487 static void init_cpuid_fault(struct cpuinfo_x86 *c) 488 { 489 u64 msr; 490 491 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 492 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 493 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 494 } 495 } 496 497 static void init_intel_misc_features(struct cpuinfo_x86 *c) 498 { 499 u64 msr; 500 501 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 502 return; 503 504 /* Clear all MISC features */ 505 this_cpu_write(msr_misc_features_shadow, 0); 506 507 /* Check features and update capabilities and shadow control bits */ 508 init_cpuid_fault(c); 509 probe_xeon_phi_r3mwait(c); 510 511 msr = this_cpu_read(msr_misc_features_shadow); 512 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 513 } 514 515 static void init_intel(struct cpuinfo_x86 *c) 516 { 517 early_init_intel(c); 518 519 intel_workarounds(c); 520 521 init_intel_cacheinfo(c); 522 523 if (c->cpuid_level > 9) { 524 unsigned eax = cpuid_eax(10); 525 /* Check for version and the number of counters */ 526 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 527 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 528 } 529 530 if (cpu_has(c, X86_FEATURE_XMM2)) 531 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 532 533 if (boot_cpu_has(X86_FEATURE_DS)) { 534 unsigned int l1, l2; 535 536 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 537 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) 538 set_cpu_cap(c, X86_FEATURE_BTS); 539 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) 540 set_cpu_cap(c, X86_FEATURE_PEBS); 541 } 542 543 if (boot_cpu_has(X86_FEATURE_CLFLUSH) && 544 (c->x86_vfm == INTEL_CORE2_DUNNINGTON || 545 c->x86_vfm == INTEL_NEHALEM_EX || 546 c->x86_vfm == INTEL_WESTMERE_EX)) 547 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 548 549 if (boot_cpu_has(X86_FEATURE_MWAIT) && 550 (c->x86_vfm == INTEL_ATOM_GOLDMONT || 551 c->x86_vfm == INTEL_LUNARLAKE_M)) 552 set_cpu_bug(c, X86_BUG_MONITOR); 553 554 #ifdef CONFIG_X86_64 555 if (c->x86 == 15) 556 c->x86_cache_alignment = c->x86_clflush_size * 2; 557 if (c->x86 == 6) 558 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 559 #else 560 /* 561 * Names for the Pentium II/Celeron processors 562 * detectable only by also checking the cache size. 563 * Dixon is NOT a Celeron. 564 */ 565 if (c->x86 == 6) { 566 unsigned int l2 = c->x86_cache_size; 567 char *p = NULL; 568 569 switch (c->x86_model) { 570 case 5: 571 if (l2 == 0) 572 p = "Celeron (Covington)"; 573 else if (l2 == 256) 574 p = "Mobile Pentium II (Dixon)"; 575 break; 576 577 case 6: 578 if (l2 == 128) 579 p = "Celeron (Mendocino)"; 580 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 581 p = "Celeron-A"; 582 break; 583 584 case 8: 585 if (l2 == 128) 586 p = "Celeron (Coppermine)"; 587 break; 588 } 589 590 if (p) 591 strcpy(c->x86_model_id, p); 592 } 593 #endif 594 595 /* Work around errata */ 596 srat_detect_node(c); 597 598 init_ia32_feat_ctl(c); 599 600 init_intel_misc_features(c); 601 602 split_lock_init(); 603 604 intel_init_thermal(c); 605 } 606 607 #ifdef CONFIG_X86_32 608 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 609 { 610 /* 611 * Intel PIII Tualatin. This comes in two flavours. 612 * One has 256kb of cache, the other 512. We have no way 613 * to determine which, so we use a boottime override 614 * for the 512kb model, and assume 256 otherwise. 615 */ 616 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 617 size = 256; 618 619 /* 620 * Intel Quark SoC X1000 contains a 4-way set associative 621 * 16K cache with a 16 byte cache line and 256 lines per tag 622 */ 623 if ((c->x86 == 5) && (c->x86_model == 9)) 624 size = 16; 625 return size; 626 } 627 #endif 628 629 #define TLB_INST_4K 0x01 630 #define TLB_INST_4M 0x02 631 #define TLB_INST_2M_4M 0x03 632 633 #define TLB_INST_ALL 0x05 634 #define TLB_INST_1G 0x06 635 636 #define TLB_DATA_4K 0x11 637 #define TLB_DATA_4M 0x12 638 #define TLB_DATA_2M_4M 0x13 639 #define TLB_DATA_4K_4M 0x14 640 641 #define TLB_DATA_1G 0x16 642 #define TLB_DATA_1G_2M_4M 0x17 643 644 #define TLB_DATA0_4K 0x21 645 #define TLB_DATA0_4M 0x22 646 #define TLB_DATA0_2M_4M 0x23 647 648 #define STLB_4K 0x41 649 #define STLB_4K_2M 0x42 650 651 /* 652 * All of leaf 0x2's one-byte TLB descriptors implies the same number of 653 * entries for their respective TLB types. The 0x63 descriptor is an 654 * exception: it implies 4 dTLB entries for 1GB pages 32 dTLB entries 655 * for 2MB or 4MB pages. Encode descriptor 0x63 dTLB entry count for 656 * 2MB/4MB pages here, as its count for dTLB 1GB pages is already at the 657 * intel_tlb_table[] mapping. 658 */ 659 #define TLB_0x63_2M_4M_ENTRIES 32 660 661 struct _tlb_table { 662 unsigned char descriptor; 663 char tlb_type; 664 unsigned int entries; 665 }; 666 667 static const struct _tlb_table intel_tlb_table[] = { 668 { 0x01, TLB_INST_4K, 32}, /* TLB_INST 4 KByte pages, 4-way set associative */ 669 { 0x02, TLB_INST_4M, 2}, /* TLB_INST 4 MByte pages, full associative */ 670 { 0x03, TLB_DATA_4K, 64}, /* TLB_DATA 4 KByte pages, 4-way set associative */ 671 { 0x04, TLB_DATA_4M, 8}, /* TLB_DATA 4 MByte pages, 4-way set associative */ 672 { 0x05, TLB_DATA_4M, 32}, /* TLB_DATA 4 MByte pages, 4-way set associative */ 673 { 0x0b, TLB_INST_4M, 4}, /* TLB_INST 4 MByte pages, 4-way set associative */ 674 { 0x4f, TLB_INST_4K, 32}, /* TLB_INST 4 KByte pages */ 675 { 0x50, TLB_INST_ALL, 64}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */ 676 { 0x51, TLB_INST_ALL, 128}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */ 677 { 0x52, TLB_INST_ALL, 256}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */ 678 { 0x55, TLB_INST_2M_4M, 7}, /* TLB_INST 2-MByte or 4-MByte pages, fully associative */ 679 { 0x56, TLB_DATA0_4M, 16}, /* TLB_DATA0 4 MByte pages, 4-way set associative */ 680 { 0x57, TLB_DATA0_4K, 16}, /* TLB_DATA0 4 KByte pages, 4-way associative */ 681 { 0x59, TLB_DATA0_4K, 16}, /* TLB_DATA0 4 KByte pages, fully associative */ 682 { 0x5a, TLB_DATA0_2M_4M, 32}, /* TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative */ 683 { 0x5b, TLB_DATA_4K_4M, 64}, /* TLB_DATA 4 KByte and 4 MByte pages */ 684 { 0x5c, TLB_DATA_4K_4M, 128}, /* TLB_DATA 4 KByte and 4 MByte pages */ 685 { 0x5d, TLB_DATA_4K_4M, 256}, /* TLB_DATA 4 KByte and 4 MByte pages */ 686 { 0x61, TLB_INST_4K, 48}, /* TLB_INST 4 KByte pages, full associative */ 687 { 0x63, TLB_DATA_1G_2M_4M, 4}, /* TLB_DATA 1 GByte pages, 4-way set associative 688 * (plus 32 entries TLB_DATA 2 MByte or 4 MByte pages, not encoded here) */ 689 { 0x6b, TLB_DATA_4K, 256}, /* TLB_DATA 4 KByte pages, 8-way associative */ 690 { 0x6c, TLB_DATA_2M_4M, 128}, /* TLB_DATA 2 MByte or 4 MByte pages, 8-way associative */ 691 { 0x6d, TLB_DATA_1G, 16}, /* TLB_DATA 1 GByte pages, fully associative */ 692 { 0x76, TLB_INST_2M_4M, 8}, /* TLB_INST 2-MByte or 4-MByte pages, fully associative */ 693 { 0xb0, TLB_INST_4K, 128}, /* TLB_INST 4 KByte pages, 4-way set associative */ 694 { 0xb1, TLB_INST_2M_4M, 4}, /* TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries */ 695 { 0xb2, TLB_INST_4K, 64}, /* TLB_INST 4KByte pages, 4-way set associative */ 696 { 0xb3, TLB_DATA_4K, 128}, /* TLB_DATA 4 KByte pages, 4-way set associative */ 697 { 0xb4, TLB_DATA_4K, 256}, /* TLB_DATA 4 KByte pages, 4-way associative */ 698 { 0xb5, TLB_INST_4K, 64}, /* TLB_INST 4 KByte pages, 8-way set associative */ 699 { 0xb6, TLB_INST_4K, 128}, /* TLB_INST 4 KByte pages, 8-way set associative */ 700 { 0xba, TLB_DATA_4K, 64}, /* TLB_DATA 4 KByte pages, 4-way associative */ 701 { 0xc0, TLB_DATA_4K_4M, 8}, /* TLB_DATA 4 KByte and 4 MByte pages, 4-way associative */ 702 { 0xc1, STLB_4K_2M, 1024}, /* STLB 4 KByte and 2 MByte pages, 8-way associative */ 703 { 0xc2, TLB_DATA_2M_4M, 16}, /* TLB_DATA 2 MByte/4MByte pages, 4-way associative */ 704 { 0xca, STLB_4K, 512}, /* STLB 4 KByte pages, 4-way associative */ 705 { 0x00, 0, 0 } 706 }; 707 708 static void intel_tlb_lookup(const unsigned char desc) 709 { 710 unsigned int entries; 711 unsigned char k; 712 713 if (desc == 0) 714 return; 715 716 /* look up this descriptor in the table */ 717 for (k = 0; intel_tlb_table[k].descriptor != desc && 718 intel_tlb_table[k].descriptor != 0; k++) 719 ; 720 721 if (intel_tlb_table[k].tlb_type == 0) 722 return; 723 724 entries = intel_tlb_table[k].entries; 725 switch (intel_tlb_table[k].tlb_type) { 726 case STLB_4K: 727 tlb_lli_4k = max(tlb_lli_4k, entries); 728 tlb_lld_4k = max(tlb_lld_4k, entries); 729 break; 730 case STLB_4K_2M: 731 tlb_lli_4k = max(tlb_lli_4k, entries); 732 tlb_lld_4k = max(tlb_lld_4k, entries); 733 tlb_lli_2m = max(tlb_lli_2m, entries); 734 tlb_lld_2m = max(tlb_lld_2m, entries); 735 tlb_lli_4m = max(tlb_lli_4m, entries); 736 tlb_lld_4m = max(tlb_lld_4m, entries); 737 break; 738 case TLB_INST_ALL: 739 tlb_lli_4k = max(tlb_lli_4k, entries); 740 tlb_lli_2m = max(tlb_lli_2m, entries); 741 tlb_lli_4m = max(tlb_lli_4m, entries); 742 break; 743 case TLB_INST_4K: 744 tlb_lli_4k = max(tlb_lli_4k, entries); 745 break; 746 case TLB_INST_4M: 747 tlb_lli_4m = max(tlb_lli_4m, entries); 748 break; 749 case TLB_INST_2M_4M: 750 tlb_lli_2m = max(tlb_lli_2m, entries); 751 tlb_lli_4m = max(tlb_lli_4m, entries); 752 break; 753 case TLB_DATA_4K: 754 case TLB_DATA0_4K: 755 tlb_lld_4k = max(tlb_lld_4k, entries); 756 break; 757 case TLB_DATA_4M: 758 case TLB_DATA0_4M: 759 tlb_lld_4m = max(tlb_lld_4m, entries); 760 break; 761 case TLB_DATA_2M_4M: 762 case TLB_DATA0_2M_4M: 763 tlb_lld_2m = max(tlb_lld_2m, entries); 764 tlb_lld_4m = max(tlb_lld_4m, entries); 765 break; 766 case TLB_DATA_4K_4M: 767 tlb_lld_4k = max(tlb_lld_4k, entries); 768 tlb_lld_4m = max(tlb_lld_4m, entries); 769 break; 770 case TLB_DATA_1G_2M_4M: 771 tlb_lld_2m = max(tlb_lld_2m, TLB_0x63_2M_4M_ENTRIES); 772 tlb_lld_4m = max(tlb_lld_4m, TLB_0x63_2M_4M_ENTRIES); 773 fallthrough; 774 case TLB_DATA_1G: 775 tlb_lld_1g = max(tlb_lld_1g, entries); 776 break; 777 } 778 } 779 780 static void intel_detect_tlb(struct cpuinfo_x86 *c) 781 { 782 int i, j, n; 783 unsigned int regs[4]; 784 unsigned char *desc = (unsigned char *)regs; 785 786 if (c->cpuid_level < 2) 787 return; 788 789 /* Number of times to iterate */ 790 n = cpuid_eax(2) & 0xFF; 791 792 for (i = 0 ; i < n ; i++) { 793 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 794 795 /* If bit 31 is set, this is an unknown format */ 796 for (j = 0 ; j < 4 ; j++) 797 if (regs[j] & (1 << 31)) 798 regs[j] = 0; 799 800 /* Byte 0 is level count, not a descriptor */ 801 for (j = 1 ; j < 16 ; j++) 802 intel_tlb_lookup(desc[j]); 803 } 804 } 805 806 static const struct cpu_dev intel_cpu_dev = { 807 .c_vendor = "Intel", 808 .c_ident = { "GenuineIntel" }, 809 #ifdef CONFIG_X86_32 810 .legacy_models = { 811 { .family = 4, .model_names = 812 { 813 [0] = "486 DX-25/33", 814 [1] = "486 DX-50", 815 [2] = "486 SX", 816 [3] = "486 DX/2", 817 [4] = "486 SL", 818 [5] = "486 SX/2", 819 [7] = "486 DX/2-WB", 820 [8] = "486 DX/4", 821 [9] = "486 DX/4-WB" 822 } 823 }, 824 { .family = 5, .model_names = 825 { 826 [0] = "Pentium 60/66 A-step", 827 [1] = "Pentium 60/66", 828 [2] = "Pentium 75 - 200", 829 [3] = "OverDrive PODP5V83", 830 [4] = "Pentium MMX", 831 [7] = "Mobile Pentium 75 - 200", 832 [8] = "Mobile Pentium MMX", 833 [9] = "Quark SoC X1000", 834 } 835 }, 836 { .family = 6, .model_names = 837 { 838 [0] = "Pentium Pro A-step", 839 [1] = "Pentium Pro", 840 [3] = "Pentium II (Klamath)", 841 [4] = "Pentium II (Deschutes)", 842 [5] = "Pentium II (Deschutes)", 843 [6] = "Mobile Pentium II", 844 [7] = "Pentium III (Katmai)", 845 [8] = "Pentium III (Coppermine)", 846 [10] = "Pentium III (Cascades)", 847 [11] = "Pentium III (Tualatin)", 848 } 849 }, 850 { .family = 15, .model_names = 851 { 852 [0] = "Pentium 4 (Unknown)", 853 [1] = "Pentium 4 (Willamette)", 854 [2] = "Pentium 4 (Northwood)", 855 [4] = "Pentium 4 (Foster)", 856 [5] = "Pentium 4 (Foster)", 857 } 858 }, 859 }, 860 .legacy_cache_size = intel_size_cache, 861 #endif 862 .c_detect_tlb = intel_detect_tlb, 863 .c_early_init = early_init_intel, 864 .c_bsp_init = bsp_init_intel, 865 .c_init = init_intel, 866 .c_x86_vendor = X86_VENDOR_INTEL, 867 }; 868 869 cpu_dev_register(intel_cpu_dev); 870