1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 #include <linux/pgtable.h> 4 5 #include <linux/string.h> 6 #include <linux/bitops.h> 7 #include <linux/smp.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/thread_info.h> 11 #include <linux/init.h> 12 #include <linux/uaccess.h> 13 14 #include <asm/cpufeature.h> 15 #include <asm/msr.h> 16 #include <asm/bugs.h> 17 #include <asm/cpu.h> 18 #include <asm/intel-family.h> 19 #include <asm/microcode.h> 20 #include <asm/hwcap2.h> 21 #include <asm/elf.h> 22 #include <asm/cpu_device_id.h> 23 #include <asm/resctrl.h> 24 #include <asm/numa.h> 25 #include <asm/thermal.h> 26 27 #ifdef CONFIG_X86_64 28 #include <linux/topology.h> 29 #endif 30 31 #include "cpu.h" 32 33 #ifdef CONFIG_X86_LOCAL_APIC 34 #include <asm/mpspec.h> 35 #include <asm/apic.h> 36 #endif 37 38 /* 39 * Processors which have self-snooping capability can handle conflicting 40 * memory type across CPUs by snooping its own cache. However, there exists 41 * CPU models in which having conflicting memory types still leads to 42 * unpredictable behavior, machine check errors, or hangs. Clear this 43 * feature to prevent its use on machines with known erratas. 44 */ 45 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) 46 { 47 switch (c->x86_vfm) { 48 case INTEL_CORE_YONAH: 49 case INTEL_CORE2_MEROM: 50 case INTEL_CORE2_MEROM_L: 51 case INTEL_CORE2_PENRYN: 52 case INTEL_CORE2_DUNNINGTON: 53 case INTEL_NEHALEM: 54 case INTEL_NEHALEM_G: 55 case INTEL_NEHALEM_EP: 56 case INTEL_NEHALEM_EX: 57 case INTEL_WESTMERE: 58 case INTEL_WESTMERE_EP: 59 case INTEL_SANDYBRIDGE: 60 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); 61 } 62 } 63 64 static bool ring3mwait_disabled __read_mostly; 65 66 static int __init ring3mwait_disable(char *__unused) 67 { 68 ring3mwait_disabled = true; 69 return 1; 70 } 71 __setup("ring3mwait=disable", ring3mwait_disable); 72 73 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 74 { 75 /* 76 * Ring 3 MONITOR/MWAIT feature cannot be detected without 77 * cpu model and family comparison. 78 */ 79 if (c->x86 != 6) 80 return; 81 switch (c->x86_vfm) { 82 case INTEL_XEON_PHI_KNL: 83 case INTEL_XEON_PHI_KNM: 84 break; 85 default: 86 return; 87 } 88 89 if (ring3mwait_disabled) 90 return; 91 92 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 93 this_cpu_or(msr_misc_features_shadow, 94 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 95 96 if (c == &boot_cpu_data) 97 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 98 } 99 100 /* 101 * Early microcode releases for the Spectre v2 mitigation were broken. 102 * Information taken from; 103 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 104 * - https://kb.vmware.com/s/article/52345 105 * - Microcode revisions observed in the wild 106 * - Release note from 20180108 microcode release 107 */ 108 struct sku_microcode { 109 u32 vfm; 110 u8 stepping; 111 u32 microcode; 112 }; 113 static const struct sku_microcode spectre_bad_microcodes[] = { 114 { INTEL_KABYLAKE, 0x0B, 0x80 }, 115 { INTEL_KABYLAKE, 0x0A, 0x80 }, 116 { INTEL_KABYLAKE, 0x09, 0x80 }, 117 { INTEL_KABYLAKE_L, 0x0A, 0x80 }, 118 { INTEL_KABYLAKE_L, 0x09, 0x80 }, 119 { INTEL_SKYLAKE_X, 0x03, 0x0100013e }, 120 { INTEL_SKYLAKE_X, 0x04, 0x0200003c }, 121 { INTEL_BROADWELL, 0x04, 0x28 }, 122 { INTEL_BROADWELL_G, 0x01, 0x1b }, 123 { INTEL_BROADWELL_D, 0x02, 0x14 }, 124 { INTEL_BROADWELL_D, 0x03, 0x07000011 }, 125 { INTEL_BROADWELL_X, 0x01, 0x0b000025 }, 126 { INTEL_HASWELL_L, 0x01, 0x21 }, 127 { INTEL_HASWELL_G, 0x01, 0x18 }, 128 { INTEL_HASWELL, 0x03, 0x23 }, 129 { INTEL_HASWELL_X, 0x02, 0x3b }, 130 { INTEL_HASWELL_X, 0x04, 0x10 }, 131 { INTEL_IVYBRIDGE_X, 0x04, 0x42a }, 132 /* Observed in the wild */ 133 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b }, 134 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 }, 135 }; 136 137 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 138 { 139 int i; 140 141 /* 142 * We know that the hypervisor lie to us on the microcode version so 143 * we may as well hope that it is running the correct version. 144 */ 145 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 146 return false; 147 148 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 149 if (c->x86_vfm == spectre_bad_microcodes[i].vfm && 150 c->x86_stepping == spectre_bad_microcodes[i].stepping) 151 return (c->microcode <= spectre_bad_microcodes[i].microcode); 152 } 153 return false; 154 } 155 156 #define MSR_IA32_TME_ACTIVATE 0x982 157 158 /* Helpers to access TME_ACTIVATE MSR */ 159 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 160 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 161 162 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 163 164 static void detect_tme_early(struct cpuinfo_x86 *c) 165 { 166 u64 tme_activate; 167 int keyid_bits; 168 169 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); 170 171 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 172 pr_info_once("x86/tme: not enabled by BIOS\n"); 173 clear_cpu_cap(c, X86_FEATURE_TME); 174 return; 175 } 176 pr_info_once("x86/tme: enabled by BIOS\n"); 177 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 178 if (!keyid_bits) 179 return; 180 181 /* 182 * KeyID bits are set by BIOS and can be present regardless 183 * of whether the kernel is using them. They effectively lower 184 * the number of physical address bits. 185 * 186 * Update cpuinfo_x86::x86_phys_bits accordingly. 187 */ 188 c->x86_phys_bits -= keyid_bits; 189 pr_info_once("x86/mktme: BIOS enabled: x86_phys_bits reduced by %d\n", 190 keyid_bits); 191 } 192 193 void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) 194 { 195 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 196 return; 197 198 if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd)) 199 return; 200 201 /* 202 * The BIOS can have limited CPUID to leaf 2, which breaks feature 203 * enumeration. Unlock it and update the maximum leaf info. 204 */ 205 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) 206 c->cpuid_level = cpuid_eax(0); 207 } 208 209 static void early_init_intel(struct cpuinfo_x86 *c) 210 { 211 u64 misc_enable; 212 213 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 214 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 215 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 216 217 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 218 c->microcode = intel_get_microcode_revision(); 219 220 /* Now if any of them are set, check the blacklist and clear the lot */ 221 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 222 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 223 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 224 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 225 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 226 setup_clear_cpu_cap(X86_FEATURE_IBRS); 227 setup_clear_cpu_cap(X86_FEATURE_IBPB); 228 setup_clear_cpu_cap(X86_FEATURE_STIBP); 229 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 230 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 231 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 232 setup_clear_cpu_cap(X86_FEATURE_SSBD); 233 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 234 } 235 236 /* 237 * Atom erratum AAE44/AAF40/AAG38/AAH41: 238 * 239 * A race condition between speculative fetches and invalidating 240 * a large page. This is worked around in microcode, but we 241 * need the microcode to have already been loaded... so if it is 242 * not, recommend a BIOS update and disable large pages. 243 */ 244 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && 245 c->microcode < 0x20e) { 246 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 247 clear_cpu_cap(c, X86_FEATURE_PSE); 248 } 249 250 #ifdef CONFIG_X86_64 251 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 252 #else 253 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 254 if (c->x86 == 15 && c->x86_cache_alignment == 64) 255 c->x86_cache_alignment = 128; 256 #endif 257 258 /* CPUID workaround for 0F33/0F34 CPU */ 259 if (c->x86 == 0xF && c->x86_model == 0x3 260 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 261 c->x86_phys_bits = 36; 262 263 /* 264 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 265 * with P/T states and does not stop in deep C-states. 266 * 267 * It is also reliable across cores and sockets. (but not across 268 * cabinets - we turn it off in that case explicitly.) 269 */ 270 if (c->x86_power & (1 << 8)) { 271 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 272 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 273 } 274 275 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 276 switch (c->x86_vfm) { 277 case INTEL_ATOM_SALTWELL_MID: 278 case INTEL_ATOM_SALTWELL_TABLET: 279 case INTEL_ATOM_SILVERMONT_MID: 280 case INTEL_ATOM_AIRMONT_NP: 281 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 282 break; 283 } 284 285 /* 286 * PAT is broken on early family 6 CPUs, the last of which 287 * is "Yonah" where the erratum is named "AN7": 288 * 289 * Page with PAT (Page Attribute Table) Set to USWC 290 * (Uncacheable Speculative Write Combine) While 291 * Associated MTRR (Memory Type Range Register) Is UC 292 * (Uncacheable) May Consolidate to UC 293 * 294 * Disable PAT and fall back to MTRR on these CPUs. 295 */ 296 if (c->x86_vfm >= INTEL_PENTIUM_PRO && 297 c->x86_vfm <= INTEL_CORE_YONAH) 298 clear_cpu_cap(c, X86_FEATURE_PAT); 299 300 /* 301 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 302 * clear the fast string and enhanced fast string CPU capabilities. 303 */ 304 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 305 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 306 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 307 pr_info("Disabled fast string operations\n"); 308 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 309 setup_clear_cpu_cap(X86_FEATURE_ERMS); 310 } 311 } 312 313 /* 314 * Intel Quark Core DevMan_001.pdf section 6.4.11 315 * "The operating system also is required to invalidate (i.e., flush) 316 * the TLB when any changes are made to any of the page table entries. 317 * The operating system must reload CR3 to cause the TLB to be flushed" 318 * 319 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 320 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE 321 * to be modified. 322 */ 323 if (c->x86_vfm == INTEL_QUARK_X1000) { 324 pr_info("Disabling PGE capability bit\n"); 325 setup_clear_cpu_cap(X86_FEATURE_PGE); 326 } 327 328 check_memory_type_self_snoop_errata(c); 329 330 /* 331 * Adjust the number of physical bits early because it affects the 332 * valid bits of the MTRR mask registers. 333 */ 334 if (cpu_has(c, X86_FEATURE_TME)) 335 detect_tme_early(c); 336 } 337 338 static void bsp_init_intel(struct cpuinfo_x86 *c) 339 { 340 resctrl_cpu_detect(c); 341 } 342 343 #ifdef CONFIG_X86_32 344 /* 345 * Early probe support logic for ppro memory erratum #50 346 * 347 * This is called before we do cpu ident work 348 */ 349 350 int ppro_with_ram_bug(void) 351 { 352 /* Uses data from early_cpu_detect now */ 353 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 354 boot_cpu_data.x86 == 6 && 355 boot_cpu_data.x86_model == 1 && 356 boot_cpu_data.x86_stepping < 8) { 357 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 358 return 1; 359 } 360 return 0; 361 } 362 363 static void intel_smp_check(struct cpuinfo_x86 *c) 364 { 365 /* calling is from identify_secondary_cpu() ? */ 366 if (!c->cpu_index) 367 return; 368 369 /* 370 * Mask B, Pentium, but not Pentium MMX 371 */ 372 if (c->x86 == 5 && 373 c->x86_stepping >= 1 && c->x86_stepping <= 4 && 374 c->x86_model <= 3) { 375 /* 376 * Remember we have B step Pentia with bugs 377 */ 378 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 379 "with B stepping processors.\n"); 380 } 381 } 382 383 static int forcepae; 384 static int __init forcepae_setup(char *__unused) 385 { 386 forcepae = 1; 387 return 1; 388 } 389 __setup("forcepae", forcepae_setup); 390 391 static void intel_workarounds(struct cpuinfo_x86 *c) 392 { 393 #ifdef CONFIG_X86_F00F_BUG 394 /* 395 * All models of Pentium and Pentium with MMX technology CPUs 396 * have the F0 0F bug, which lets nonprivileged users lock up the 397 * system. Announce that the fault handler will be checking for it. 398 * The Quark is also family 5, but does not have the same bug. 399 */ 400 clear_cpu_bug(c, X86_BUG_F00F); 401 if (c->x86 == 5 && c->x86_model < 9) { 402 static int f00f_workaround_enabled; 403 404 set_cpu_bug(c, X86_BUG_F00F); 405 if (!f00f_workaround_enabled) { 406 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 407 f00f_workaround_enabled = 1; 408 } 409 } 410 #endif 411 412 /* 413 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 414 * model 3 mask 3 415 */ 416 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) 417 clear_cpu_cap(c, X86_FEATURE_SEP); 418 419 /* 420 * PAE CPUID issue: many Pentium M report no PAE but may have a 421 * functionally usable PAE implementation. 422 * Forcefully enable PAE if kernel parameter "forcepae" is present. 423 */ 424 if (forcepae) { 425 pr_warn("PAE forced!\n"); 426 set_cpu_cap(c, X86_FEATURE_PAE); 427 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 428 } 429 430 /* 431 * P4 Xeon erratum 037 workaround. 432 * Hardware prefetcher may cause stale data to be loaded into the cache. 433 */ 434 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { 435 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 436 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 437 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 438 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 439 } 440 } 441 442 /* 443 * See if we have a good local APIC by checking for buggy Pentia, 444 * i.e. all B steppings and the C2 stepping of P54C when using their 445 * integrated APIC (see 11AP erratum in "Pentium Processor 446 * Specification Update"). 447 */ 448 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 449 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 450 set_cpu_bug(c, X86_BUG_11AP); 451 452 453 #ifdef CONFIG_X86_INTEL_USERCOPY 454 /* 455 * Set up the preferred alignment for movsl bulk memory moves 456 */ 457 switch (c->x86) { 458 case 4: /* 486: untested */ 459 break; 460 case 5: /* Old Pentia: untested */ 461 break; 462 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 463 movsl_mask.mask = 7; 464 break; 465 case 15: /* P4 is OK down to 8-byte alignment */ 466 movsl_mask.mask = 7; 467 break; 468 } 469 #endif 470 471 intel_smp_check(c); 472 } 473 #else 474 static void intel_workarounds(struct cpuinfo_x86 *c) 475 { 476 } 477 #endif 478 479 static void srat_detect_node(struct cpuinfo_x86 *c) 480 { 481 #ifdef CONFIG_NUMA 482 unsigned node; 483 int cpu = smp_processor_id(); 484 485 /* Don't do the funky fallback heuristics the AMD version employs 486 for now. */ 487 node = numa_cpu_node(cpu); 488 if (node == NUMA_NO_NODE || !node_online(node)) { 489 /* reuse the value from init_cpu_to_node() */ 490 node = cpu_to_node(cpu); 491 } 492 numa_set_node(cpu, node); 493 #endif 494 } 495 496 static void init_cpuid_fault(struct cpuinfo_x86 *c) 497 { 498 u64 msr; 499 500 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 501 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 502 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 503 } 504 } 505 506 static void init_intel_misc_features(struct cpuinfo_x86 *c) 507 { 508 u64 msr; 509 510 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 511 return; 512 513 /* Clear all MISC features */ 514 this_cpu_write(msr_misc_features_shadow, 0); 515 516 /* Check features and update capabilities and shadow control bits */ 517 init_cpuid_fault(c); 518 probe_xeon_phi_r3mwait(c); 519 520 msr = this_cpu_read(msr_misc_features_shadow); 521 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 522 } 523 524 static void init_intel(struct cpuinfo_x86 *c) 525 { 526 early_init_intel(c); 527 528 intel_workarounds(c); 529 530 init_intel_cacheinfo(c); 531 532 if (c->cpuid_level > 9) { 533 unsigned eax = cpuid_eax(10); 534 /* Check for version and the number of counters */ 535 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 536 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 537 } 538 539 if (cpu_has(c, X86_FEATURE_XMM2)) 540 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 541 542 if (boot_cpu_has(X86_FEATURE_DS)) { 543 unsigned int l1, l2; 544 545 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 546 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) 547 set_cpu_cap(c, X86_FEATURE_BTS); 548 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) 549 set_cpu_cap(c, X86_FEATURE_PEBS); 550 } 551 552 if (boot_cpu_has(X86_FEATURE_CLFLUSH) && 553 (c->x86_vfm == INTEL_CORE2_DUNNINGTON || 554 c->x86_vfm == INTEL_NEHALEM_EX || 555 c->x86_vfm == INTEL_WESTMERE_EX)) 556 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 557 558 if (boot_cpu_has(X86_FEATURE_MWAIT) && c->x86_vfm == INTEL_ATOM_GOLDMONT) 559 set_cpu_bug(c, X86_BUG_MONITOR); 560 561 #ifdef CONFIG_X86_64 562 if (c->x86 == 15) 563 c->x86_cache_alignment = c->x86_clflush_size * 2; 564 if (c->x86 == 6) 565 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 566 #else 567 /* 568 * Names for the Pentium II/Celeron processors 569 * detectable only by also checking the cache size. 570 * Dixon is NOT a Celeron. 571 */ 572 if (c->x86 == 6) { 573 unsigned int l2 = c->x86_cache_size; 574 char *p = NULL; 575 576 switch (c->x86_model) { 577 case 5: 578 if (l2 == 0) 579 p = "Celeron (Covington)"; 580 else if (l2 == 256) 581 p = "Mobile Pentium II (Dixon)"; 582 break; 583 584 case 6: 585 if (l2 == 128) 586 p = "Celeron (Mendocino)"; 587 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 588 p = "Celeron-A"; 589 break; 590 591 case 8: 592 if (l2 == 128) 593 p = "Celeron (Coppermine)"; 594 break; 595 } 596 597 if (p) 598 strcpy(c->x86_model_id, p); 599 } 600 601 if (c->x86 == 15) 602 set_cpu_cap(c, X86_FEATURE_P4); 603 if (c->x86 == 6) 604 set_cpu_cap(c, X86_FEATURE_P3); 605 #endif 606 607 /* Work around errata */ 608 srat_detect_node(c); 609 610 init_ia32_feat_ctl(c); 611 612 init_intel_misc_features(c); 613 614 split_lock_init(); 615 616 intel_init_thermal(c); 617 } 618 619 #ifdef CONFIG_X86_32 620 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 621 { 622 /* 623 * Intel PIII Tualatin. This comes in two flavours. 624 * One has 256kb of cache, the other 512. We have no way 625 * to determine which, so we use a boottime override 626 * for the 512kb model, and assume 256 otherwise. 627 */ 628 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 629 size = 256; 630 631 /* 632 * Intel Quark SoC X1000 contains a 4-way set associative 633 * 16K cache with a 16 byte cache line and 256 lines per tag 634 */ 635 if ((c->x86 == 5) && (c->x86_model == 9)) 636 size = 16; 637 return size; 638 } 639 #endif 640 641 #define TLB_INST_4K 0x01 642 #define TLB_INST_4M 0x02 643 #define TLB_INST_2M_4M 0x03 644 645 #define TLB_INST_ALL 0x05 646 #define TLB_INST_1G 0x06 647 648 #define TLB_DATA_4K 0x11 649 #define TLB_DATA_4M 0x12 650 #define TLB_DATA_2M_4M 0x13 651 #define TLB_DATA_4K_4M 0x14 652 653 #define TLB_DATA_1G 0x16 654 655 #define TLB_DATA0_4K 0x21 656 #define TLB_DATA0_4M 0x22 657 #define TLB_DATA0_2M_4M 0x23 658 659 #define STLB_4K 0x41 660 #define STLB_4K_2M 0x42 661 662 static const struct _tlb_table intel_tlb_table[] = { 663 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 664 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 665 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 666 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 667 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 668 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 669 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" }, 670 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 671 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 672 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 673 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 674 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 675 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 676 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 677 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 678 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 679 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 680 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 681 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 682 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 683 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, 684 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, 685 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, 686 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 687 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 688 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 689 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 690 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 691 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 692 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 693 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 694 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 695 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 696 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 697 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" }, 698 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 699 { 0x00, 0, 0 } 700 }; 701 702 static void intel_tlb_lookup(const unsigned char desc) 703 { 704 unsigned char k; 705 if (desc == 0) 706 return; 707 708 /* look up this descriptor in the table */ 709 for (k = 0; intel_tlb_table[k].descriptor != desc && 710 intel_tlb_table[k].descriptor != 0; k++) 711 ; 712 713 if (intel_tlb_table[k].tlb_type == 0) 714 return; 715 716 switch (intel_tlb_table[k].tlb_type) { 717 case STLB_4K: 718 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 719 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 720 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 721 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 722 break; 723 case STLB_4K_2M: 724 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 725 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 726 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 727 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 728 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 729 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 730 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 731 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 732 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 733 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 734 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 735 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 736 break; 737 case TLB_INST_ALL: 738 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 739 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 740 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 741 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 742 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 743 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 744 break; 745 case TLB_INST_4K: 746 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 747 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 748 break; 749 case TLB_INST_4M: 750 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 751 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 752 break; 753 case TLB_INST_2M_4M: 754 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 755 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 756 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 757 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 758 break; 759 case TLB_DATA_4K: 760 case TLB_DATA0_4K: 761 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 762 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 763 break; 764 case TLB_DATA_4M: 765 case TLB_DATA0_4M: 766 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 767 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 768 break; 769 case TLB_DATA_2M_4M: 770 case TLB_DATA0_2M_4M: 771 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 772 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 773 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 774 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 775 break; 776 case TLB_DATA_4K_4M: 777 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 778 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 779 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 780 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 781 break; 782 case TLB_DATA_1G: 783 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 784 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 785 break; 786 } 787 } 788 789 static void intel_detect_tlb(struct cpuinfo_x86 *c) 790 { 791 int i, j, n; 792 unsigned int regs[4]; 793 unsigned char *desc = (unsigned char *)regs; 794 795 if (c->cpuid_level < 2) 796 return; 797 798 /* Number of times to iterate */ 799 n = cpuid_eax(2) & 0xFF; 800 801 for (i = 0 ; i < n ; i++) { 802 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 803 804 /* If bit 31 is set, this is an unknown format */ 805 for (j = 0 ; j < 3 ; j++) 806 if (regs[j] & (1 << 31)) 807 regs[j] = 0; 808 809 /* Byte 0 is level count, not a descriptor */ 810 for (j = 1 ; j < 16 ; j++) 811 intel_tlb_lookup(desc[j]); 812 } 813 } 814 815 static const struct cpu_dev intel_cpu_dev = { 816 .c_vendor = "Intel", 817 .c_ident = { "GenuineIntel" }, 818 #ifdef CONFIG_X86_32 819 .legacy_models = { 820 { .family = 4, .model_names = 821 { 822 [0] = "486 DX-25/33", 823 [1] = "486 DX-50", 824 [2] = "486 SX", 825 [3] = "486 DX/2", 826 [4] = "486 SL", 827 [5] = "486 SX/2", 828 [7] = "486 DX/2-WB", 829 [8] = "486 DX/4", 830 [9] = "486 DX/4-WB" 831 } 832 }, 833 { .family = 5, .model_names = 834 { 835 [0] = "Pentium 60/66 A-step", 836 [1] = "Pentium 60/66", 837 [2] = "Pentium 75 - 200", 838 [3] = "OverDrive PODP5V83", 839 [4] = "Pentium MMX", 840 [7] = "Mobile Pentium 75 - 200", 841 [8] = "Mobile Pentium MMX", 842 [9] = "Quark SoC X1000", 843 } 844 }, 845 { .family = 6, .model_names = 846 { 847 [0] = "Pentium Pro A-step", 848 [1] = "Pentium Pro", 849 [3] = "Pentium II (Klamath)", 850 [4] = "Pentium II (Deschutes)", 851 [5] = "Pentium II (Deschutes)", 852 [6] = "Mobile Pentium II", 853 [7] = "Pentium III (Katmai)", 854 [8] = "Pentium III (Coppermine)", 855 [10] = "Pentium III (Cascades)", 856 [11] = "Pentium III (Tualatin)", 857 } 858 }, 859 { .family = 15, .model_names = 860 { 861 [0] = "Pentium 4 (Unknown)", 862 [1] = "Pentium 4 (Willamette)", 863 [2] = "Pentium 4 (Northwood)", 864 [4] = "Pentium 4 (Foster)", 865 [5] = "Pentium 4 (Foster)", 866 } 867 }, 868 }, 869 .legacy_cache_size = intel_size_cache, 870 #endif 871 .c_detect_tlb = intel_detect_tlb, 872 .c_early_init = early_init_intel, 873 .c_bsp_init = bsp_init_intel, 874 .c_init = init_intel, 875 .c_x86_vendor = X86_VENDOR_INTEL, 876 }; 877 878 cpu_dev_register(intel_cpu_dev); 879 880 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 881 882 /** 883 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU 884 * 885 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in 886 * a hybrid processor. If the processor is not hybrid, returns 0. 887 */ 888 u8 get_this_hybrid_cpu_type(void) 889 { 890 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 891 return 0; 892 893 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; 894 } 895 896 /** 897 * get_this_hybrid_cpu_native_id() - Get the native id of this hybrid CPU 898 * 899 * Returns the uarch native ID [23:0] of a CPU in a hybrid processor. 900 * If the processor is not hybrid, returns 0. 901 */ 902 u32 get_this_hybrid_cpu_native_id(void) 903 { 904 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 905 return 0; 906 907 return cpuid_eax(0x0000001a) & 908 (BIT_ULL(X86_HYBRID_CPU_TYPE_ID_SHIFT) - 1); 909 } 910