1 #include <linux/init.h> 2 #include <linux/kernel.h> 3 4 #include <linux/string.h> 5 #include <linux/bitops.h> 6 #include <linux/smp.h> 7 #include <linux/sched.h> 8 #include <linux/thread_info.h> 9 #include <linux/module.h> 10 11 #include <asm/processor.h> 12 #include <asm/pgtable.h> 13 #include <asm/msr.h> 14 #include <asm/uaccess.h> 15 #include <asm/ds.h> 16 #include <asm/bugs.h> 17 18 #ifdef CONFIG_X86_64 19 #include <asm/topology.h> 20 #include <asm/numa_64.h> 21 #endif 22 23 #include "cpu.h" 24 25 #ifdef CONFIG_X86_LOCAL_APIC 26 #include <asm/mpspec.h> 27 #include <asm/apic.h> 28 #include <mach_apic.h> 29 #endif 30 31 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 32 { 33 /* Unmask CPUID levels if masked: */ 34 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 35 u64 misc_enable; 36 37 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 38 39 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { 40 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; 41 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 42 c->cpuid_level = cpuid_eax(0); 43 } 44 } 45 46 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 47 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 49 50 #ifdef CONFIG_X86_64 51 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 52 #else 53 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 54 if (c->x86 == 15 && c->x86_cache_alignment == 64) 55 c->x86_cache_alignment = 128; 56 #endif 57 58 /* 59 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 60 * with P/T states and does not stop in deep C-states. 61 * 62 * It is also reliable across cores and sockets. (but not across 63 * cabinets - we turn it off in that case explicitly.) 64 */ 65 if (c->x86_power & (1 << 8)) { 66 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 67 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 68 set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE); 69 sched_clock_stable = 1; 70 } 71 72 } 73 74 #ifdef CONFIG_X86_32 75 /* 76 * Early probe support logic for ppro memory erratum #50 77 * 78 * This is called before we do cpu ident work 79 */ 80 81 int __cpuinit ppro_with_ram_bug(void) 82 { 83 /* Uses data from early_cpu_detect now */ 84 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 85 boot_cpu_data.x86 == 6 && 86 boot_cpu_data.x86_model == 1 && 87 boot_cpu_data.x86_mask < 8) { 88 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 89 return 1; 90 } 91 return 0; 92 } 93 94 #ifdef CONFIG_X86_F00F_BUG 95 static void __cpuinit trap_init_f00f_bug(void) 96 { 97 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); 98 99 /* 100 * Update the IDT descriptor and reload the IDT so that 101 * it uses the read-only mapped virtual address. 102 */ 103 idt_descr.address = fix_to_virt(FIX_F00F_IDT); 104 load_idt(&idt_descr); 105 } 106 #endif 107 108 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 109 { 110 unsigned long lo, hi; 111 112 #ifdef CONFIG_X86_F00F_BUG 113 /* 114 * All current models of Pentium and Pentium with MMX technology CPUs 115 * have the F0 0F bug, which lets nonprivileged users lock up the system. 116 * Note that the workaround only should be initialized once... 117 */ 118 c->f00f_bug = 0; 119 if (!paravirt_enabled() && c->x86 == 5) { 120 static int f00f_workaround_enabled; 121 122 c->f00f_bug = 1; 123 if (!f00f_workaround_enabled) { 124 trap_init_f00f_bug(); 125 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 126 f00f_workaround_enabled = 1; 127 } 128 } 129 #endif 130 131 /* 132 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 133 * model 3 mask 3 134 */ 135 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 136 clear_cpu_cap(c, X86_FEATURE_SEP); 137 138 /* 139 * P4 Xeon errata 037 workaround. 140 * Hardware prefetcher may cause stale data to be loaded into the cache. 141 */ 142 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 143 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); 144 if ((lo & (1<<9)) == 0) { 145 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); 146 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); 147 lo |= (1<<9); /* Disable hw prefetching */ 148 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); 149 } 150 } 151 152 /* 153 * See if we have a good local APIC by checking for buggy Pentia, 154 * i.e. all B steppings and the C2 stepping of P54C when using their 155 * integrated APIC (see 11AP erratum in "Pentium Processor 156 * Specification Update"). 157 */ 158 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && 159 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 160 set_cpu_cap(c, X86_FEATURE_11AP); 161 162 163 #ifdef CONFIG_X86_INTEL_USERCOPY 164 /* 165 * Set up the preferred alignment for movsl bulk memory moves 166 */ 167 switch (c->x86) { 168 case 4: /* 486: untested */ 169 break; 170 case 5: /* Old Pentia: untested */ 171 break; 172 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 173 movsl_mask.mask = 7; 174 break; 175 case 15: /* P4 is OK down to 8-byte alignment */ 176 movsl_mask.mask = 7; 177 break; 178 } 179 #endif 180 181 #ifdef CONFIG_X86_NUMAQ 182 numaq_tsc_disable(); 183 #endif 184 } 185 #else 186 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 187 { 188 } 189 #endif 190 191 static void __cpuinit srat_detect_node(void) 192 { 193 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 194 unsigned node; 195 int cpu = smp_processor_id(); 196 int apicid = hard_smp_processor_id(); 197 198 /* Don't do the funky fallback heuristics the AMD version employs 199 for now. */ 200 node = apicid_to_node[apicid]; 201 if (node == NUMA_NO_NODE || !node_online(node)) 202 node = first_node(node_online_map); 203 numa_set_node(cpu, node); 204 205 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); 206 #endif 207 } 208 209 /* 210 * find out the number of processor cores on the die 211 */ 212 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) 213 { 214 unsigned int eax, ebx, ecx, edx; 215 216 if (c->cpuid_level < 4) 217 return 1; 218 219 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 220 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 221 if (eax & 0x1f) 222 return ((eax >> 26) + 1); 223 else 224 return 1; 225 } 226 227 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c) 228 { 229 /* Intel VMX MSR indicated features */ 230 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 231 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 232 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 233 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 234 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 235 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 236 237 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 238 239 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 240 clear_cpu_cap(c, X86_FEATURE_VNMI); 241 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 242 clear_cpu_cap(c, X86_FEATURE_EPT); 243 clear_cpu_cap(c, X86_FEATURE_VPID); 244 245 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 246 msr_ctl = vmx_msr_high | vmx_msr_low; 247 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 248 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 249 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 250 set_cpu_cap(c, X86_FEATURE_VNMI); 251 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 252 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 253 vmx_msr_low, vmx_msr_high); 254 msr_ctl2 = vmx_msr_high | vmx_msr_low; 255 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 256 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 257 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 258 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 259 set_cpu_cap(c, X86_FEATURE_EPT); 260 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 261 set_cpu_cap(c, X86_FEATURE_VPID); 262 } 263 } 264 265 static void __cpuinit init_intel(struct cpuinfo_x86 *c) 266 { 267 unsigned int l2 = 0; 268 269 early_init_intel(c); 270 271 intel_workarounds(c); 272 273 /* 274 * Detect the extended topology information if available. This 275 * will reinitialise the initial_apicid which will be used 276 * in init_intel_cacheinfo() 277 */ 278 detect_extended_topology(c); 279 280 l2 = init_intel_cacheinfo(c); 281 if (c->cpuid_level > 9) { 282 unsigned eax = cpuid_eax(10); 283 /* Check for version and the number of counters */ 284 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 285 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 286 } 287 288 if (cpu_has_xmm2) 289 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 290 if (cpu_has_ds) { 291 unsigned int l1; 292 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 293 if (!(l1 & (1<<11))) 294 set_cpu_cap(c, X86_FEATURE_BTS); 295 if (!(l1 & (1<<12))) 296 set_cpu_cap(c, X86_FEATURE_PEBS); 297 ds_init_intel(c); 298 } 299 300 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush) 301 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR); 302 303 #ifdef CONFIG_X86_64 304 if (c->x86 == 15) 305 c->x86_cache_alignment = c->x86_clflush_size * 2; 306 if (c->x86 == 6) 307 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 308 #else 309 /* 310 * Names for the Pentium II/Celeron processors 311 * detectable only by also checking the cache size. 312 * Dixon is NOT a Celeron. 313 */ 314 if (c->x86 == 6) { 315 char *p = NULL; 316 317 switch (c->x86_model) { 318 case 5: 319 if (c->x86_mask == 0) { 320 if (l2 == 0) 321 p = "Celeron (Covington)"; 322 else if (l2 == 256) 323 p = "Mobile Pentium II (Dixon)"; 324 } 325 break; 326 327 case 6: 328 if (l2 == 128) 329 p = "Celeron (Mendocino)"; 330 else if (c->x86_mask == 0 || c->x86_mask == 5) 331 p = "Celeron-A"; 332 break; 333 334 case 8: 335 if (l2 == 128) 336 p = "Celeron (Coppermine)"; 337 break; 338 } 339 340 if (p) 341 strcpy(c->x86_model_id, p); 342 } 343 344 if (c->x86 == 15) 345 set_cpu_cap(c, X86_FEATURE_P4); 346 if (c->x86 == 6) 347 set_cpu_cap(c, X86_FEATURE_P3); 348 #endif 349 350 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 351 /* 352 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 353 * detection. 354 */ 355 c->x86_max_cores = intel_num_cpu_cores(c); 356 #ifdef CONFIG_X86_32 357 detect_ht(c); 358 #endif 359 } 360 361 /* Work around errata */ 362 srat_detect_node(); 363 364 if (cpu_has(c, X86_FEATURE_VMX)) 365 detect_vmx_virtcap(c); 366 } 367 368 #ifdef CONFIG_X86_32 369 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 370 { 371 /* 372 * Intel PIII Tualatin. This comes in two flavours. 373 * One has 256kb of cache, the other 512. We have no way 374 * to determine which, so we use a boottime override 375 * for the 512kb model, and assume 256 otherwise. 376 */ 377 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 378 size = 256; 379 return size; 380 } 381 #endif 382 383 static struct cpu_dev intel_cpu_dev __cpuinitdata = { 384 .c_vendor = "Intel", 385 .c_ident = { "GenuineIntel" }, 386 #ifdef CONFIG_X86_32 387 .c_models = { 388 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 389 { 390 [0] = "486 DX-25/33", 391 [1] = "486 DX-50", 392 [2] = "486 SX", 393 [3] = "486 DX/2", 394 [4] = "486 SL", 395 [5] = "486 SX/2", 396 [7] = "486 DX/2-WB", 397 [8] = "486 DX/4", 398 [9] = "486 DX/4-WB" 399 } 400 }, 401 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = 402 { 403 [0] = "Pentium 60/66 A-step", 404 [1] = "Pentium 60/66", 405 [2] = "Pentium 75 - 200", 406 [3] = "OverDrive PODP5V83", 407 [4] = "Pentium MMX", 408 [7] = "Mobile Pentium 75 - 200", 409 [8] = "Mobile Pentium MMX" 410 } 411 }, 412 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = 413 { 414 [0] = "Pentium Pro A-step", 415 [1] = "Pentium Pro", 416 [3] = "Pentium II (Klamath)", 417 [4] = "Pentium II (Deschutes)", 418 [5] = "Pentium II (Deschutes)", 419 [6] = "Mobile Pentium II", 420 [7] = "Pentium III (Katmai)", 421 [8] = "Pentium III (Coppermine)", 422 [10] = "Pentium III (Cascades)", 423 [11] = "Pentium III (Tualatin)", 424 } 425 }, 426 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = 427 { 428 [0] = "Pentium 4 (Unknown)", 429 [1] = "Pentium 4 (Willamette)", 430 [2] = "Pentium 4 (Northwood)", 431 [4] = "Pentium 4 (Foster)", 432 [5] = "Pentium 4 (Foster)", 433 } 434 }, 435 }, 436 .c_size_cache = intel_size_cache, 437 #endif 438 .c_early_init = early_init_intel, 439 .c_init = init_intel, 440 .c_x86_vendor = X86_VENDOR_INTEL, 441 }; 442 443 cpu_dev_register(intel_cpu_dev); 444 445