1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/bitops.h> 4 #include <linux/init.h> 5 #include <linux/kernel.h> 6 #include <linux/minmax.h> 7 #include <linux/smp.h> 8 #include <linux/string.h> 9 #include <linux/types.h> 10 11 #ifdef CONFIG_X86_64 12 #include <linux/topology.h> 13 #endif 14 15 #include <asm/bugs.h> 16 #include <asm/cpu_device_id.h> 17 #include <asm/cpufeature.h> 18 #include <asm/cpu.h> 19 #include <asm/cpuid/api.h> 20 #include <asm/hwcap2.h> 21 #include <asm/intel-family.h> 22 #include <asm/microcode.h> 23 #include <asm/msr.h> 24 #include <asm/numa.h> 25 #include <asm/resctrl.h> 26 #include <asm/thermal.h> 27 #include <asm/uaccess.h> 28 29 #include "cpu.h" 30 31 /* 32 * Processors which have self-snooping capability can handle conflicting 33 * memory type across CPUs by snooping its own cache. However, there exists 34 * CPU models in which having conflicting memory types still leads to 35 * unpredictable behavior, machine check errors, or hangs. Clear this 36 * feature to prevent its use on machines with known erratas. 37 */ 38 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) 39 { 40 switch (c->x86_vfm) { 41 case INTEL_CORE_YONAH: 42 case INTEL_CORE2_MEROM: 43 case INTEL_CORE2_MEROM_L: 44 case INTEL_CORE2_PENRYN: 45 case INTEL_CORE2_DUNNINGTON: 46 case INTEL_NEHALEM: 47 case INTEL_NEHALEM_G: 48 case INTEL_NEHALEM_EP: 49 case INTEL_NEHALEM_EX: 50 case INTEL_WESTMERE: 51 case INTEL_WESTMERE_EP: 52 case INTEL_SANDYBRIDGE: 53 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); 54 } 55 } 56 57 static bool ring3mwait_disabled __read_mostly; 58 59 static int __init ring3mwait_disable(char *__unused) 60 { 61 ring3mwait_disabled = true; 62 return 1; 63 } 64 __setup("ring3mwait=disable", ring3mwait_disable); 65 66 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 67 { 68 /* 69 * Ring 3 MONITOR/MWAIT feature cannot be detected without 70 * cpu model and family comparison. 71 */ 72 if (c->x86 != 6) 73 return; 74 switch (c->x86_vfm) { 75 case INTEL_XEON_PHI_KNL: 76 case INTEL_XEON_PHI_KNM: 77 break; 78 default: 79 return; 80 } 81 82 if (ring3mwait_disabled) 83 return; 84 85 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 86 this_cpu_or(msr_misc_features_shadow, 87 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 88 89 if (c == &boot_cpu_data) 90 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 91 } 92 93 /* 94 * Early microcode releases for the Spectre v2 mitigation were broken. 95 * Information taken from; 96 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 97 * - https://kb.vmware.com/s/article/52345 98 * - Microcode revisions observed in the wild 99 * - Release note from 20180108 microcode release 100 */ 101 struct sku_microcode { 102 u32 vfm; 103 u8 stepping; 104 u32 microcode; 105 }; 106 static const struct sku_microcode spectre_bad_microcodes[] = { 107 { INTEL_KABYLAKE, 0x0B, 0x80 }, 108 { INTEL_KABYLAKE, 0x0A, 0x80 }, 109 { INTEL_KABYLAKE, 0x09, 0x80 }, 110 { INTEL_KABYLAKE_L, 0x0A, 0x80 }, 111 { INTEL_KABYLAKE_L, 0x09, 0x80 }, 112 { INTEL_SKYLAKE_X, 0x03, 0x0100013e }, 113 { INTEL_SKYLAKE_X, 0x04, 0x0200003c }, 114 { INTEL_BROADWELL, 0x04, 0x28 }, 115 { INTEL_BROADWELL_G, 0x01, 0x1b }, 116 { INTEL_BROADWELL_D, 0x02, 0x14 }, 117 { INTEL_BROADWELL_D, 0x03, 0x07000011 }, 118 { INTEL_BROADWELL_X, 0x01, 0x0b000025 }, 119 { INTEL_HASWELL_L, 0x01, 0x21 }, 120 { INTEL_HASWELL_G, 0x01, 0x18 }, 121 { INTEL_HASWELL, 0x03, 0x23 }, 122 { INTEL_HASWELL_X, 0x02, 0x3b }, 123 { INTEL_HASWELL_X, 0x04, 0x10 }, 124 { INTEL_IVYBRIDGE_X, 0x04, 0x42a }, 125 /* Observed in the wild */ 126 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b }, 127 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 }, 128 }; 129 130 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 131 { 132 int i; 133 134 /* 135 * We know that the hypervisor lie to us on the microcode version so 136 * we may as well hope that it is running the correct version. 137 */ 138 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 139 return false; 140 141 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 142 if (c->x86_vfm == spectre_bad_microcodes[i].vfm && 143 c->x86_stepping == spectre_bad_microcodes[i].stepping) 144 return (c->microcode <= spectre_bad_microcodes[i].microcode); 145 } 146 return false; 147 } 148 149 #define MSR_IA32_TME_ACTIVATE 0x982 150 151 /* Helpers to access TME_ACTIVATE MSR */ 152 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 153 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 154 155 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 156 157 static void detect_tme_early(struct cpuinfo_x86 *c) 158 { 159 u64 tme_activate; 160 int keyid_bits; 161 162 rdmsrq(MSR_IA32_TME_ACTIVATE, tme_activate); 163 164 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 165 pr_info_once("x86/tme: not enabled by BIOS\n"); 166 clear_cpu_cap(c, X86_FEATURE_TME); 167 return; 168 } 169 pr_info_once("x86/tme: enabled by BIOS\n"); 170 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 171 if (!keyid_bits) 172 return; 173 174 /* 175 * KeyID bits are set by BIOS and can be present regardless 176 * of whether the kernel is using them. They effectively lower 177 * the number of physical address bits. 178 * 179 * Update cpuinfo_x86::x86_phys_bits accordingly. 180 */ 181 c->x86_phys_bits -= keyid_bits; 182 pr_info_once("x86/mktme: BIOS enabled: x86_phys_bits reduced by %d\n", 183 keyid_bits); 184 } 185 186 void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) 187 { 188 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 189 return; 190 191 if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) 192 return; 193 194 /* 195 * The BIOS can have limited CPUID to leaf 2, which breaks feature 196 * enumeration. Unlock it and update the maximum leaf info. 197 */ 198 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) 199 c->cpuid_level = cpuid_eax(0); 200 } 201 202 /* 203 * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 204 * structures are populated. 205 */ 206 static u32 intel_cpuid_vfm(void) 207 { 208 u32 eax = cpuid_eax(1); 209 u32 fam = x86_family(eax); 210 u32 model = x86_model(eax); 211 212 return IFM(fam, model); 213 } 214 215 u32 intel_get_platform_id(void) 216 { 217 unsigned int val[2]; 218 219 if (x86_hypervisor_present) 220 return 0; 221 222 /* 223 * This can be called early. Use CPUID directly instead of 224 * relying on cpuinfo_x86 which may not be fully initialized. 225 * The PII does not have MSR_IA32_PLATFORM_ID. Everything 226 * before _it_ has no microcode (for Linux at least). 227 */ 228 if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) 229 return 0; 230 231 /* get processor flags from MSR 0x17 */ 232 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); 233 234 return (val[1] >> 18) & 7; 235 } 236 237 static void early_init_intel(struct cpuinfo_x86 *c) 238 { 239 u64 misc_enable; 240 241 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 242 c->microcode = intel_get_microcode_revision(); 243 c->intel_platform_id = intel_get_platform_id(); 244 245 /* Now if any of them are set, check the blacklist and clear the lot */ 246 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 247 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 248 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 249 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 250 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 251 setup_clear_cpu_cap(X86_FEATURE_IBRS); 252 setup_clear_cpu_cap(X86_FEATURE_IBPB); 253 setup_clear_cpu_cap(X86_FEATURE_STIBP); 254 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 255 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 256 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 257 setup_clear_cpu_cap(X86_FEATURE_SSBD); 258 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 259 } 260 261 /* 262 * Atom erratum AAE44/AAF40/AAG38/AAH41: 263 * 264 * A race condition between speculative fetches and invalidating 265 * a large page. This is worked around in microcode, but we 266 * need the microcode to have already been loaded... so if it is 267 * not, recommend a BIOS update and disable large pages. 268 */ 269 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && 270 c->microcode < 0x20e) { 271 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 272 clear_cpu_cap(c, X86_FEATURE_PSE); 273 } 274 275 #ifndef CONFIG_X86_64 276 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 277 if (c->x86 == 15 && c->x86_cache_alignment == 64) 278 c->x86_cache_alignment = 128; 279 #endif 280 281 /* CPUID workaround for 0F33/0F34 CPU */ 282 if (c->x86_vfm == INTEL_P4_PRESCOTT && 283 (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 284 c->x86_phys_bits = 36; 285 286 /* 287 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 288 * with P/T states and does not stop in deep C-states. 289 * 290 * It is also reliable across cores and sockets. (but not across 291 * cabinets - we turn it off in that case explicitly.) 292 * 293 * Use a model-specific check for some older CPUs that have invariant 294 * TSC but may not report it architecturally via 8000_0007. 295 */ 296 if (c->x86_power & (1 << 8)) { 297 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 298 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 299 } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) || 300 (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { 301 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 302 } 303 304 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 305 switch (c->x86_vfm) { 306 case INTEL_ATOM_SALTWELL_MID: 307 case INTEL_ATOM_SALTWELL_TABLET: 308 case INTEL_ATOM_SILVERMONT_MID: 309 case INTEL_ATOM_AIRMONT_NP: 310 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 311 break; 312 } 313 314 /* 315 * PAT is broken on early family 6 CPUs, the last of which 316 * is "Yonah" where the erratum is named "AN7": 317 * 318 * Page with PAT (Page Attribute Table) Set to USWC 319 * (Uncacheable Speculative Write Combine) While 320 * Associated MTRR (Memory Type Range Register) Is UC 321 * (Uncacheable) May Consolidate to UC 322 * 323 * Disable PAT and fall back to MTRR on these CPUs. 324 */ 325 if (c->x86_vfm >= INTEL_PENTIUM_PRO && 326 c->x86_vfm <= INTEL_CORE_YONAH) 327 clear_cpu_cap(c, X86_FEATURE_PAT); 328 329 /* 330 * Modern CPUs are generally expected to have a sane fast string 331 * implementation. However, BIOSes typically have a knob to tweak 332 * the architectural MISC_ENABLE.FAST_STRING enable bit. 333 * 334 * Adhere to the preference and program the Linux-defined fast 335 * string flag and enhanced fast string capabilities accordingly. 336 */ 337 if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { 338 rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); 339 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { 340 /* X86_FEATURE_ERMS is set based on CPUID */ 341 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 342 } else { 343 pr_info("Disabled fast string operations\n"); 344 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 345 setup_clear_cpu_cap(X86_FEATURE_ERMS); 346 } 347 } 348 349 /* 350 * Intel Quark Core DevMan_001.pdf section 6.4.11 351 * "The operating system also is required to invalidate (i.e., flush) 352 * the TLB when any changes are made to any of the page table entries. 353 * The operating system must reload CR3 to cause the TLB to be flushed" 354 * 355 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 356 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE 357 * to be modified. 358 */ 359 if (c->x86_vfm == INTEL_QUARK_X1000) { 360 pr_info("Disabling PGE capability bit\n"); 361 setup_clear_cpu_cap(X86_FEATURE_PGE); 362 } 363 364 check_memory_type_self_snoop_errata(c); 365 366 /* 367 * Adjust the number of physical bits early because it affects the 368 * valid bits of the MTRR mask registers. 369 */ 370 if (cpu_has(c, X86_FEATURE_TME)) 371 detect_tme_early(c); 372 } 373 374 static void bsp_init_intel(struct cpuinfo_x86 *c) 375 { 376 resctrl_cpu_detect(c); 377 } 378 379 #ifdef CONFIG_X86_32 380 /* 381 * Early probe support logic for ppro memory erratum #50 382 * 383 * This is called before we do cpu ident work 384 */ 385 386 int ppro_with_ram_bug(void) 387 { 388 /* Uses data from early_cpu_detect now */ 389 if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && 390 boot_cpu_data.x86_stepping < 8) { 391 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 392 return 1; 393 } 394 return 0; 395 } 396 397 static void intel_smp_check(struct cpuinfo_x86 *c) 398 { 399 /* calling is from identify_secondary_cpu() ? */ 400 if (!c->cpu_index) 401 return; 402 403 /* 404 * Mask B, Pentium, but not Pentium MMX 405 */ 406 if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && 407 c->x86_stepping >= 1 && c->x86_stepping <= 4) { 408 /* 409 * Remember we have B step Pentia with bugs 410 */ 411 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 412 "with B stepping processors.\n"); 413 } 414 } 415 416 static int forcepae; 417 static int __init forcepae_setup(char *__unused) 418 { 419 forcepae = 1; 420 return 1; 421 } 422 __setup("forcepae", forcepae_setup); 423 424 static void intel_workarounds(struct cpuinfo_x86 *c) 425 { 426 /* 427 * All models of Pentium and Pentium with MMX technology CPUs 428 * have the F0 0F bug, which lets nonprivileged users lock up the 429 * system. The fault handler always checks for it. 430 * The Quark is also family 5, but does not have the same bug. 431 */ 432 if (IS_ENABLED(CONFIG_X86_F00F_BUG) && 433 (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000)) 434 set_cpu_bug(c, X86_BUG_F00F); 435 436 /* 437 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 438 * model 3 mask 3 439 */ 440 if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || 441 c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) 442 clear_cpu_cap(c, X86_FEATURE_SEP); 443 444 /* 445 * PAE CPUID issue: many Pentium M report no PAE but may have a 446 * functionally usable PAE implementation. 447 * Forcefully enable PAE if kernel parameter "forcepae" is present. 448 */ 449 if (forcepae) { 450 pr_warn("PAE forced!\n"); 451 set_cpu_cap(c, X86_FEATURE_PAE); 452 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 453 } 454 455 /* 456 * P4 Xeon erratum 037 workaround. 457 * Hardware prefetcher may cause stale data to be loaded into the cache. 458 */ 459 if (c->x86_vfm == INTEL_P4_WILLAMETTE && c->x86_stepping == 1) { 460 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 461 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 462 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 463 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 464 } 465 } 466 467 /* 468 * See if we have a good local APIC by checking for buggy Pentia, 469 * i.e. all B steppings and the C2 stepping of P54C when using their 470 * integrated APIC (see 11AP erratum in "Pentium Processor 471 * Specification Update"). 472 */ 473 if (boot_cpu_has(X86_FEATURE_APIC) && c->x86_vfm == INTEL_PENTIUM_75 && 474 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 475 set_cpu_bug(c, X86_BUG_11AP); 476 477 #ifdef CONFIG_X86_INTEL_USERCOPY 478 /* 479 * MOVSL bulk memory moves can be slow when source and dest are not 480 * both 8-byte aligned. PII/PIII only like MOVSL with 8-byte alignment. 481 * 482 * Set the preferred alignment for Pentium Pro and newer processors, as 483 * it has only been tested on these. 484 */ 485 if (c->x86_vfm >= INTEL_PENTIUM_PRO) 486 movsl_mask.mask = 7; 487 #endif 488 489 intel_smp_check(c); 490 } 491 #else 492 static void intel_workarounds(struct cpuinfo_x86 *c) 493 { 494 } 495 #endif 496 497 static void srat_detect_node(struct cpuinfo_x86 *c) 498 { 499 #ifdef CONFIG_NUMA 500 unsigned node; 501 int cpu = smp_processor_id(); 502 503 /* Don't do the funky fallback heuristics the AMD version employs 504 for now. */ 505 node = numa_cpu_node(cpu); 506 if (node == NUMA_NO_NODE || !node_online(node)) { 507 /* reuse the value from init_cpu_to_node() */ 508 node = cpu_to_node(cpu); 509 } 510 numa_set_node(cpu, node); 511 #endif 512 } 513 514 static void init_cpuid_fault(struct cpuinfo_x86 *c) 515 { 516 u64 msr; 517 518 if (!rdmsrq_safe(MSR_PLATFORM_INFO, &msr)) { 519 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 520 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 521 } 522 } 523 524 static void init_intel_misc_features(struct cpuinfo_x86 *c) 525 { 526 u64 msr; 527 528 if (rdmsrq_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 529 return; 530 531 /* Clear all MISC features */ 532 this_cpu_write(msr_misc_features_shadow, 0); 533 534 /* Check features and update capabilities and shadow control bits */ 535 init_cpuid_fault(c); 536 probe_xeon_phi_r3mwait(c); 537 538 msr = this_cpu_read(msr_misc_features_shadow); 539 wrmsrq(MSR_MISC_FEATURES_ENABLES, msr); 540 } 541 542 /* 543 * This is a list of Intel CPUs that are known to suffer from downclocking when 544 * ZMM registers (512-bit vectors) are used. On these CPUs, when the kernel 545 * executes SIMD-optimized code such as cryptography functions or CRCs, it 546 * should prefer 256-bit (YMM) code to 512-bit (ZMM) code. 547 */ 548 static const struct x86_cpu_id zmm_exclusion_list[] = { 549 X86_MATCH_VFM(INTEL_SKYLAKE_X, 0), 550 X86_MATCH_VFM(INTEL_ICELAKE_X, 0), 551 X86_MATCH_VFM(INTEL_ICELAKE_D, 0), 552 X86_MATCH_VFM(INTEL_ICELAKE, 0), 553 X86_MATCH_VFM(INTEL_ICELAKE_L, 0), 554 X86_MATCH_VFM(INTEL_ICELAKE_NNPI, 0), 555 X86_MATCH_VFM(INTEL_TIGERLAKE_L, 0), 556 X86_MATCH_VFM(INTEL_TIGERLAKE, 0), 557 /* Allow Rocket Lake and later, and Sapphire Rapids and later. */ 558 {}, 559 }; 560 561 static void init_intel(struct cpuinfo_x86 *c) 562 { 563 early_init_intel(c); 564 565 intel_workarounds(c); 566 567 init_intel_cacheinfo(c); 568 569 if (c->cpuid_level > 9) { 570 unsigned eax = cpuid_eax(10); 571 /* Check for version and the number of counters */ 572 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 573 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 574 } 575 576 if (cpu_has(c, X86_FEATURE_XMM2)) 577 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 578 579 if (boot_cpu_has(X86_FEATURE_DS)) { 580 u64 l; 581 582 rdmsrq(MSR_IA32_MISC_ENABLE, l); 583 if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) 584 set_cpu_cap(c, X86_FEATURE_BTS); 585 if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) 586 set_cpu_cap(c, X86_FEATURE_PEBS); 587 } 588 589 if (boot_cpu_has(X86_FEATURE_CLFLUSH) && 590 (c->x86_vfm == INTEL_CORE2_DUNNINGTON || 591 c->x86_vfm == INTEL_NEHALEM_EX || 592 c->x86_vfm == INTEL_WESTMERE_EX)) 593 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 594 595 if (boot_cpu_has(X86_FEATURE_MWAIT) && 596 (c->x86_vfm == INTEL_ATOM_GOLDMONT || 597 c->x86_vfm == INTEL_LUNARLAKE_M)) 598 set_cpu_bug(c, X86_BUG_MONITOR); 599 600 #ifdef CONFIG_X86_64 601 if (c->x86 == 15) 602 c->x86_cache_alignment = c->x86_clflush_size * 2; 603 #else 604 /* 605 * Names for the Pentium II/Celeron processors 606 * detectable only by also checking the cache size. 607 * Dixon is NOT a Celeron. 608 */ 609 if (c->x86 == 6) { 610 unsigned int l2 = c->x86_cache_size; 611 char *p = NULL; 612 613 switch (c->x86_model) { 614 case 5: 615 if (l2 == 0) 616 p = "Celeron (Covington)"; 617 else if (l2 == 256) 618 p = "Mobile Pentium II (Dixon)"; 619 break; 620 621 case 6: 622 if (l2 == 128) 623 p = "Celeron (Mendocino)"; 624 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 625 p = "Celeron-A"; 626 break; 627 628 case 8: 629 if (l2 == 128) 630 p = "Celeron (Coppermine)"; 631 break; 632 } 633 634 if (p) 635 strcpy(c->x86_model_id, p); 636 } 637 #endif 638 639 if (x86_match_cpu(zmm_exclusion_list)) 640 set_cpu_cap(c, X86_FEATURE_PREFER_YMM); 641 642 /* Work around errata */ 643 srat_detect_node(c); 644 645 init_ia32_feat_ctl(c); 646 647 init_intel_misc_features(c); 648 649 split_lock_init(); 650 651 intel_init_thermal(c); 652 } 653 654 #ifdef CONFIG_X86_32 655 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 656 { 657 /* 658 * Intel PIII Tualatin. This comes in two flavours. 659 * One has 256kb of cache, the other 512. We have no way 660 * to determine which, so we use a boottime override 661 * for the 512kb model, and assume 256 otherwise. 662 */ 663 if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) 664 size = 256; 665 666 /* 667 * Intel Quark SoC X1000 contains a 4-way set associative 668 * 16K cache with a 16 byte cache line and 256 lines per tag 669 */ 670 if (c->x86_vfm == INTEL_QUARK_X1000) 671 size = 16; 672 return size; 673 } 674 #endif 675 676 static void intel_tlb_lookup(const struct leaf_0x2_table *desc) 677 { 678 short entries = desc->entries; 679 680 switch (desc->t_type) { 681 case STLB_4K: 682 tlb_lli_4k = max(tlb_lli_4k, entries); 683 tlb_lld_4k = max(tlb_lld_4k, entries); 684 break; 685 case STLB_4K_2M: 686 tlb_lli_4k = max(tlb_lli_4k, entries); 687 tlb_lld_4k = max(tlb_lld_4k, entries); 688 tlb_lli_2m = max(tlb_lli_2m, entries); 689 tlb_lld_2m = max(tlb_lld_2m, entries); 690 tlb_lli_4m = max(tlb_lli_4m, entries); 691 tlb_lld_4m = max(tlb_lld_4m, entries); 692 break; 693 case TLB_INST_ALL: 694 tlb_lli_4k = max(tlb_lli_4k, entries); 695 tlb_lli_2m = max(tlb_lli_2m, entries); 696 tlb_lli_4m = max(tlb_lli_4m, entries); 697 break; 698 case TLB_INST_4K: 699 tlb_lli_4k = max(tlb_lli_4k, entries); 700 break; 701 case TLB_INST_4M: 702 tlb_lli_4m = max(tlb_lli_4m, entries); 703 break; 704 case TLB_INST_2M_4M: 705 tlb_lli_2m = max(tlb_lli_2m, entries); 706 tlb_lli_4m = max(tlb_lli_4m, entries); 707 break; 708 case TLB_DATA_4K: 709 case TLB_DATA0_4K: 710 tlb_lld_4k = max(tlb_lld_4k, entries); 711 break; 712 case TLB_DATA_4M: 713 case TLB_DATA0_4M: 714 tlb_lld_4m = max(tlb_lld_4m, entries); 715 break; 716 case TLB_DATA_2M_4M: 717 case TLB_DATA0_2M_4M: 718 tlb_lld_2m = max(tlb_lld_2m, entries); 719 tlb_lld_4m = max(tlb_lld_4m, entries); 720 break; 721 case TLB_DATA_4K_4M: 722 tlb_lld_4k = max(tlb_lld_4k, entries); 723 tlb_lld_4m = max(tlb_lld_4m, entries); 724 break; 725 case TLB_DATA_1G_2M_4M: 726 tlb_lld_2m = max(tlb_lld_2m, TLB_0x63_2M_4M_ENTRIES); 727 tlb_lld_4m = max(tlb_lld_4m, TLB_0x63_2M_4M_ENTRIES); 728 fallthrough; 729 case TLB_DATA_1G: 730 tlb_lld_1g = max(tlb_lld_1g, entries); 731 break; 732 } 733 } 734 735 static void intel_detect_tlb(struct cpuinfo_x86 *c) 736 { 737 const struct leaf_0x2_table *desc; 738 union leaf_0x2_regs regs; 739 u8 *ptr; 740 741 if (c->cpuid_level < 2) 742 return; 743 744 cpuid_leaf_0x2(®s); 745 for_each_cpuid_0x2_desc(regs, ptr, desc) 746 intel_tlb_lookup(desc); 747 } 748 749 static const struct cpu_dev intel_cpu_dev = { 750 .c_vendor = "Intel", 751 .c_ident = { "GenuineIntel" }, 752 #ifdef CONFIG_X86_32 753 .legacy_models = { 754 { .family = 4, .model_names = 755 { 756 [0] = "486 DX-25/33", 757 [1] = "486 DX-50", 758 [2] = "486 SX", 759 [3] = "486 DX/2", 760 [4] = "486 SL", 761 [5] = "486 SX/2", 762 [7] = "486 DX/2-WB", 763 [8] = "486 DX/4", 764 [9] = "486 DX/4-WB" 765 } 766 }, 767 { .family = 5, .model_names = 768 { 769 [0] = "Pentium 60/66 A-step", 770 [1] = "Pentium 60/66", 771 [2] = "Pentium 75 - 200", 772 [3] = "OverDrive PODP5V83", 773 [4] = "Pentium MMX", 774 [7] = "Mobile Pentium 75 - 200", 775 [8] = "Mobile Pentium MMX", 776 [9] = "Quark SoC X1000", 777 } 778 }, 779 { .family = 6, .model_names = 780 { 781 [0] = "Pentium Pro A-step", 782 [1] = "Pentium Pro", 783 [3] = "Pentium II (Klamath)", 784 [4] = "Pentium II (Deschutes)", 785 [5] = "Pentium II (Deschutes)", 786 [6] = "Mobile Pentium II", 787 [7] = "Pentium III (Katmai)", 788 [8] = "Pentium III (Coppermine)", 789 [10] = "Pentium III (Cascades)", 790 [11] = "Pentium III (Tualatin)", 791 } 792 }, 793 { .family = 15, .model_names = 794 { 795 [0] = "Pentium 4 (Unknown)", 796 [1] = "Pentium 4 (Willamette)", 797 [2] = "Pentium 4 (Northwood)", 798 [4] = "Pentium 4 (Foster)", 799 [5] = "Pentium 4 (Foster)", 800 } 801 }, 802 }, 803 .legacy_cache_size = intel_size_cache, 804 #endif 805 .c_detect_tlb = intel_detect_tlb, 806 .c_early_init = early_init_intel, 807 .c_bsp_init = bsp_init_intel, 808 .c_init = init_intel, 809 .c_x86_vendor = X86_VENDOR_INTEL, 810 }; 811 812 cpu_dev_register(intel_cpu_dev); 813